Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 43
System Register Organization—Intel
®
Quark Core
X1000 Core does not cause any AC faults when the effective address given in the
instruction has the proper alignment.
VM (Virtual 8086 Mode, bit 17)
The VM bit provides Virtual 8086 Mode within Protected Mode. When the VM bit is
set while the Intel
®
Quark SoC X1000 Core is in Protected Mode, the Intel
®
Quark
SoC X1000 Core switches to Virtual 8086 operation, handling segment loads and
generating exception 13 faults on privileged opcodes. The VM bit can be set only in
Protected Mode by the IRET instruction (when current privilege level = 0) and by
task switches at any privilege level. The VM bit is unaffected by POPF. PUSHF
always pushes a 0 in this bit, even when executing in Virtual 8086 Mode. The
EFLAGS image pushed during interrupt processing or saved during task switches
contains a 1 in this bit if the interrupted code was executing as a Virtual 8086 Task.
RF (Resume Flag, bit 16)
The RF flag is used in conjunction with the debug register breakpoints. It is checked
at instruction boundaries before breakpoint processing. When RF is set, it causes
any debug fault to be ignored on the next instruction. RF is then automatically
reset at the successful completion of every instruction (no faults are signaled)
except the IRET instruction, the POPF instruction, (and JMP, CALL, and INT
instructions causing a task switch). These instructions set RF to the value specified
by the memory image. For example, at the end of the breakpoint service routine,
the IRET instruction can pop an EFLAG image having the RF bit set and resume the
program's execution at the breakpoint address without generating another
breakpoint fault on the same location.
NT (Nested Task, bit 14)
The flag applies to Protected Mode. NT is set to indicate that the execution of this
task is within another task. When set, it indicates that the current nested task's
Task State Segment (TSS) has a valid back link to the previous task's TSS. This bit
is set or reset by control transfers to other tasks. The value of NT in EFLAGS is
tested by the IRET instruction to determine whether to do an inter-task return or
an intra-task return. A POPF or an IRET instruction affects the setting of this bit
according to the image popped, at any privilege level.
IOPL (Input/Output Privilege Level, bits 12-13)
This two-bit field applies to Protected Mode. IOPL indicates the numerically
maximum CPL (current privilege level) value permitted to execute I/O instructions
without generating an exception 13 fault or consulting the I/O Permission Bitmap.
It also indicates the maximum CPL value allowing alteration of the IF (INTR Enable
Flag) bit when new values are popped into the EFLAG register. POPF and IRET
instruction can alter the IOPL field when executed at CPL = 0. Task switches can
always alter the IOPL field, when the new flag image is loaded from the incoming
task's TSS.
OF (Overflow Flag, bit 11)
The OF bit is set when the operation results in a signed overflow. Signed overflow
occurs when the operation resulted in carry/borrow into the sign bit (high-order
bit) of the result but did not result in a carry/borrow out of the high-order bit, or
vice-versa. For 8-, 16-, 32-bit operations, OF is set according to overflow at bit 7,
15, and 31, respectively.
DF (Direction Flag, bit 10)
DF defines whether ESI and/or EDI registers post decrement or post increment
during the string instructions. Post increment occurs when DF is reset. Post
decrement occurs when DF is set.