Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 47
System Register Organization—Intel
®
Quark Core
4.4.1.1 Control Register 0 (CR0)
CR0, shown in Figure 13, contains 10 bits for control and status purposes. The function
of the bits in CR0 can be categorized as follows:
•Intel
®
Quark SoC X1000 Core Operating Modes: PG, PE (Table 10)
• On-Chip Cache Control Modes: CD, NW (Table 11)
• On-Chip Floating-Point Unit: NE, TS, EM, TS (Table 12 and Table 13). (Also applies
for the Intel
®
Quark SoC X1000 Core.)
• Alignment Check Control: AM
• Supervisor Write Protect: WP
Figure 13. Control Registers