Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 49
System Register Organization—Intel
®
Quark Core
reach the external bus are cache misses. Write hits with NW=1 never update main
memory. Invalidate cycles are ignored when NW=1.
AM (Alignment Mask, bit 18)
Enables automatic alignment checking when set; disables alignment checking when
clear. Alignment checking is performed only when the AM flag is set, the AC flag in
the EFLAGS register is set, CPL is 3, and the processor is operating in either
protected or virtual-8086 mode.
Setting AM=0 prevents AC faults from occurring before the Intel
®
Quark SoC
X1000 Core has created the AC interrupt service routine.
WP (Write Protect, bit 16)
When set, inhibits supervisor-level procedures from writing into read-only pages;
when clear, allows supervisor-level procedures to write into read-only pages
(regardless of the U/S bit setting). This flag facilitates implementation of the copy-
on-write method of creating a new process (forking) used by operating systems
such as UNIX.
Refer to Section 6.4.6, “Page Level Protection (R/W, U/S Bits)” on page 102.
Note: Refer to Table 12 and Table 13 for values and interpolation of NE, EM, TS, and MP bits,
in addition to the sections below.
NE (Numeric Error, bit 5)
Enables the native (internal) mechanism for reporting x87 FPU errors when set;
enables the PC-style x87 FPU error reporting mechanism when clear. When the NE
flag is clear and the IGNNE# input is asserted, x87 FPU errors are ignored. When
the NE flag is clear and the IGNNE# input is deasserted, an unmasked x87 FPU
error causes the processor to assert the FERR# pin to generate an external
interrupt and to stop instruction execution immediately before executing the next
waiting floating-point instruction or WAIT/FWAIT instruction.
The FERR# pin is intended to drive an input to an external interrupt controller (the
FERR# pin emulates the ERROR# pin of the Intel 287 and Intel 387 DX math
coprocessors). The NE flag, IGNNE# pin, and FERR# pin are used with external
logic to implement PC-style error reporting.
Refer to Section 9.2.14, “Numeric Error Reporting (FERR#, IGNNE#)” on page 159
and Section 10.3.14, “Floating-Point Error Handling for the Intel
®
Quark SoC
X1000 Core” on page 225.
For any unmasked floating-point exceptions (UFPE), the floating-point error output
pin (FERR#) is driven active.
For NE=0, the Intel
®
Quark SoC X1000 Core works in conjunction with the ignore
numeric error input (IGNNE#) and the FERR# output pins. When a UFPE occurs and
the IGNNE# input is inactive, the Intel
®
Quark SoC X1000 Core freezes
immediately before executing the next floating-point instruction. An external
interrupt controller supplies an interrupt vector when FERR# is driven active. The
UFPE is ignored if IGNNE# is active and floating-point execution continues.
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000
provides the capability to control the IGNNE# pin via a register; the default
value of the register is 1'b0.
Note: The freeze does not take place when the next instruction is one of the control
instructions FNCLEX, FNINIT, FNSAVE, FNSTENV, FNSTCW, FNSTSW, FNSTSW AX,
FNENI, FNDISI and FNSETPM. The freeze does occur when the next instruction is WAIT.
Note: For NE=1, any UFPE results in a software interrupt 16, immediately before executing
the next non-control floating-point or WAIT instruction. The ignore numeric error input
(IGNNE#) signal is ignored.