Specifications
Intel
®
Quark Core—Contents
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
6 Order Number: 329679-001US
6.3.5 Call Gates..............................................................................................87
6.3.6 Task Switching.......................................................................................88
6.3.6.1 Floating-Point Task Switching......................................................89
6.3.7 Initialization and Transition to Protected Mode............................................89
6.4 Paging..............................................................................................................91
6.4.1 Paging Concepts.....................................................................................91
6.4.2 Paging Organization................................................................................91
6.4.2.1 Page Mechanism .......................................................................91
6.4.2.2 Page Descriptor Base Register.....................................................91
6.4.2.3 Page Directory..........................................................................92
6.4.2.4 Page Tables..............................................................................92
6.4.2.5 Page Directory/Table Entries.......................................................92
6.4.2.6 Paging-Mode Modifiers ..............................................................92
6.4.3 PAE Paging ............................................................................................93
6.4.3.1 PDPTE Registers........................................................................93
6.4.3.2 Linear-Address Translation with PAE Paging ..................................94
6.4.4 #GP Faults for Intel
®
Quark SoC X1000 Core ..........................................100
6.4.5 Access Rights ......................................................................................100
6.4.5.1 SMEP Details for Intel
®
Quark SoC X1000 Core...........................101
6.4.6 Page Level Protection (R/W, U/S Bits)......................................................102
6.4.7 Page Cacheability (PWT and PCD Bits).....................................................103
6.4.8 Translation Lookaside Buffer ..................................................................103
6.4.9 Page-Fault Exceptions ..........................................................................104
6.4.10 Paging Operation..................................................................................106
6.4.11 Operating System Responsibilities...........................................................107
6.5 Virtual 8086 Environment .................................................................................107
6.5.1 Executing Programs ..............................................................................107
6.5.2 Virtual 8086 Mode Addressing Mechanism................................................108
6.5.3 Paging in Virtual Mode...........................................................................108
6.5.4 Protection and I/O Permission Bitmap......................................................109
6.5.5 Interrupt Handling ................................................................................110
6.5.6 Entering and Leaving Virtual 8086 Mode ..................................................111
6.5.6.1 Task Switches to and from Virtual 8086 Mode .............................112
6.5.6.2 Transitions Through Trap and Interrupt Gates, and IRET...............112
7.0 On-Chip Cache .........................................................................................................114
7.1 Cache Organization..........................................................................................114
7.1.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Cache ........................115
7.2 Cache Control .................................................................................................116
7.2.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Cache Control and
Operating Modes ..................................................................................116
7.3 Cache Line Fills................................................................................................117
7.4 Cache Line Invalidations...................................................................................118
7.4.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Snoop Cycles and
Write-Back Mode Invalidation.................................................................118
7.5 Cache Replacement..........................................................................................118
7.6 Page Cacheability ............................................................................................119
7.6.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core and Processor Page
Cacheability.........................................................................................121
7.7 Cache Flushing................................................................................................122
7.7.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Cache Flushing............122
7.8 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Write-Back Cache Architecture .123
7.8.1 Write-Back Cache Coherency Protocol......................................................123
7.8.2 Detecting On-Chip Write-Back Cache of the Write-Back Enhanced Intel
®
Quark SoC X1000 Core..........................................................................125
8.0 System Management Mode (SMM) Architectures ...........................................................127