Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 61
System Register Organization—Intel
®
Quark Core
Figure 22. FPU Control Word
4.5.5 FPU Control Word
The FPU provides several processing options that are selected by loading a control word
from memory into the control register. Figure 22 shows the format and encoding of
fields in the control word.
The low-order byte of the FPU control word configures the FPU error and exception
masking. Bits 5:0 of the control word contain individual masks for each of the six
exceptions that the FPU recognizes.
The high-order byte of the control word configures the FPU operating mode, including
precision and rounding.
RC (Rounding Control, bits 11:10)
RC bits provide for directed rounding and true chop, as well as the unbiased round
to nearest even mode specified in the IEEE standard. Rounding control affects only
those instructions that perform rounding at the end of the operation (and thus can
generate a precision exception); namely, FST, FSTP, FIST, all arithmetic instructions
(except FPREM, FPREM1, FXTRACT, FABS and FCHS), and all transcendental
instructions.
PC (Precision Control, bits 9:8)
PC bits can be used to set the FPU internal operating precision of the significand at
less than the default of 64 bits (extended precision). This can be useful in providing
compatibility with early generation arithmetic processors of smaller precision. PC
A5157-01
0715
P
M
U
M
O
M
Z
M
D
M
I
M
Invalid Operation
Denormalized Operand
Zero Divide
Overflow
Underflow
Precision
Exception Masks:
Reserved
Reserved
Reserved
†
Precision Control
Rounding Control
"0" after reset or FINIT;
changeable upon loading the
control word (CW). Programs
must ignore this bit.
Rounding Control:
00-Round to nearest or even
01- Round down (toward -œ)
10- Round up (toward +œ)
11- Chop (truncate toward zero)
Precision Control:
00-24 bits (single precision)
01- (reserved)
10-53 bits (double precision)
11-64 bits (extended precision)
PC
Note:
See section 4.2.7, "Compatibility," for RESERVED bits.
RC
XXXX
†
XX
See Section 4.8 for RESERVED bits.