Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
62 Order Number: 329679-001US
affects only the instructions ADD, SUB, DIV, MUL, and SQRT. For all other
instructions, either the precision is determined by the opcode or extended precision
is used.
4.6 Debug and Test Registers
4.6.1 Debug Registers
The programmer accessible debug registers in Table 19 provide on-chip support for
debugging. Debug registers DR[3:0] specify the four linear breakpoints. The Debug
control register DR7, is used to set the breakpoints and the Debug Status Register,
DR6, displays the current state of the breakpoints. The use of the Debug registers is
described in Chapter 11.0, “Debugging Support.”
4.6.2 Test Registers
The Intel
®
Quark SoC X1000 Core contains the test registers listed in Table 20. TR6
and TR7 are used to control the testing of the translation lookaside buffer. TR3, TR4
and TR5 are used for testing the on-chip cache. The use of the test registers is
discussed in Appendix B, “Testability.”
4.7 Register Accessibility
There are a few differences regarding the accessibility of the registers in Real and
Protected Mode. Table 21 summarizes these differences. See Chapter 6.0, “Protected
Mode Architecture.”
Table 19. Debug Registers
Debug Registers
Linear Breakpoint Address 0 DR0
Linear Breakpoint Address 1 DR1
Linear Breakpoint Address 2 DR2
Linear Breakpoint Address 3 DR3
Intel Reserved, Do Not Define DR4
Intel Reserved, Do Not Define DR5
Breakpoint Status DR6
Breakpoint Control DR7
Table 20. Test Registers
Test Registers
Cache Test Data TR3
Cache Test Status TR4
Cache Test Control TR5
TLB (Translation Lookaside Buffer) Test Control TR6
TLB (Translation Lookaside Buffer) Test Status TR7