Specifications

Intel
®
Quark Core—Protected Mode Architecture
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
68 Order Number: 329679-001US
6.0 Protected Mode Architecture
The full capabilities of the Intel
®
Quark SoC X1000 Core are available when it operates
in Protected Virtual Address Mode (Protected Mode). Protected Mode vastly increases
the linear address space to four Gbytes (232 bytes) and allows the processor to run
virtual memory programs of almost unlimited size (64 terabytes or 246 bytes).
Protected Mode allows the use of additional instructions that support multi-tasking
operating systems. The base architecture of the Intel
®
Quark SoC X1000 Core remains
the same and the registers, instructions, and addressing modes described in the
previous chapters are retained. The main difference between Protected Mode and Real
Mode from a programmer’s view is the increased address space and a different
addressing mechanism.
6.1 Addressing Mechanism
Like Real Mode, Protected Mode uses two components to form the logical address: a
16-bit selector is used to determine the linear base address of a segment, then the
base address is added to a 32-bit effective address to form a 32-bit linear address. The
linear address is either used as the 32-bit physical address, or if paging is enabled, the
paging mechanism maps the 32-bit linear address into a 32-bit physical address.
The difference between the two modes lies in calculating the base address. In Protected
Mode the selector is used to specify an index into an operating system defined table
(see Figure 24). The table contains the 32-bit base address of a given segment. The
physical address is formed by adding the base address obtained from the table to the
offset.
Paging provides an additional memory management mechanism that operates only in
Protected Mode. Paging provides a means of managing the very large segments of the
Intel
®
Quark SoC X1000 Core. As such, paging operates beneath segmentation. The
paging mechanism translates the protected linear address that comes from the
segmentation unit into a physical address. Figure 25 shows the complete Intel
®
Quark
SoC X1000 Core addressing mechanism with paging enabled.