Specifications
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 7
Contents—Intel
®
Quark Core
8.1 SMM Overview................................................................................................ 127
8.2 Terminology ................................................................................................... 127
8.3 System Management Interrupt Processing.......................................................... 128
8.3.1 System Management Interrupt (SMI#).................................................... 129
8.3.2 SMI# Active (SMIACT#)........................................................................ 129
8.3.3 SMRAM............................................................................................... 130
8.3.3.1 SMRAM State Save Map........................................................... 131
8.3.4 Exit From SMM..................................................................................... 133
8.4 System Management Mode Programming Model .................................................. 134
8.4.1 Entering System Management Mode ....................................................... 134
8.4.2 Processor Environment.......................................................................... 135
8.4.2.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Environment . 136
8.4.3 Executing System Management Mode Handler.......................................... 136
8.4.3.1 Exceptions and Interrupts within System Management Mode ........ 137
8.5 SMM Features................................................................................................. 138
8.5.1 SMM Revision Identifier......................................................................... 138
8.5.2 Auto Halt Restart ................................................................................. 138
8.5.3 I/O Instruction Restart.......................................................................... 139
8.5.4 SMM Base Relocation............................................................................ 140
8.6 SMM System Design Considerations................................................................... 141
8.6.1 SMRAM Interface.................................................................................. 141
8.6.2 Cache Flushes...................................................................................... 142
8.6.2.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core System
Management Mode and Cache Flushing...................................... 144
8.6.2.2 Snoop During SMM.................................................................. 146
8.6.3 A20M# Pin and SMBASE Relocation ........................................................ 146
8.6.4 Processor Reset During SMM.................................................................. 146
8.6.5 SMM and Second-Level Write Buffers ...................................................... 147
8.6.6 Nested SMI#s and I/O Restart ............................................................... 147
8.7 SMM Software Considerations ........................................................................... 147
8.7.1 SMM Code Considerations...................................................................... 147
8.7.2 Exception Handling............................................................................... 148
8.7.3 Halt During SMM.................................................................................. 148
8.7.4 Relocating SMRAM to an Address Above One Megabyte ............................. 148
9.0 Hardware Interface................................................................................................... 149
9.1 Introduction ................................................................................................... 149
9.2 Signal Descriptions.......................................................................................... 150
9.2.1 Clock (CLK)......................................................................................... 150
9.2.2 Address Bus (A[31:2], BE[3:0]#)........................................................... 150
9.2.3 Data Lines (D[31:0]) ............................................................................ 151
9.2.4 Parity ................................................................................................. 151
9.2.4.1 Data Parity Input/Outputs (DP[3:0]) ......................................... 151
9.2.4.2 Parity Status Output (PCHK#) .................................................. 151
9.2.5 Bus Cycle Definition.............................................................................. 152
9.2.5.1 M/IO#, D/C#, W/R# Outputs ................................................... 152
9.2.5.2 Bus Lock Output (LOCK#)........................................................ 152
9.2.5.3 Pseudo-Lock Output (PLOCK#) ................................................. 153
9.2.5.4 PLOCK# Floating-Point Considerations....................................... 153
9.2.6 Bus Control ......................................................................................... 153
9.2.6.1 Address Status Output (ADS#)................................................. 153
9.2.6.2 Non-Burst Ready Input (RDY#)................................................. 153
9.2.7 Burst Control....................................................................................... 154
9.2.7.1 Burst Ready Input (BRDY#) ..................................................... 154
9.2.7.2 Burst Last Output (BLAST#)..................................................... 154
9.2.8 Interrupt Signals.................................................................................. 154