Specifications
Intel
®
Quark Core—Contents
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
8 Order Number: 329679-001US
9.2.8.1 Reset Input (RESET)................................................................154
9.2.8.2 Soft Reset Input (SRESET) .......................................................155
9.2.8.3 System Management Interrupt Request Input (SMI#)..................155
9.2.8.4 System Management Mode Active Output (SMIACT#) ..................155
9.2.8.5 Maskable Interrupt Request Input (INTR) ...................................155
9.2.8.6 Non-maskable Interrupt Request Input (NMI)..............................156
9.2.8.7 Stop Clock Interrupt Request Input (STPCLK#) ...........................156
9.2.9 Bus Arbitration Signals ..........................................................................156
9.2.9.1 Bus Request Output (BREQ)......................................................156
9.2.9.2 Bus Hold Request Input (HOLD) ................................................156
9.2.9.3 Bus Hold Acknowledge Output (HLDA)........................................157
9.2.9.4 Backoff Input (BOFF#).............................................................157
9.2.10 Cache Invalidation................................................................................157
9.2.10.1 Address Hold Request Input (AHOLD) ........................................158
9.2.10.2 External Address Valid Input (EADS#)........................................158
9.2.11 Cache Control ......................................................................................158
9.2.11.1 Cache Enable Input (KEN#)......................................................158
9.2.11.2 Cache Flush Input (FLUSH#).....................................................158
9.2.12 Page Cacheability (PWT, PCD) ................................................................159
9.2.13 RESERVED#.........................................................................................159
9.2.14 Numeric Error Reporting (FERR#, IGNNE#)..............................................159
9.2.14.1 Floating-Point Error Output (FERR#)..........................................159
9.2.14.2 Ignore Numeric Error Input (IGNNE#)........................................160
9.2.15 Bus Size Control (BS16#, BS8#) ............................................................160
9.2.16 Address Bit 20 Mask (A20M#) ................................................................161
9.2.17 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Signals and Other
Enhanced Bus Features .........................................................................161
9.2.17.1 Cacheability (CACHE#) ............................................................161
9.2.17.2 Cache Flush (FLUSH#).............................................................162
9.2.17.3 Hit/Miss to a Modified Line (HITM#)...........................................162
9.2.17.4 Soft Reset (SRESET)................................................................163
9.2.17.5 Invalidation Request (INV) .......................................................163
9.2.17.6 Write-Back/Write-Through (WB/WT#)........................................164
9.2.17.7 Pseudo-Lock Output (PLOCK#)..................................................164
9.2.18 Test Signals.........................................................................................164
9.2.18.1 Test Clock (TCK) .....................................................................164
9.2.18.2 Test Mode Select (TMS) ...........................................................165
9.2.18.3 Test Data Input (TDI) ..............................................................165
9.2.18.4 Test Data Output (TDO)...........................................................165
9.3 Interrupt and Non-Maskable Interrupt Interface...................................................165
9.3.1 Interrupt Logic .....................................................................................166
9.3.2 NMI Logic ............................................................................................166
9.3.3 SMI# Logic..........................................................................................166
9.3.4 STPCLK# Logic.....................................................................................167
9.4 Write Buffers...................................................................................................167
9.4.1 Write Buffers and I/O Cycles ..................................................................169
9.4.2 Write Buffers on Locked Bus Cycles.........................................................169
9.5 Reset and Initialization.....................................................................................169
9.5.1 Floating-Point Register Values ................................................................170
9.5.2 Pin State During Reset ..........................................................................171
9.5.2.1 Controlling the CLK Signal in the Processor during Power On.........173
9.5.2.2 FERR# Pin State During Reset for Intel
®
Quark SoC X1000 Core ...173
9.5.2.3 Power Down Mode (In-circuit Emulator Support)..........................174
9.6 Clock Control ..................................................................................................174
9.6.1 Stop Grant Bus Cycles...........................................................................174
9.6.2 Pin State During Stop Grant...................................................................175