Specifications

Intel
®
Quark Core—Protected Mode Architecture
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
88 Order Number: 329679-001US
Interrupt gates and trap gates work in a similar fashion as the call gates, except there
is no copying of parameters. The only difference between trap and interrupt gates is
that control transfers through an interrupt gate disable further interrupts (i.e., the IF
bit is set to 0), and trap gates leave the interrupt status unchanged.
6.3.6 Task Switching
An important attribute of any multi-tasking/multi-user operating system is its ability to
switch between tasks or processes rapidly. The Intel
®
Quark SoC X1000 Core directly
supports this operation by providing a task switch instruction in hardware. The Intel
®
Quark SoC X1000 Core task switch operation saves the entire state of the machine (all
of the registers, address space, and a link to the previous task), loads a new execution
state, performs protection checks, and commences execution in the new task, in about
10 microseconds. Like transfer of control via gates, the task switch operation is invoked
by executing an inter-segment JMP or CALL instruction that refers to a Task State
Segment (TSS) or a task gate descriptor in the GDT or LDT. An INT n instruction,
exception, trap, or external interrupt may also invoke the task switch operation if there
is a task gate descriptor in the associated IDT descriptor slot.
The TSS descriptor points to a segment (see Figure 36) containing the entire Intel
®
Quark SoC X1000 Core execution state whereas a task gate descriptor contains a TSS
selector. Figure 38 shows a Intel
®
Quark SoC X1000 Core TSS. The limit of an Intel
®
Quark SoC X1000 Core TSS must be greater than 0064H and can be as large as
4 Gbytes. In the additional TSS space, the operating system is free to store additional
information, such as the reason the task is inactive, the time the task has spent
running, and the open files belonging to the task.
Figure 38. Intel
®
Quark Core TSS