Specifications
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 91
Protected Mode Architecture—Intel
®
Quark Core
Figure 40. GDT Descriptors for Simple System
6.4 Paging
6.4.1 Paging Concepts
Paging is another type of memory management useful for virtual memory multi-tasking
operating systems. Unlike segmentation, which modularizes programs and data into
variable length segments, paging divides programs into multiple uniform size pages.
Pages bear no direct relation to the logical structure of a program. Whereas segment
selectors can be considered the logical “name” of a program module or data structure,
a page most likely corresponds to only a portion of a module or data structure.
By taking advantage of the locality of reference displayed by most programs, only a
small number of pages from each active task need be in memory at any moment.
6.4.2 Paging Organization
6.4.2.1 Page Mechanism
The Intel
®
Quark SoC X1000 Core uses two levels of tables to translate the linear
address (from the segmentation unit) to a physical address. There are three
components to the paging mechanism of the Intel
®
Quark SoC X1000 Core: the page
directory, the page tables, and the page itself (page frame). All memory-resident
elements of the Intel
®
Quark SoC X1000 Core paging mechanism are 4 Kbytes. A
uniform size for all of the elements simplifies memory allocation and reallocation
schemes by eliminating problems with memory fragmentation.
6.4.2.2 Page Descriptor Base Register
CR2 is the Page Fault Linear Address register. It holds the 32-bit linear address that
caused the last page fault detected.
CR3 is the Page Directory Physical Base Address register. It contains the physical
starting address of the page directory. The lower 12 bits of CR3 are always zero to
ensure that the page directory is always page aligned. Loading it via a MOV CR3 reg
instruction causes the page table entry cache to be flushed, as does a task switch
through a TSS that changes the value of CR0 (see Section 6.4.8).
2
Base 31...24
00(H)
G
1
D
1
00
Limit
19.16
F(H) 1
001001
0
Base 23...16
00(H)
Data
Descriptor
Segment Base 15...0
0118(H)
Segment Base 15...0
FFFF(H)
1
Base 31...24
00(H)
G
1
D
1
00
Limit
19.16
F(H) 1
001001
1
Base 23...16
00(H)
Code
Descriptor
Segment Base 15...0
0118(H)
Segment Base 15...0
FFFF(H)
NULL DESCRIPTOR
0
31 24 16 15 8 0