Specifications

Intel
®
Quark Core—Protected Mode Architecture
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
92 Order Number: 329679-001US
6.4.2.3 Page Directory
The Page Directory is 4 Kbytes long and allows up to 1024 page directory entries. Each
page directory entry contains the address of the next level of tables, the Page Tables
and information about the page table. The upper 10 bits of the linear address
(A[31:22]) are used as an index to select the correct page directory entry.
6.4.2.4 Page Tables
Each Page Table is 4 Kbytes and holds up to 1024 page table entries. Page table entries
contain the starting address of the page frame and statistical information about the
page. Address bits A[21:12] are used as an index to select one of the 1024 page table
entries. The 20 upper-bit page frame address is concatenated with the lower 12 bits of
the linear address to form the physical address. Page tables can be shared between
tasks and swapped to disks.
6.4.2.5 Page Directory/Table Entries
The lower 12 bits of the page table entries and page directory entries contain statistical
information about pages and page tables, respectively. The P (Present) bit 0 indicates
whether a page directory or page table entry can be used in address translation. If
P = 1 the entry can be used for address translation. If P = 0 the entry cannot be used
for translation, and all other bits are available for use by the software. For example the
remaining 31 bits could be used to indicate where on the disk the page is stored.
Bit 5, the Accessed (A) bit, is set by the Intel
®
Quark SoC X1000 Core for both types of
entries before a read or write access occurs to an address covered by the entry. Bit 6,
the D (Dirty) bit, is set to 1 before a write to an address covered by that page table
entry occurs. The D bit is undefined for page directory entries. When the P, A and D bits
are updated by the Intel
®
Quark SoC X1000 Core, a read-modify-write cycle is
generated that locks the bus and prevents conflicts with other processors or
peripherals. Software that modifies these bits should use the LOCK prefix to ensure the
integrity of the page tables in multi-master systems.
The three bits marked OS Reserved (bits 11:9) are software-definable. OSs are free to
use these bits for any purpose. An example of the use of the OS Reserved bits is storing
information about page aging. By keeping track of how long a page has been in
memory since being accessed, an operating system can implement a page replacement
algorithm such as least recently used.
Bit 2, the User/Supervisor (U/S) bit, and bit 1, the Read/Write (R/W) bit, are used to
provide protection attributes for individual pages.
6.4.2.6 Paging-Mode Modifiers
Details of how each paging mode operates are determined by the following control bits:
• The WP flag in CR0 (bit 16).
• The PSE, PGE, PCIDE, and SMEP flags in CR4 (bit 4, bit 7, bit 17, and bit 20,
respectively).
• The NXE flag in the IA32_EFER MSR (bit 11).
CR0.WP allows pages to be protected from supervisor-mode writes. If CR0.WP = 0,
supervisor-mode write accesses are allowed to linear addresses with read-only access
rights; if CR0.WP = 1, they are not. (User-mode write accesses are never allowed to
linear addresses with read-only access rights, regardless of the value of CR0.WP.)