Specifications

Intel
®
Quark Core—Protected Mode Architecture
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
96 Order Number: 329679-001US
Figure 42. Linear-Address Translation to a 2-MByte Page using PAE Paging
Table 31. Format of a PAE Page-Directory Entry that Maps a 2-MByte Page
Bit Position(s) Contents
0 (P) Present; must be 1 to map a 2-MByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 2-MByte page referenced by this
entry
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte page
referenced by this entry
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the
2-MByte page referenced by this entry
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the
2-MByte page referenced by this entry
5 (A)
Accessed; indicates whether software has accessed the 2-MByte page referenced by
this entry
6 (D)
Dirty; indicates whether software has written to the 2-MByte page referenced by this
entry
7 (PS) Page size; must be 1 (otherwise, this entry references a page table; see Table 32)
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global; ignored
otherwise
11:9 Ignored
12 (PAT) Reserved for Intel
®
Quark SoC X1000 Core (must be 0)
20:13 Reserved (must be 0)
(M–1):21 Physical address of the 2-MByte page referenced by this entry
62:M Reserved (must be 0)
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from
the 2-MByte page controlled by this entry); otherwise, reserved (must be 0)