Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 97
Protected Mode Architecture—Intel
®
Quark Core
Table 32. Format of a PAE Page-Directory Entry that References a Page Table
Bit Position(s) Contents
0 (P) Present; must be 1 to map a page table
1 (R/W)
Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by this
entry
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte region
controlled by this entry
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the
page table referenced by this entry
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the
page table referenced by this entry
5 (A) Accessed; indicates whether this entry has been used for linear-address translation
6 (D) Ignored
7 (PS) Page size; must be 0 (otherwise, this entry maps a 2-MByte page; see Table 31)
11:8 Ignored
(M–1):12 Physical address of 4-KByte aligned page table referenced by this entry
62:M Reserved (must be 0)
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from
the 2-MByte region controlled by this entry); otherwise, reserved (must be 0)
Table 33. Format of a PAE Page-Table Entry that Maps a 4-KByte Page
Bit Position(s) Contents
0 (P) Present; must be 1 to map a 4-KByte page
1 (R/W)
Read/write; if 0, writes may not be allowed to the 4-KByte page referenced by this
entry
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 4-KByte page
referenced by this entry
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access
the 4-KByte page referenced by this entry
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access
the 4-KByte page referenced by this entry
5 (A)
Accessed; indicates whether software has accessed the 4-KByte page referenced
by this entry
6 (D)
Dirty; indicates whether software has written to the 4-KByte page referenced by
this entry
7 (PAT) Reserved for Intel
®
Quark SoC X1000 Core (must be 0)
8 (G)
Global; if CR4.PGE = 1, determines whether the translation is global; ignored
otherwise
11:9 Ignored
(M–1):12 Physical address of 4-KByte page referenced by this entry
62:M Reserved (must be 0)
63 (XD)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed
from the 4-KByte page controlled by this entry); otherwise, reserved (must be 0)