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Doc. No.: 332050-001

Intel® Xeon® Processor D-1500

Product Family

Datasheet- Volume 1 of 4: Integrated Platform Controller Hub

March 2015

Summary of content (608 pages)

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Intel® Xeon® Processor D-1500 Product Family Datasheet- Volume 1 of 4: Integrated Platform Controller Hub March 2015 Doc. No.
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Legal Lines and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses.
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Content 1 Introduction.....................................................................................................................24 1.1 About This Manual ....................................................................................................24 1.1.1 Chapter Descriptions .....................................................................................25 1.2 Overview .................................................................................................................
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3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 4 Serial Interrupt (D31:F0)........................................................................................... 85 3.10.1 Start Frame ................................................................................................. 86 3.10.2 Data Frames ................................................................................................ 86 3.10.3 Stop Frame .....................................................................................
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3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.17.12 Function Level Reset Support (FLR) ............................................................... 143 3.17.13 USB Overcurrent Protection .......................................................................... 143 Integrated USB 2.0 Rate Matching Hub ...................................................................... 144 3.18.1 Overview ................................................................................................... 144 3.18.
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5.2 6 5.1.12 REC—Root Error Command Register .............................................................. 197 5.1.13 CIR2314—Chipset Initialization Register 2314................................................. 197 5.1.14 CIR2320—Chipset Initialization Register 2320................................................. 197 5.1.15 TCTL—TCO Configuration Register................................................................. 197 5.1.16 D31IP—Device 31 Interrupt Pin Register ..................................
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5.2.6 5.2.7 TIRE0—Thermal Initialization Register E0 ....................................................... 223 TIRF0—Thermal Initialization Register F0........................................................ 224 6 Gigabit LAN Configuration Registers ..............................................................................225 6.1 Gigabit LAN Configuration Registers (Gigabit LAN—D25:F0) .......................................... 225 6.1.1 VID—Vendor Identification Register (Gigabit LAN—D25:F0)......
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7.2 7.3 7.4 7.5 7.6 7.7 8 7.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ................................... 244 7.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) ........................... 245 7.1.16 GC—GPIO Control Register (LPC I/F — D31:F0) .............................................. 245 7.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register (LPC I/F—D31:F0) ....... 246 7.1.18 SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) ............................. 247 7.
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7.8 7.9 7.10 8 7.7.1 NMI_SC—NMI Status and Control Register...................................................... 282 7.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) Register .............................. 283 7.7.3 PORT92—Init Register.................................................................................. 283 7.7.4 COPROC_ERR—Coprocessor Error Register ..................................................... 283 7.7.5 RST_CNT—Reset Control Register...........................................
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8.1.21 8.1.22 8.1.23 8.1.24 8.1.25 8.1.26 8.1.27 8.2 8.3 8.4 9 10 INT_PN—Interrupt Pin Register (SATA–D31:F2) .............................................. 331 IDE_TIM—IDE Timing Register (SATA–D31:F2) ............................................... 331 SIDETIM—Slave IDE Timing Register (SATA–D31:F2) ...................................... 331 SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2) ...................... 332 SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2)........................
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9.1.20 9.1.21 9.1.22 9.1.23 9.1.24 9.2 9.3 10 IDE_TIM—IDE Timing Register (SATA–D31:F5) ............................................... 378 SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F5) ....................... 378 SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F5) ........................ 378 IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F5)........................... 379 PID—PCI Power Management Capability Identification Register (SATA– D31:F5) ......................................
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10.2 10.1.37 FLR_NEXT—Function Level Reset Next Capability Pointer Register (USB EHCI—D29:F0) ........................................................................................... 406 10.1.38 FLR_CLV—Function Level Reset Capability Length and Version Register (USB EHCI—D29:F0) ................................................................................... 407 10.1.39 FLR_CTRL—Function Level Reset Control Register (USB EHCI—D29:F0) ............. 407 10.1.
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12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.1.6 12.1.7 12.1.8 12.1.9 12.2 13 VID—Vendor Identification Register (SMBus—D31:F3)...................................... 465 DID—Device Identification Register (SMBus—D31:F3) ...................................... 465 PCICMD—PCI Command Register (SMBus—D31:F3)......................................... 466 PCISTS—PCI Status Register (SMBus—D31:F3) ............................................... 466 RID—Revision Identification Register (SMBus—D31:F3) ...................
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13.1.17 PMBL—Prefetchable Memory Base and Limit Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................................................... 486 13.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) .................................................................... 486 13.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) ..................................................
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13.1.58 CEM—Correctable Error Mask Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) ..................................................................... 507 13.1.59 AECC—Advanced Error Capabilities and Control Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) ..................................................................... 507 13.1.60 RES—Root Error Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) . 508 13.1.
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15.2 15.3 15.4 16 16 15.1.22 OPMENU—Opcode Menu Configuration Register (SPI Memory Mapped Configuration Registers) .............................................................................. 530 15.1.23 BBAR—BIOS Base Address Configuration Register (SPI Memory Mapped Configuration Registers) .............................................................................. 531 15.1.24 FDOC—Flash Descriptor Observability Control Register (SPI Memory Mapped Configuration Registers) .........................
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16.1.6 16.1.7 16.1.8 16.1.9 16.1.10 16.1.11 16.1.12 16.1.13 16.1.14 16.1.15 16.1.16 16.1.17 16.1.18 16.1.19 16.1.20 16.2 17 PI— Programming Interface Register ............................................................. 547 SCC—Sub Class Code Register ...................................................................... 547 BCC—Base Class Code Register ..................................................................... 547 CLS—Cache Line Size Register .................................................
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3-9 Flow for Port Enable / Device Present Bits ......................................................................... 125 3-10 Serial Data transmitted over the SGPIO Interface .............................................................. 129 3-11 EHCI with USB 2.0 with Rate Matching Hub ....................................................................... 144 3-12 Intel® Xeon® Processor D-1500 Product Family Intel® Management Engine (Intel® ME) High-Level Block Diagram ................................
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3-47 Data Values for Slave Read Registers................................................................................ 155 3-48 Host Notify Format .........................................................................................................158 3-49 Intel® Xeon® Processor D-1500 Product Family Thermal Throttle States (T-states)................ 160 3-50 Intel® Xeon® Processor D-1500 Product Family Thermal Throttling Configuration Registers .......................................................
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17-8 IDER BAR4 Register Address Map .................................................................................... 593 17-9 Serial Port for Remote Keyboard and Text (KT) Redirection Register Address Map .................. 598 17-10KT IO/Memory Mapped Device Register Address Map ........................................................
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Revision History Revision Number 001 Description • Initial Release.
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Platform Controller Hub Features             22 PCI Express* — Up to eight PCI Express root ports — Supports PCI Express Rev 2.0 running at up to 5.0 GT/s — Ports 1-4 and 5-8 can independently be configured to support multiple port configurations — Module based Hot-Plug supported (that is, ExpressCard*) — NEW: Latency Tolerance Reporting — NEW: Optimized Buffer Flush/Fill Integrated Serial ATA Host Controller — Up to six SATA ports — Data transfer rates supported: 6.0 Gb/s, 3.
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1.05 V operation with tolerance up to 3.3 V IO 1.
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Introduction 1 Introduction 1.1 About This Manual This document is intended for Original Equipment Manufacturers and BIOS vendors creating products based on the Integrated Intel® Xeon® Processor D-1500 Product Family Logic Platform Controller Hub. See Section 1.3 for definitions and supported features).
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Introduction Table 1-1. Industry Specifications (Sheet 2 of 2) Specification Intel ® Virtualization Technology Location http://www.intel.com/technology/virtualization/index.htm SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7 http://www.intel.com/technology/virtualization/index.htm Advanced Host Controller Interface specification for Serial ATA, Revision 1.3 http://www.intel.com/technology/serialata/ahci.htm 1.1.
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Introduction Chapter 12, “SMBus Controller Registers (D31:F3)” provides a detailed description of registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 13, “PCI Express* Configuration Registers” provides a detailed description of registers that reside in the PCI Express controller. This controller resides at Device 28, Functions 0 to 7 (D28:F0-F7).
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Introduction 1.2.1 Capability Overview The following sub-sections provide an overview of Intel® Xeon® Processor D-1500 Product Family’s capabilities. PCI Express* Interface Intel® Xeon® Processor D-1500 Product Family provides up to 8 PCI Express Root Ports, supporting the PCI Express Base Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in each direction (10 GB/s concurrent).
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Introduction SPI_CS1# are used to access two separate SPI Flash components in Descriptor Mode. SPI_CS2# is dedicated only to support Trusted Platform Module (TPM) on SPI (TPM can be configured through Intel® Xeon® Processor D-1500 Product Family soft straps to operate over LPC or SPI, but no more than 1 TPM is allowed in the system). SPI_CS2# may not be used for any purpose other than TPM.
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Introduction Universal Serial Bus (USB) Controllers Intel® Xeon® Processor D-1500 Product Family contains one eXtensible Host Controller Interface (xHCI) controller and one Enhanced Host Controller Interface (EHCI) controllers. The xHCI controller is mapped as PCI D20:F0 and it supports up to 4 USB 2.0 ports of which all 4 can be configured as SuperSpeed (USB 3.0) ports. EHCI controller 1 (EHCI1) is located at D29:F0 and it supports up to 4 USB 2.0 ports. One of the USB 2.
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Introduction Enhanced Power Management Intel® Xeon® Processor D-1500 Product Family’s power management functions fully support the Advanced Configuration and Power Interface (ACPI) Specification, Revision 4.0a, and include enhanced clock control and various low-power (suspend) states (such as Suspend-to-RAM and Suspend-to-Disk). A hardware-based thermal management circuit permits software-independent entrance to low-power states.
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Introduction Intel® Xeon® Processor D-1500 Product Family SMBus also implements hardwarebased Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide addresses to all SMBus devices. Intel® Virtualization Technology for Directed I/O (Intel® VT-d) Intel® Xeon® Processor D-1500 Product Family provides hardware support for implementation of Intel Virtualization Technology with Directed I/O (Intel VT-d).
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Introduction not appear as a host accessible PCI device, but is instead almost completely performed by Firmware with minimal BIOS interaction. The Intel KVM technology feature is only available with internal graphics. IDE-R Function The IDE-R function is an IDE Redirection interface that provides client connection to management console ATA/ATAPI devices, such as hard disk drives and optical disk drives.
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Introduction Table 1-1.
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Introduction 6. This table shows the default PCI Express Function Number-to-Root Port mapping.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks 2 Intel® Xeon® Processor D1500 Product Family and System Clocks Intel® Xeon® Processor D-1500 Product Family provides a complete system clocking solution through Integrated Clocking. Intel® Xeon® Processor D-1500 Product Family-based platforms require several single-ended and differential clocks to synchronize signal operation and data propagation between system-wide interfaces, and across clock domains.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks A summary is given in the following tables; Table 2-1 shows the system clock input to Intel® Xeon® Processor D-1500 Product Family. Table 2-2 shows system clock outputs generated by Intel® Xeon® Processor D-1500 Product Family. Table 2-1. SoC Clock Inputs Clock Domain CLKIN_GND2_P/N N/A Unused. Tie each signal to GND through a 10 KΩ resistor. N/A Unused. Tie each signal to GND through a 10 KΩ resistor. CLKIN_GND4_P/N N/A Unused.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks 2.3 Functional Blocks Intel® Xeon® Processor D-1500 Product Family has 1 main PLL in which its output is divided down through Modulators and Dividers to provide great flexibility in clock source selection, configuration, and better power management. Table 2-3 describes the PLLs on Intel® Xeon® Processor D-1500 Product Family and the clock domains that are driven from the PLLs. Table 2-3.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks 2.5 Integrated Clock Controller (ICC) Registers This section describes all registers and base functionality that is related to the Integrated Clock Controller. The ICC registers are not visible using PCI Configuration access and it is not mapped to I/O memory as other devices within Intel® Xeon® Processor D-1500 Product Family.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks 2.5.1.2 SSCTRIPARAM_PCHPCIE100—100 MHz Intel® Xeon® Processor D1500 Product Family PCIe Clock SSC Triangle Register Default Value: 12404038h Bit 31:0 2.5.1.3 R/W 32-bit Description 100 MHz PCIe Clock SSC Triangle Control — R/W. This register is used for Intel® Xeon® Processor D-1500 Product Family PCIe clock SSC control. Firmware may program this field with various values when SSC is enabled.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks 2.5.1.5 DIV_FLEX4824—48 MHz and 24 MHz Single Ended FLEX Clock Divide Enable Register Default Value: Attribute: Size: 00030103h Bit 31:16 15 14:11 10:8 7:0 2.5.1.6 Description Reserved DIV_FLEX4824 Enable/Disable — R/W. This register controls the 48 MHz and 24 MHz single ended FLEX clock divider from a 96 MHz internal clock source. 0 = Enables divider 1 = Disables divider Reserved DIV_FLEX4824 Divider Selection — R/W.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks Bit 20 PCIe Clock 4 Output Clock Enable — R/W. 0 = Output is gated to a low state. 1 = Output is enabled to toggle (Default). 19 PCIe Clock 3 Output Clock Enable — R/W. 0 = Output is gated to a low state. 1 = Output is enabled to toggle (Default). 18 PCIe Clock 2 Output Clock Enable — R/W. 0 = Output is gated to a low state. 1 = Output is enabled to toggle (Default). 17 PCIe Clock 1 Output Clock Enable — R/W.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks Bit Description 12 FLEX3 Clock Buffer Resistance Selection — R/W. This parameter controls Single/Double load series resistance. 0 = 25 Ω single load usage 1 = 17 Ω double load usage (Default). 11:8 7:5 4 3:0 2.5.1.8 Reserved FLEX1 Clock Buffer Slew Rate Selection — R/W. This parameter controls slew rate of FLEX clock 3. Each bit step change corresponds to ~0.2 V/ns. 000 = 0.6 V/ns minimum 100 = 1.4 V/ns (Default) 111 = 2.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks Bit 4 3:1 0 2.5.1.9 Description CLKOUT_33MHz_1 Clock Buffer Resistance Selection — R/W. This parameter controls Single/ Double load series resistance. 0 = 25 Ω single load usage 1 = 17 Ω double load usage (Default). CLKOUT_33MHz_0 Clock Buffer Slew Rate Selection — R/W. This parameter controls slew rate of 33 MHz clock 0. Each bit step change corresponds to ~0.2 V/ns. 000 = 0.6 V/ns minimum 100 = 1.4 V/ns (Default) 111 = 2.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks Bit 3:0 2.5.1.11 Description Reserved ICCCTL—ICC Control Register Default Value: 00000008h Bit 31:5 4 2.5.1.12 R/W 32-bit Description Reserved Dynamic Power Management for 96MHz Clock Source MODIV6 — R/W. This field enables power management for all clocks that use this source to be brought down to the lowest power state when hardware detects an idle condition.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks 2.5.1.13 Bit Description 1 CLKRUN Control Enable for fixed 33 MHz Single Ended Clock Output 1 — R/W. Controls the enabling of support for CLKRUN protocol for fixed 33 MHz clock outputs. 0 = CLKRUN Control is disabled and clock is free running (Default) 1 = CLKRUN Control is enabled and clock output can be turned off 0 CLKRUN Control Enable for fixed 33 MHz Single Ended Clock Output 0 — R/W.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks Bit Description 19:16 CLKRQ# Select for CLKOUT_PCIE4_P/N — R/W. Select version of external input CLKRQ# for dynamic control of the output CLKOUT_PCIE4_P/N. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 15:12 CLKRQ# Select for CLKOUT_PCIE3_P/N — R/W. Select version of external input CLKRQ# for dynamic control of the output CLKOUT_PCIE3_P/N.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks Bit Description 3:0 CLKRQ# Select for CLKOUT_PCIE0_P/N — R/W. Select version of external input CLKRQ# for dynamic control of the output CLKOUT_PCIE0_P/N. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 2.5.1.
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Intel® Xeon® Processor D-1500 Product Family and System Clocks Bit Description 17 Enable CLKREQ# for CLKOUT_ PCIE1_P/N — R/W. Enable dynamic control of CLKOUT_ PCIE1_P/N by the mapped CLKREQ#. This register bit may be updated dynamically. 0 = Disable dynamic control of CLKOUT_ PCIE1_P/N (Default) 1 = Enable dynamic control of CLKOUT_ PCIE1_P/N 16 Enable CLKREQ# for CLKOUT_ PCIE0_P/N — R/W. Enable dynamic control of CLKOUT_ PCIE0_P/N by the mapped CLKREQ#. This register bit may be updated dynamically.
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Functional Description 3 Functional Description This chapter describes the functions and interfaces of Intel® Xeon® Processor D-1500 Product Family. 3.1 PCI-to-PCI Bridge The PCI-to-PCI bridge resides in PCI. The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the SoC. All register contents are lost when core well power is removed.
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Functional Description 3.2.1 Supported PCIe* Port Configurations PCI Express Root Ports 1–4 or Ports 5–8 can independently be configured as four x1s, two x2s, one x2 and two x1s, or one x4 port widths, as shown in Table 3-1 and Table 3-2. Function disable is covered in Section 5.1.63. Table 3-1. PCI Express* Ports 1 thru 4 - Supported Configurations Port 1 Port 2 Port 3 Port 4 x4 x2 x2 x2 x1 Table 3-2.
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Functional Description 3.2.3 Power Management 3.2.3.1 S4/S5 Support Software initiates the transition to S4/S5 by performing an I/O write to the Power Management Control register in Intel® Xeon® Processor D-1500 Product Family. After the I/O write completion has been returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet) message on its downstream link.
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Functional Description If RCTL.PIE is set, an interrupt will be generated. If RCTL.PIE is not set, a message will be sent to the power management controller so that a GPE can be set. If messages have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, an interrupt will be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state. 3.2.3.
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Functional Description Figure 3-1. Generation of SERR# to Platform 3.2.5 Hot-Plug Each root port implements a Hot-Plug controller that performs the following: • Messages to turn on/off/blink LEDs • Presence and attention button detection • Interrupt generation The root port only allows Hot-Plug with modules (such as, ExpressCard*). Edgeconnector based Hot-Plug is not supported. 3.2.5.
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Functional Description • Generates the message on the downstream port • When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/ F2/F3/F4/F5/F6/F7:Offset 58h:Bit 4) to indicate the command has completed. If SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are set, the root port generates an interrupt. The command completed register (SLSTS.CC) applies only to commands issued by software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.
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Functional Description When any of these bits are set, SMI# will be generated. These bits are set regardless of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI. 3.3 Gigabit Ethernet Controller (B0:D25:F0) Intel® Xeon® Processor D-1500 Product Family integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is compatible with the Intel® Ethernet Network Connection I127LM/V Platform LAN Connect device.
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Functional Description — VLAN support compliant with the 802.
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Functional Description 3.3.1.1 Transaction Layer The upper layer of the host architecture is the transaction layer. The transaction layer connects to the device GbE controller using an implementation specific protocol. Through this GbE controller-to-transaction-layer protocol, the application-specific parts of the device interact with the subsystem and transmit and receive requests to or from the remote agent, respectively. 3.3.1.2 Data Alignment 3.3.1.2.
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Functional Description completion status is received, the System Error bit in the PCI configuration space is set. If the system errors are enabled in configuration space, a system error is indicated on the PCI host bus. 3.3.3 Ethernet Interface The integrated GbE controller provides a complete CSMA/CD function supporting IEEE 802.3 (10 Mb/s), 802.3u (100 Mb/s) implementations. It also supports the IEEE 802.3z and 802.3ab (1000 Mb/s) implementations.
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Functional Description Both mechanisms use an internal logic signal to wake the system up. The wake-up steps are as follows: 1. Host wake event occurs (packet is not delivered to host). 2. The Platform LAN Connect Device receives a WoL packet/link status change. 3.
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Functional Description 3.3.4.1.2 ACPI Power Management Wake Up The integrated GbE controller supports ACPI Power Management based Wake ups. It can generate system wake-up events from three sources: • Receiving a Magic Packet*. • Receiving a Network Wake Up Packet. • Detecting a link change of state.
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Functional Description particular event, state, or activity that is indicated on that output. In addition, each LED can be individually configured for output polarity as well as for blinking versus nonblinking (steady-state) indication. The configuration for LED outputs is specified using the LEDCTL register. Furthermore, the hardware-default configuration for all the LED outputs, can be specified using NVM fields; thereby, supporting LED displays configurable to a particular OEM preference.
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Functional Description 2. All subsequent requests targeting the function are not claimed and will be master aborted immediately on the bus. This includes any configuration, I/O or memory cycles. However, the function will continue to accept completions targeting the function. 3.3.6.1.2 FLR Operation Function resets all configuration, I/O, and memory registers of the function except those indicated otherwise and resets all internal states of the function to the default or initial condition. 3.3.6.1.
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Functional Description Figure 3-2. LPC Interface Diagram PLT_RST# Intel Xeon Processor D-1500 Product Family 33 MHz CLK LAD[3:0] LPC Device LFRAME# LDRQ[1:0] #( Optional) LPCPD#( Optional) SMI#( Optional) 3.4.1.1 LPC Cycle Types Intel® Xeon® Processor D-1500 Product Family implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.1. Table 3-5 shows the cycle types supported by Intel® Xeon® Processor D-1500 Product Family. Table 3-5.
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Functional Description 3.4.1.2 Start Field Definition Table 3-6. Start Field Bit Definitions Bits[3:0] Encoding 0000 Start of cycle for a generic target 0010 Grant for bus master 0 0011 Grant for bus master 1 1111 Stop/Abort: End of a cycle for a target. Note: 3.4.1.3 Definition All other encodings are RESERVED. Cycle Type / Direction (CYCTYPE + DIR) Intel® Xeon® Processor D-1500 Product Family always drives Bit 0 of this field to 0.
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Functional Description 3.4.1.5 SYNC Valid values for the SYNC field are shown in Table 3-9. Table 3-9. SYNC Bit Definition Bits[3:0] Indication 0000 Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request deassertion and no more transfers desired for that channel. 0101 Short Wait: Part indicating wait-states. For bus master cycles, Intel® Xeon® Processor D-1500 Product Family does not use this encoding.
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Functional Description • A peripheral drives an invalid value. 3.4.1.9 I/O Cycles For I/O cycles targeting registers specified in Intel® Xeon® Processor D-1500 Product Family’s decode ranges, Intel® Xeon® Processor D-1500 Product Family performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers.
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Functional Description Note: Intel® Xeon® Processor D-1500 Product Family cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures.
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Functional Description The DMA controller also features refresh address generation, and auto-initialization following a DMA termination. 3.5.1 Channel Priority For priority resolution, the DMA consists of two logical channel groups: Channels 0–3 and Channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service.
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Functional Description 3.5.3 Summary of DMA Transfer Sizes Table 3-10 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. The column labeled “Current Address Increment/Decrement” indicates the number added to or taken from the Current Address register after each DMA transfer cycle.
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Functional Description 3.5.5 Software Commands There are three additional special software commands that the DMA controller can execute. The three software commands are: • Clear Byte Pointer Flip-Flop • Master Clear • Clear Mask Register They do not depend on any specific bit pattern on the data bus. 3.6 Low Pin Count (LPC) DMA DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host.
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Functional Description Figure 3-4. DMA Request Assertion through LDRQ# LCLK LDRQ# 3.6.2 Start MSB LSB ACT Start Abandoning DMA Requests DMA Requests can be de-asserted in two fashions: on error conditions by sending an LDRQ# message with the ‘ACT’ bit cleared to 0, or normally through a SYNC field during the DMA transfer. This section describes boundary conditions where the DMA request needs to be removed prior to a data transfer.
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Functional Description — The peripheral acknowledges the data with a valid SYNC. — If a 16-bit transfer, the process is repeated for the next 8 bits. 6. If a DMA writes… — Intel® Xeon® Processor D-1500 Product Family turns the bus around and waits for data. — The peripheral indicates data ready through SYNC and transfers the first byte. — If a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. 3.6.
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Functional Description When Intel® Xeon® Processor D-1500 Product Family sees one of these two encodings, it ends the DMA transfer after this byte and de-asserts the DMA request to the 8237. Therefore, if Intel® Xeon® Processor D-1500 Product Family indicated a 16bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. Intel® Xeon® Processor D-1500 Product Family does not attempt to transfer the second byte, and de-asserts the DMA request internally.
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Functional Description The peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller than what it may currently have buffered. To that end, it is recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and not rely on the 8237. 3.
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Functional Description Only two conventions need to be observed when programming the counters. First, for each counter, the control word must be written before the initial count is written. Second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). A new initial count may be written to a counter at any time without affecting the counter's programmed mode.
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Functional Description 3.7.2.1 Simple Read The first method is to perform a simple read operation. The counter is selected through Port 40h (Counter 0), 41h (Counter 1), or 42h (Counter 2). Note: Performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. However, in the case of Counter 2, the count can be stopped by writing to the GATE bit in Port 61h. 3.7.2.
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Functional Description 3.8 8259 Programmable Interrupt Controllers (PIC) (D31:F0) Intel® Xeon® Processor D-1500 Product Family incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts can include: system timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and DMA channels.
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Functional Description 3.8.1 Interrupt Handling 3.8.1.1 Generating Interrupts The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. Table 3-14 defines the IRR, ISR, and IMR. Table 3-14. Interrupt Status Registers 3.8.1.2 Bit Description IRR Interrupt Request Register.
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Functional Description 5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA# pulse. 6.
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Functional Description • For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. The slave controller compares this identification code to the value stored in its ICW3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 3.8.2.
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Functional Description Specific EOI command to the slave and then reading its ISR. If it is 0, a nonspecific EOI can also be sent to the master. 3.8.4.3 Automatic Rotation Mode (Equal Priority Devices) In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced.
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Functional Description level on the corresponding IRQ input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring. In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7 vector is returned. 3.8.4.
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Functional Description requests. In the special mask mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0. 3.8.6 Steering PCI Interrupts Intel® Xeon® Processor D-1500 Product Family can be programmed to allow PIRQA#PIRQH# to be routed internally to interrupts 3–7, 9–12, 14 or 15.
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Functional Description 3.9.2 Interrupt Mapping The I/O APIC within Intel® Xeon® Processor D-1500 Product Family supports 24 APIC interrupts. Each interrupt has its own unique vector assigned by software. The interrupt vectors are mapped as shown in the following table: Table 3-16.
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Functional Description 3.9.3 PCI / PCI Express* Message-Based Interrupts When external devices through PCI/PCI Express wish to generate an interrupt, they will send the message defined in the PCI Express* Base Specification, Revision 2.0 for generating INTA# – INTD#. These will be translated internal assertions/de-assertions of INTA# – INTD#. 3.9.
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Functional Description abnormal system behavior may occur. For example, IRQ14/15 may not be detected by Intel® Xeon® Processor D-1500 Product Family's interrupt controller. When the SATA controller is not running in Native IDE mode, IRQ14 and IRQ15 are used as special interrupts. If the SATA controller is in native mode, these interrupts can be mapped to other devices accordingly. 3.10.1 Start Frame The serial IRQ protocol has two modes of operation which affect the start frame.
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Functional Description 3.10.3 Stop Frame After all data frames, a Stop Frame is driven by Intel® Xeon® Processor D-1500 Product Family. The SERIRQ signal is driven low by Intel® Xeon® Processor D-1500 Product Family for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration register. The number of clocks determines the next mode. Table 3-17. Stop Frame Explanation Stop Frame Width 3.10.4 Next Mode 2 PCI clocks Quiet Mode.
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Functional Description Table 3-18. Data Frame Format (Sheet 2 of 2) 3.11 Data Frame # Interrupt Clocks Past Start Frame 12 IRQ11 35 13 IRQ12 38 14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR# 15 IRQ14 44 Not attached to SATA logic 16 IRQ15 47 Not attached to SATA logic 17 IOCHCK# 50 Same as ISA IOCHCK# going active.
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Functional Description 3.11.1 Update Cycles An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide chain is properly configured. During this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the RAM locations. The update cycle will start at least 488 µs after the UIP bit of register A is asserted, and the entire cycle does not take more than 1984 µs to complete.
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Functional Description 3.11.5 Clearing Battery-Backed RTC RAM Clearing CMOS RAM in a Intel® Xeon® Processor D-1500 Product Family-based platform can be done by using a jumper on RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Using RTCRST# to Clear CMOS A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of those configuration bits that reside in the RTC power well.
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Functional Description Table 3-19. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2) Bit Name Register Location Bit(s) Default State NEWCENTURY_STS TCO1 Status Register (TCO1_STS) TCOBase + 04h 7 0 Intruder Detect (INTRD_DET) TCO2 Status Register (TCO2_STS) TCOBase + 06h 0 0 Top Swap (TS) Backed Up Control Register (BUC) Chipset Config Registers:Offset 3414h 0 X Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear CMOS values.
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Functional Description 3.12.2 Intel® Xeon® Processor D-1500 Product Family and System Power States Table 3-20 shows the power states defined for INTEL® XEON® PROCESSOR D-1500 PRODUCT FAMILY-based platforms. The state names generally match the corresponding ACPI states. Table 3-20. General Power States for Systems Using Intel® Xeon® Processor D-1500 Product Family State/ Substates Legacy Name / Description G0/S0/C0 Full On: Processor operating.
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Functional Description Table 3-21. State Transition Rules for Intel® Xeon® Processor D-1500 Product Family (Sheet 2 of 2) Present State G2/S5 G2 G3 Transition Trigger Next State • Any Enabled Wake Event • G0/S0/C02 • Mechanical Off/Power Failure • G3 • • Any Enabled Wake Event Mechanical Off/Power Failure • • • G0/S0/C02 G1/S3, G1/S4 or G2/S5 (see Section 3.12.7) G3 • Power Returns • S0/C0 (reboot) or G2/S54 (stay off until power button pressed or other wake event)1,2 Notes: 1.
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Functional Description 3.12.4 SMI# / SCI Generation Upon any enabled SMI event taking place while the End of SMI (EOS) bit is set, Intel® Xeon® Processor D-1500 Product Family will clear the EOS bit and assert SMI to the processor, which will cause it to enter SMM space. SMI assertion is performed using a Virtual Legacy Wire (VLW) message. Prior system generations (those based upon legacy processors) used an actual SMI# pin.
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Functional Description Table 3-23.
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Functional Description Table 3-23.
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Functional Description 3.12.4.2 PCI Express* Hot-Plug PCI Express has a Hot-Plug mechanism and is capable of generating a SCI using the GPE1 register. It is also capable of generating an SMI. However, it is not capable of generating a wake event. 3.12.5 C-States Intel® Xeon® Processor D-1500 Product Family-based systems implement C-states by having the processor control the states.
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Functional Description 3.12.6.3 Exiting Sleep States Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state and have to be enabled using a GPIO pin before it can be used. Upon exit from Intel® Xeon® Processor D-1500 Product Family-controlled Sleep states, the WAK_STS bit is set.
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Functional Description 2. 3. 4. Reset Types include: Power Button override, Intel ME initiated power button override, Intel ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus unconditional power down, processor thermal trip, Intel® Xeon® Processor D-1500 Product Family catastrophic temperature event. When the WAKE# pin is active and the PCI Express device is enabled to wake the system, Intel® Xeon® Processor D-1500 Product Family will wake the platform.
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Functional Description Intel® Xeon® Processor D-1500 Product Family monitors both Intel® Xeon® Processor D-1500 Product Family PWROK and RSMRST# to detect for power failures. If Intel® Xeon® Processor D-1500 Product Family PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set. Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Table 3-27.
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Functional Description this case, the transition to the G2/S5 state should not depend on any particular response from the processor (such as, Messages), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable using the PWRBTN_LVL bit. Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred.
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Functional Description 3.12.7.3 PME# (PCI Power Management Event) The PME# signal comes from a PCI Express* device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME# signal goes from high to low. No event is caused when it goes from low to high. There is also an internal PME_B0 bit. This is separate from the external PME# signal and can cause the same effect. 3.12.7.
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Functional Description Note: A thermal trip event will: • Clear the PWRBTN_STS bit • Clear all the GPE0_EN register bits • Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave receiving message and not set due to SMBAlert 3.12.8 ALT Access Mode Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths.
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Functional Description Table 3-30.
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Functional Description Table 3-30.
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Functional Description Table 3-32. Register Write Accesses in ALT Access Mode I/O Address Register Write Value 08h DMA Status Register for Channels 0–3 D0h DMA Status Register for Channels 4–7 3.12.9 System Power Supplies, Planes, and Signals 3.12.9.1 Power Plane Control with SLP_S3#, SLP_S4#, SLP_A# and SLP_LAN# The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3).
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Functional Description It is required that the power associated with PCIe* have been valid for 99 ms prior to PCH_PWROK assertion in order to comply with the 100 ms PCIe 2.0 specification on PLTRST# de-assertion. Note: SYS_RESET# is recommended for implementing the system reset button. This saves external logic that is needed if the PCH_PWROK input is used. Additionally, it allows for better handling of the SMBus and processor resets and avoids improperly reporting power failures. 3.12.9.
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Functional Description Figure 3-5.
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Functional Description 3.12.9.5 SLP_WLAN# Pin Behavior Intel® Xeon® Processor D-1500 Product Family controls the voltage rails into the external wireless LAN PHY using the SLP_WLAN# pin. • The wireless LAN PHY is always powered when the Host is running. — SLP_WLAN#=’1’ whenever SLP_S3#=’1’. • If Wake on Wireless LAN (WoWLAN) is required from S4/S5 states, the host BIOS must set HOST_WLAN_PP_EN (RCBA+3318h bit 4).
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Functional Description SRTCRST# is used to reset portions of the Intel Management Engine and should not be connected to a jumper or button on the platform. The only time this signal gets asserted (driven low in combination with RTCRST#) should be when the coin cell battery is removed or not installed and the platform is in the G3 state. Pulling this signal low independently (without RTCRST# also being driven low) may cause the platform to enter an indeterminate state.
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Functional Description A reset in which the host and Intel ME partitions of the platform are reset is called a Global Reset. During a Global Reset, all Intel® Xeon® Processor D-1500 Product Family functionality is reset except RTC Power Well backed information and Suspend well status, configuration, and functional logic for controlling and reporting the reset. Intel ME and Host power back up after the power cycle period.
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Functional Description Table 3-35.
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Functional Description 3.13.1.1 Detecting a System Lockup When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch the first instruction after reset, the TCO timer times out twice and Intel® Xeon® Processor D-1500 Product Family asserts PLTRST#. 3.13.1.2 Handling an Intruder Intel® Xeon® Processor D-1500 Product Family has an input signal, INTRUDER#, that can be attached to a switch that is activated by the system’s case being open.
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Functional Description 3.13.2 TCO Modes 3.13.2.1 TCO Legacy / Compatible Mode In TCO Legacy/Compatible mode, only the host SMBus is used. The TCO Slave is connected to the host SMBus internally by default. In this mode, the Intel ME SMBus controllers are not used and should be disabled by soft strap. Figure 3-6.
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Functional Description 3.13.2.2 Advanced TCO Mode Intel® Xeon® Processor D-1500 Product Family supports the Advanced TCO mode in which SMLink0 and SMLink1 are used in addition to the host SMBus. See Figure 3-7 for more details. In this mode, the Intel ME SMBus controllers must be enabled by soft strap in the flash descriptor. SMLink1 is used for a Node Power Monitor.
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Functional Description 3.14.1 Power Wells Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some Intel® Xeon® Processor D-1500 Product Family GPIOs may be connected to pins on devices that exist in the core well.
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Functional Description • Offset 44h: GPI_IO_SEL3[95:64] • Offset 48h: GP_LVL3[95:64] • Offset 60h: GP_RST_SEL[31:0] • Offset 64h: GP_RST_SEL2[63:32] • Offset 68h: GP_RST_SEL3[95:64] Note: All other GPIO registers not listed here are not to be locked by GLE. Once these registers are locked down, they become Read-Only registers and any software writes to these registers will have no effect. To unlock the registers, the GPIO Lockdown Enable (GLE) bit is required to be cleared to ‘0’.
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Functional Description The anticipated usage model is that either Intel® Xeon® Processor D-1500 Product Family or the SIO can drive a pin low to turn off an LED. In the case of the power LED, the SIO would normally leave its corresponding pin in a high-Z state to allow the LED to turn on. In this state, Intel® Xeon® Processor D-1500 Product Family can blink the LED by driving its corresponding pin low and subsequently tri-stating the buffer.
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Functional Description 3.14.5.2 Serial Message Format In order to serialize the data onto the GPIO, an initial state of high-Z is assumed. The SIO is required to have its LED control pin in a high-Z state as well to allow Intel® Xeon® Processor D-1500 Product Family to blink the LED (refer to the reference diagram). The three components of the serial message include the sync, data, and idle fields. The sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data.
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Functional Description The MAP register, Section 9.1.27, provides the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1 (IDE controller) is hidden by software writing to the Function Disable Register (D31, F0, Offset F2h, bit 1), and its configuration registers are not used.
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Functional Description Feature Description Host & Link Initiated Power Management Capability for the host controller or device to request Partial and Slumber interface power states Staggered Spin-Up Enables the host the ability to spin up hard drives sequentially to prevent power load problems on boot Command Completion Coalescing Reduces interrupt and completion overhead by allowing a specified number of commands to complete and then generating an interrupt to process the commands 3.15.
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Functional Description 3.15.5 Hot-Plug Operation Intel® Xeon® Processor D-1500 Product Family supports Hot-Plug Surprise removal and Insertion Notification. An internal SATA port with a Mechanical Presence Switch can support PARTIAL and SLUMBER with Hot-Plug Enabled. Software can take advantage of power savings in the low power states while enabling Hot-Plug operation. Refer to chapter 7 of the AHCI specification for details. 3.15.
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Functional Description • D0 – Device is working and instantly available. • D1 – Device enters when it receives a STANdBY IMMEDIATE command. Exit latency from this state is in seconds • D3 – From the SATA device’s perspective, no different than a D1 state, in that it is entered using the STANdBY IMMEDIATE command. However, an ACPI method is also called which will reset the device and then cut its power. Each of these device states are subsets of the host controller’s D0 state.
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Functional Description 2. When the power state is D3, no interrupts may be generated, even if they are enabled. If an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as if no device is present on the cable, and power will be minimized.
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Functional Description Figure 3-9. Flow for Port Enable / Device Present Bits 3.15.9 SATA LED The SATALED# output is driven whenever the BSY bit is set in any SATA port. The SATALED# is an active-low open-drain output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive. 3.15.
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Functional Description for the associated port. See Section 7.3.1 of the AHCI Specification for more information. 3.15.11 SGPIO Signals The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED signaling. These signals are not related to SATALED#, which allows for simplified indication of SATA command activity. The SGPIO group interfaces with an external controller chip that fetches and serializes the data for driving across the SGPIO bus.
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Functional Description There are 2 different ways of resetting Intel® Xeon® Processor D-1500 Product Family’s SGPIO interface, asynchronous reset and synchronous reset. Asynchronous reset is caused by platform reset to cause the SGPIO interface to be tri-state asynchronously. Synchronous reset is caused by setting the CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will complete the existing full bit stream transmission then only tri-state all the SGPIO pins.
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Functional Description Table 3-37. Multi-activity LED Message Type Byte 3-2 Description Value (VAL): This field describes the state of each LED for a particular location. There are three LEDs that may be supported by the HBA. Each LED has 3 bits of control.
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Functional Description 3.15.11.4 SGPIO Waveform Figure 3-10.
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Functional Description 3.16 High Precision Event Timers (HPET) This function provides a set of timers that can be used by the operating system. The timers are defined such that the operating system may be able to assign specific timers to be used directly by specific applications. Each timer can be configured to cause a separate interrupt. Intel® Xeon® Processor D-1500 Product Family provides eight timers.
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Functional Description Mapping Option #2 (Standard Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The interrupts can be routed to various interrupts in the 8259 or I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a timer is set for edge-triggered mode, the timers should not be shared with any legacy interrupts.
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Functional Description The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts. 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_VAL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_VAL register. 5. Software sets the ENABLE_CNF bit to enable interrupts.
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Functional Description 3.16.6 Handling Interrupts If each timer has a unique interrupt and the timer has been configured for edgetriggered mode, then there are no specific steps required. No read is required to process the interrupt. If a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. This is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared.
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Functional Description 3.17.1 EHC Initialization The following descriptions step through the expected Intel® Xeon® Processor D-1500 Product Family Enhanced Host Controller (EHC) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. 3.17.1.1 BIOS Initialization BIOS performs a number of platform customization steps after the core well has powered up.
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Functional Description Intel® Xeon® Processor D-1500 Product Family always performs any currentlypending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. If there is time left in the microframe, then the EHC performs any pending asynchronous traffic until the end of the microframe (EOF1). The debug port traffic is only presented on Port 1 and Port 9, while the other ports are idle during this time. 3.17.
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Functional Description accesses to that control structure do not fail the late-start test, then the “Missed Microframe” bit will get set and written back. 3.17.6.1 Aborts on USB 2.0-Initiated Memory Reads If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs: • The Host System Error status bit is set. • The DMA engines are halted after completing up to one more transaction on the USB interface.
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Functional Description 1. The EHC hardware does not inherently consume any more power when it is in the D0 state than it does in the D3 state. However, software is required to suspend or disable all ports prior to entering the D3 state such that the maximum power consumption is reduced. 2. In the D0 state, all implemented EHC features are enabled. 3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.
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Functional Description • Allows normal system USB 2.0 traffic in a system that may only have one USB port. • Debug Port device (DPD) must be high-speed capable and connect directly to Port 1 on Intel® Xeon® Processor D-1500 Product Family-based systems (such as, the DPD cannot be connected to Port 1 through a hub. When a DPD is detected Intel® Xeon® Processor D-1500 Product Family EHCI will bypass the integrated Rate Matching Hub and connect directly to the port and the DPD.).
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Functional Description Table 3-39. Debug Port Behavior OWNER_CNT ENABLED_CT Port Enable Run / Stop Suspend 0 X X X X Debug port is not being used. Normal operation. 1 0 X X X Debug port is not being used. Normal operation. 1 1 0 0 X Debug port in Mode 1. SYNC keepalives sent plus debug traffic 1 1 0 1 X Debug port in Mode 2. SOF (and only SOF) is sent as keepalive. Debug traffic is also sent. No other normal traffic is sent out this port, because the port is not enabled.
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Functional Description — SEND_PID_CNT field — The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER — 16-bit CRC NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be included in the packet. 4. After sending the data packet, the controller waits for a handshake response from the debug device. — If a handshake is received, the debug port controller: a. Places the received PID in the RECEIVED_PID_STS field b. Resets the ERROR_GOOD#_STS bit c.
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Functional Description — The DATA_LEN_CNT field is updated to show the number of bytes that were received after the PID. 4. If a valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: — Resets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit 5.
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Functional Description clearing the Port Reset bit. Due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. Software must not continue until this bit reads 0. If a high-speed device is attached, the EHCI will automatically set the Port Enabled/ Disabled bit in the PORTSC register and the debug software can proceed.
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Functional Description 3.17.12 Function Level Reset Support (FLR) The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform.
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Functional Description It is system BIOS’ responsibility to ensure that each port is mapped to only one over current pin. Operation with more than one overcurrent pin mapped to a port is undefined. It is expected that multiple ports are mapped to a single overcurrent pin, however they should be connected at the port and not at Intel® Xeon® Processor D1500 Product Family pin. Shorting these pins together may lead to reduced test capabilities. By default, two ports are routed to each of the OC[6:0]# pins.
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Functional Description 2. The Hub Controller provides the mechanism for host-to-hub communication. Hubspecific status and control commands permit the host to configure a hub and to monitor and control its individual downstream facing ports. 3. The Transaction Translator (TT) responds to high-speed split transactions and translates them to full-/low-speed transactions with full-/low-speed devices attached on downstream facing ports. There is 1 TT per RMH in Intel® Xeon® Processor D-1500 Product Family.
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Functional Description different SMBus command protocols and is controlled by the host controller. Intel® Xeon® Processor D-1500 Product Family’s SMBus controller logic is clocked by RTC clock. The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the Host Notify command (which is actually a received message).
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Functional Description 3.20.1.1 Command Protocols In all of the following commands, the Host Status Register (offset 00h) is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set in the Host Status Register. If the device does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set.
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Functional Description When programmed for the Process Call command, Intel® Xeon® Processor D-1500 Product Family transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers. The Process Call command with I2C_EN set and the PEC_EN bit set produces undefined results. Software must force either I2C_EN or PEC_EN to 0 when running this command. See Section 5.5.
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Functional Description I2C Read This command allows Intel® Xeon® Processor D-1500 Product Family to perform block reads to certain I2C* devices, such as serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I2C “Combined Format” that has data bytes after the address. Typically these data bytes correspond to an offset (address) within the serial memory chips.
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Functional Description The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit. The next byte is the read byte count (N), which may differ from the write byte count (M). The read byte count (N) cannot be 0. The combined data payload must not exceed 32 bytes.
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Functional Description 3.20.3 Bus Timing 3.20.3.1 Clock Stretching Some devices may not be able to handle their clock toggling at the rate that Intel® Xeon® Processor D-1500 Product Family as an SMBus master would like. They have the capability of stretching the low time of the clock. When Intel® Xeon® Processor D1500 Product Family attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time.
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Functional Description Table 3-42. Enables for SMBus Slave Write and SMBus Host Events INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) Slave Write to Wake/SMI# Command X X Wake generated when asleep. Slave SMI# generated when awake (SMBUS_SMI_STS).
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Functional Description Intel® Xeon® Processor D-1500 Product Family to decode cycles, and allows an external microcontroller to perform specific actions. Key features and capabilities include: • Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify. • Receive Slave Address register: This is the address that Intel® Xeon® Processor D1500 Product Family decodes.
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Functional Description Table 3-44. Slave Write Registers (Sheet 2 of 2) Register 6–7 Note: Function Reserved 8 Reserved 9–FFh Reserved The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. Intel® Xeon® Processor D-1500 Product Family overwrites the old value with any new value received.
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Functional Description Table 3-46.
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Functional Description Table 3-47. Data Values for Slave Read Registers (Sheet 2 of 2) Register Bits 4 0 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. 1 1 = BTI Temperature Event occurred. This bit will be set if Intel® Xeon® Processor D-1500 Product Family THRM# input signal is active. Else this bit will read “0.” 2 DOA Processor Status. This bit will be 1 to indicate that the processor is dead 3 1 = SECOND_TO_STS bit set.
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Functional Description is illegal for SMBus Read or Write protocol), and the address matches Intel® Xeon® Processor D-1500 Product Family’s Slave Address, Intel® Xeon® Processor D-1500 Product Family will still grab the cycle. Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address– Read sequence beginning at Bit 20.
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Functional Description Table 3-48.
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Functional Description provide incrementally more aggressive actions. Aux and Aux2 trip points are fully Software programmable during system runtime. Aux2 trip point is set below the Aux temperature trip point. Hot Temperature Trip Point This trip point may be set dynamically if desired and provides an interrupt to ACPI (or other software) when it is crossed in either direction. Software could optionally set this as an Interrupt when the temperature exceeds this level setting.
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Functional Description 3.21.1.1.2 Thermal Sensor Accuracy (Taccuracy) Taccuracy for Intel® Xeon® Processor D-1500 Product Family is ±5 °C in the temperature range 90 °C to 120 °C. Taccuracy is ±10 °C for temperatures from 45 °C – 90 °C. Intel® Xeon® Processor D-1500 Product Family may not operate above +108 °C. This value is based on product characterization and is not ensured by manufacturing test.
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Functional Description 3.21.3 Thermal Reporting Over System Management Link 1 Interface (SMLink0) SMLink0 interface in Intel® Xeon® Processor D-1500 Product Family is the SMBus link to an optional external controller. A SMBus protocol is defined on Intel® Xeon® Processor D-1500 Product Family to allow compatible devices such as Embedded Controller (EC) or SIO to obtain system thermal data from Intel® Xeon® Processor D1500 Product Family sensors using the SMLink0 interface.
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Functional Description • Writes are not allowed to this address, and result in indeterminate behavior. • Packet Error Code (PEC) may be enabled or not, which is set up by BIOS. 3.21.3.2 Block Read Command The external controller may read thermal information from Intel® Xeon® Processor D1500 Product Family using the SMBus Block Read Command. Byte-read and Word-read SMBus commands are not supported. The reads use a different address than the writes.
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Functional Description The comparator checks if the device is within the specified range, including the limits. For example, a device that is at 100 degrees when the upper limit is 100 will not trigger the alert. Likewise, a device that is at 70 degrees when the lower limit is 70 will not trigger the alert. The compares are done only on devices that have been enabled by BIOS for checking.
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Functional Description • Setting up the temperature calculation equations. 3.21.3.7 SMBus Rules Intel® Xeon® Processor D-1500 Product Family may NACK an incoming SMBus transaction. In certain cases Intel® Xeon® Processor D-1500 Product Family will NACK the address, and in other cases it will NACK the command depending on internal conditions (such as errors, busy conditions).
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Functional Description a. Intel® Xeon® Processor D-1500 Product Family will not respond to any SMBus activity (on SMLink0 interface) until it has loaded the thermal Firmware (FW), which in general would take 1–4 ms. During this period, Intel® Xeon® Processor D-1500 Product Family will NACK any SMBus transaction from the external controller. b. The load should take 1-4 ms, but the external controller should design for 30 seconds based on long delays for S4 resume which takes longer than normal power up.
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Functional Description 5. When Intel® Xeon® Processor D-1500 Product Family updates the Block Read data structure, the external controller gets a NACK during this period. a. To ensure atomicity of the SMBus data read with respect to the data itself, when the data buffer is being updated, Intel® Xeon® Processor D-1500 Product Family will NACK the Block Read transaction. b. The update is only a few micro-seconds, so very short in terms of SMBus polling time; therefore, the next read should be successful.
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Functional Description — Integration into I/O subsystem of Intel® Xeon® Processor D-1500 Product Family — Delivery of advanced I/O functions • Security — More secure (Intel root of trust) & isolated execution — Increased security of flash file system • Modularity & Partitioning — OSV, VMM & SW Independence — Rapid response to competitive changes • Power — Always On Always Connected — Advanced functions in low power S4-S5 operation — OS independent PM & thermal heuristics Intel to high-level ME FW provides
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Functional Description • The SPI flash device stores Intel ME Firmware code that is executed by the Intel ME for its operations. Intel® Xeon® Processor D-1500 Product Family controls the flash device through the SPI interface and internal logic. • In the M0 power state, the Intel ME FW code is loaded from SPI flash into DRAM and cached in secure and isolated SRAM. In order to interface with DRAM, the Intel ME utilizes the integrated memory controller (IMC).
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Functional Description Intel® Xeon® Processor D-1500 Product Family adds third chip select SPI_CS2# for TPM support over SPI. TPM Bus will use SPI_CLK, SPI_MISO, SPI_MOSI and SPI_CS2# SPI signals. Note: Communication on the SPI bus is done with a Master – Slave protocol. The Slave is connected to Intel® Xeon® Processor D-1500 Product Family and is implemented as a tri-state bus.If Boot BIOS Strap =’00’ then LPC is selected as the location for BIOS.
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Functional Description Only three masters can access the four regions: Host processor running BIOS code, Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and Intel Management Engine. The Flash Descriptor is in Region 0 and it must be located in the first sector of Device 0 (Offset 0). Flash Region Sizes SPI flash space requirements differ by platform and configuration. The Flash Descriptor requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks.
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Functional Description Figure 3-13. Flash Descriptor Sections 4KB OEM Section Descriptor Upper MAP Management Engine VSCC Table Reserved Soft Straps Master Region Component Descriptor MAP 10 h Signature 1. The Flash signature selects Descriptor Mode as well as verifies if the flash is programmed and functioning. The data at the bottom of the flash (offset 10h) must be 0FF0A55Ah in order to be in Descriptor mode. 2.
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Functional Description 4. The Region section points to the three other regions as well as the size of each region. 5. The master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master by a requestor ID. See Section 3.23.2.1 for more information. 6. The processor and Intel® Xeon® Processor D-1500 Product Family soft strap sections contain processor and Intel® Xeon® Processor D-1500 Product Family configurable parameters. 7.
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Functional Description — Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet controller. Gigabit Ethernet software must use Program Registers to access the Gigabit Ethernet region.
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Functional Description 3.23.4.1 Intel® Xeon® Processor D-1500 Product Family SPI Based BIOS Requirements A serial flash device must meet the following minimum requirements when used explicitly for system BIOS storage. • Erase size capability of at least one of the following: 64 Kbytes, 8 Kbytes, 4 Kbytes, or 256 bytes. • Device must support multiple writes to a page without requiring a preceding erase cycle (Refer to Section 3.23.
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Functional Description • Flash part must be uniform 4-KB erasable block throughout the entire device or have 64 KB blocks with the first block (lowest address) divided into 4-KB or 8-KB blocks. • Write protection scheme must meet SPI flash unlocking requirements for Intel ME. 3.23.4.3.
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Functional Description 3.23.4.4.1 Single Input, Dual Output Fast Read Intel® Xeon® Processor D-1500 Product Family now supports the functionality of a single input, dual output fast read. Opcode and address phase are shifted in serially to the serial flash SI (Serial In) pin. Data is read out after 8 clocks (dummy bits or wait states) from the both the SI and SO pin effectively doubling the through put of each fast read output.
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Functional Description Both mechanisms are logically OR’d together such that if any of the mechanisms indicate that the access should be blocked, then it is blocked. Table 3-54 provides a summary of the mechanisms. Table 3-54.
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Functional Description Table 3-55. Recommended Pinout for 8-Pin Serial Flash Device Pin # Signal 1 Chips Select 2 Data Output 3 Write Protect 4 Ground 5 Data Input 6 Serial Clock 7 Hold / Reset 8 Supply Voltage Although an 8-pin device is preferred over a 16-pin device due to footprint compatibility, the following table contains the recommended serial flash device pin-out for a 16-pin SOIC. 3.23.8 Serial Flash Device Package Table 3-56.
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Functional Description • The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket that is land pattern compatible with the wide body SO8 package. • The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8 (200 mil) packages. The 16-pin device is supported in the SO16 (300 mil) package. 3.23.9 PWM Outputs This signal is driven as open-drain.
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Functional Description 3.25 Intel® Virtualization Technology (Intel® VT) Intel Virtualization Technology (Intel VT) makes a single system appear as multiple independent systems to software. This allows for multiple, independent operating systems to be running simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
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Functional Description PCI Express defines a form of device hot reset which can be initiated through the Bridge Control register of the root/switch port to which the device is attached. However, the hot reset cannot be applied selectively to specific device functions. Also, no similar standard functionality exists for resetting root-complex integrated devices.
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Register and Memory Mapping 4 Register and Memory Mapping Intel® Xeon® Processor D-1500 Product Family contains registers that are located in the processor I/O space and memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter describes Intel® Xeon® Processor D-1500 Product Family I/O and memory maps at the register-set level. Register access is also described.
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Register and Memory Mapping Bold 4.1 Register bits that are highlighted in bold text indicate that the bit is implemented in Intel® Xeon® Processor D-1500 Product Family. Register bits that are not implemented or are hardwired will remain in plain text. PCI Devices and Functions Intel® Xeon® Processor D-1500 Product Family incorporates a variety of PCI devices and functions, as shown in Table 4-1. Device Functions can individually be disabled.
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Register and Memory Mapping 4.2 PCI Configuration Map Each PCI function on Intel® Xeon® Processor D-1500 Product Family has a set of PCI configuration registers. The register address map tables for these register sets are included at the beginning of the chapter for the particular function. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification, Revision 2.3.
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Register and Memory Mapping Table 4-2.
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Register and Memory Mapping Table 4-2.
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Register and Memory Mapping Table 4-3.
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Register and Memory Mapping Table 4-4.
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Register and Memory Mapping Table 4-4. Memory Decode Ranges from Processor Perspective (Sheet 3 of 3) Memory Range Target Dependency/Comments 2 KB anywhere above 64 KB to 4 GB range SATA Host Controller #1 AHCI memory-mapped registers.
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Register and Memory Mapping The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the Top Swap bit.
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Chipset Configuration Registers 5 Chipset Configuration Registers This section describes all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, USB, or PCI Express*). It contains the root complex register block that describes the behavior of the upstream internal link. This block is mapped into memory space, using the Root Complex Base Address (RCBA) register of the PCI-to-LPC bridge.
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Chipset Configuration Registers Table 5-1.
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Chipset Configuration Registers The existing root port Function Disable registers operate on physical ports (not functions). Port Configuration (1x4, 4x1, and so on) is not affected by the logical function number assignment and is associated with physical ports. Note: The difference between hiding vs disabling a port is that a hidden port is not able to claim downstream Config cycles only. Memory and I/O cycles are still claimed by that hidden port.
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Chipset Configuration Registers 5.1.3 FLRSTAT—Function Level Reset Pending Status Register Offset Address: Default Value: 0408–040Bh 00000000h Attribute: Size: Bit 31:24 23 22:16 15 14:0 5.1.4 Description Reserved FLR Pending Status for D29:F0, EHCI #1 — RO/V. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. Reserved FLR Pending Status for D26:F0, EHCI #2 — RO/V. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending.
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Chipset Configuration Registers 5.1.6 TWDR—Trapped Write Data Register Offset Address: Default Value: 1E18–1E1Fh 0000000000000000h Attribute: Size: RO 64-bit This register saves the data from I/O write cycles that are trapped for software to read. Bit 63:32 31:0 5.1.7 Description Reserved Trapped I/O Data (TIOD) — RO. DWord of I/O write data. This field is undefined after trapping a read cycle.
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Chipset Configuration Registers Bit 26:24 Virtual Channel Identifier (ID) — RO. Indicates the ID to use for this virtual channel. 23:16 Reserved 15:10 Extended TC/VC Map (ETVM)— R/WL. Defines the upper 8-bits of the VC0 16-bit TC/VC mapping registers. These registers use the PCI Express reserved TC[3] traffic class bit. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set. 9:7 Reserved 6:1 Transaction Class / Virtual Channel Map (TVM) — R/WL.
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Chipset Configuration Registers 5.1.12 REC—Root Error Command Register Offset Address: Default Value: 31 Drop Poisoned Downstream Packets (DPDP) — R/W. Determines how downstream packets for internal messaging are handled that are received with the EP field set, indicating poisoned data: 0 = Packets are forwarded downstream without forcing the UT field set.
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Chipset Configuration Registers 5.1.16 D31IP—Device 31 Interrupt Pin Register Offset Address: Default Value: 3100–3103h 03243200h Bit Description Reserved 27:24 Thermal Throttle Pin (TTIP) — R/W. Indicates which pin the Thermal Throttle controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# (Default) 4h = INTD# 5h–Fh = Reserved 23:20 SATA Pin 2 (SIP2) — R/W. Indicates which pin the SATA controller 2 drives as its interrupt.
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Chipset Configuration Registers 5.1.19 Bit Description 3:0 EHCI #1 Pin (E1P) — R/W. Indicates which pin the EHCI controller #1 drives as its interrupt, if controller exists. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved Note: EHCI Controller #1 is mapped to Device 29 Function 0. D28IP—Device 28 Interrupt Pin Register Offset Address: Default Value: 310C–310Fh 00214321h Attribute: Size: R/W 32-bit Bit Description 31:28 PCI Express* #8 Pin (P8IP) — R/W.
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Chipset Configuration Registers Bit 5.1.20 Description 7:4 PCI Express #2 Pin (P2IP) — R/W. Indicates which pin the PCI Express port #2 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 3:0 PCI Express #1 Pin (P1IP) — R/W. Indicates which pin the PCI Express port #1 drives as its interrupt.
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Chipset Configuration Registers 5.1.23 D22IP—Device 22 Interrupt Pin Register Offset Address: Default Value: 3124–3127h 00004321h Bit 5.1.24 R/W 32-bit Description 31:16 Reserved 15:12 KT Pin (KTIP) — R/W. Indicates which pin the Keyboard text PCI functionality drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# (Default) 5h–Fh = Reserved 11:8 IDE-R Pin (IDERIP) — R/W.
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Chipset Configuration Registers Bit 14:12 11 10:8 7 6:4 3 2:0 5.1.26 Description Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on Intel® Xeon® Processor D-1500 Product Family is connected to the INTD# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) — R/W.
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Chipset Configuration Registers Bit Description 14:12 Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on Intel® Xeon® Processor D1500 Product Family is connected to the INTD# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 11 10:8 7 6:4 3 2:0 5.1.28 Reserved Interrupt C Pin Route (ICR) — R/W.
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Chipset Configuration Registers Bit 10:8 7 6:4 3 2:0 5.1.29 Description Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on Intel® Xeon® Processor D-1500 Product Family is connected to the INTC# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt B Pin Route (IBR) — R/W.
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Chipset Configuration Registers Bit 6:4 3 2:0 5.1.30 Description Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on Intel® Xeon® Processor D-1500 Product Family is connected to the INTB# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt A Pin Route (IAR) — R/W.
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Chipset Configuration Registers Bit 2:0 5.1.31 Description Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on Intel® Xeon® Processor D-1500 Product Family is connected to the INTA# pin reported for device 26 functions.
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Chipset Configuration Registers 5.1.32 D22IR—Device 22 Interrupt Route Register Offset Address: Default Value: 315C–315Dh 3210h Bit 15 14:12 11 10:8 7 6:4 3 2:0 5.1.33 Attribute: Size: R/W 16-bit Description Reserved Interrupt D Pin Route (IDR): — R/W.
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Chipset Configuration Registers Bit 14:12 11 10:8 7 6:4 3 2:0 5.1.34 Description Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on Intel® Xeon® Processor D-1500 Product Family is connected to the INTD# pin reported for device 20 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Reserved Interrupt C Pin Route (ICR) — R/W.
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Chipset Configuration Registers Bit Description 7:0 APIC Range Select (ASEL) — R/W. These bits define address bits 19:12 for the IOxAPIC range. The default value of 00h enables compatibility with prior Intel® Xeon® Processor D-1500 Product Family products as an initial value. This value must not be changed unless the IOxAPIC Enable bit is cleared. Note: 5.1.35 FEC1_0000h–FEC3_FFFFh is allocated to PCIe when I/OxAPIC Enable (PAE) bit is set.
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Chipset Configuration Registers 5.1.37 WADT_EXP_AC—Wake Alarm Device Expired Timer – AC Register Offset Address: Default Value: Attribute: Size: R/W 32-bit Bit Description 31:0 Wake Alarm Device Expired Timer Value for AC Mode (WADT_EXP_AC_VAL): R/W. This field contains the 32-bit wake alarm device “Expired Timer” value (1 second granularity) for AC power.
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Chipset Configuration Registers 5.1.40 Bit Description 5 Wake On LAN Override Wake Status (WOL_OVR_WK_STS) — R/WC. This bit gets set when all of the following conditions are met: • Integrated LAN Signals a Power Management Event • The system is not in S0 • The “WoL Enable Override” bit is set in configuration space. BIOS can read this status bit to determine this wake source. Software clears this bit by writing a 1 to it. 4 PRSTS Field 1 — R/WC. BIOS may program this field.
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Chipset Configuration Registers Bit Description 17:16 SLP_A# Minimum Assertion Width (SLP_A_MIN_ASST_WDTH) — R/W. This field indicates the minimum assertion width of the SLP_A# signal to guarantee that the VCCIOIN supplies have been fully power cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power circuits, and so on.
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Chipset Configuration Registers 5.1.43 DCIR3340—Chipset Initialization Register 3340 Offset Address: Default Value: 3340–3343h 00000000h Bit 31:20 19:0 5.1.44 Reserved CIR3340 Field 1 — R/W. BIOS may program this register. CIR3344—Chipset Initialization Register 3344 3344–3347h 00000000h Bit 31:2 1:0 Attribute: Size: R/W 32-bit Description Reserved CIR3344 Field 1 — R/W. BIOS must program this field to 10b.
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Chipset Configuration Registers 5.1.47 CIR3360—Chipset Initialization Register 3360 Offset Address: Default Value: 3360–3363h 00000000h Bit 31:0 5.1.48 CIR3360 Field 1 — R/W. BIOS must program this field to 0001C000h. CIR3368—Chipset Initialization Register 3368 3368–336Bh 00000000h Bit 31:0 CIR3378—Chipset Initialization Register 3378 31:0 3378–337Bh 00000000h R/W 32-bit CIR3378 Field 1 — R/W. BIOS may program this register.
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Chipset Configuration Registers 5.1.53 CIR33A0—Chipset Initialization Register 33A0 Offset Address: Default Value: 33A0–33A3h 00000000h Bit CIR33A0 Field 1 — R/W. BIOS must program this field to 00000800h. CIR33B0—Chipset Initialization Register 33B0 Offset Address: Default Value: 33B0–33B3h 00000000h Bit 31:0 5.1.55 R/W 32-bit Description CIR33C0—Chipset Initialization Register 33C0 33C0–33C3h 00000000h Bit 31:0 Attribute: Size: R/W 32-bit Description CIR33C0 Field 1 — R/W.
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Chipset Configuration Registers 5.1.58 CIR33D4—Chipset Initialization Register 33D4 Offset Address: Default Value: 33D4–33D7h 00000000h Bit Description GPIO_D to PMSYNC Enable (GPIO_D_PMSYNC_EN) — R/W. 0 = GPIO_D (as selected in RCBA+33C8h) pin state not sent to processor over PMSYNC. 1 = GPIO_D state sent to processor over PMSYNC. 30 GPIO_C to PMSYNC Enable (GPIO_C_PMSYNC_EN) — R/W. 0 = GPIO_C (as selected in RCBA+33C8h) pin state not sent to processor over PMSYNC.
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Chipset Configuration Registers 5.1.61 GCS—General Control and Status Register Offset Address: Default Value: 3410–3413h 00000yy0h (yy = xx0000x0b) Attribute: Size: Bit R/W, R/WLO 32-bit Description 31:12 Reserved 11:10 Boot BIOS Straps (BBS) — R/W. This field determines the destination of accesses to the BIOS memory range. The default values for these bits represent the strap values of GPIO51 (bit 11) at the rising edge of PCH_PWROK and SATA1GP/GPIO19 (bit 10) at the rising edge of PCH_PWROK.
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Chipset Configuration Registers 5.1.62 Bit Description 2 Reserved Page Route (RPR) — R/W. Determines where to send the reserved page registers. These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh.
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Chipset Configuration Registers 5.1.63 FD—Function Disable Register Offset Address: Default Value: 3418–341Bh See bit description Attribute: Size: R/W 32-bit When disabling a function, only the configuration space is disabled. Software must ensure that all functionality within a controller that is not desired (such as memory spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function. When a function is disabled, software must not attempt to re-enable it.
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Chipset Configuration Registers Bit Description 14 LPC Bridge Disable (LBD) — R/W. Default is 0. 0 = The LPC bridge is enabled. 1 = The LPC bridge is disabled.
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Chipset Configuration Registers 5.1.65 DISPBDF—Display Bus, Device and Function Initialization Register Offset Address: Default Value: 3424–3427h 00040010h Bit 5.1.66 Description Reserved. 18:16 Display Target Block (DTB) — R/W. The Target BLK field that Intel® Xeon® Processor D-1500 Product Family South Display controller should use when sending RAVDM messages to the processor. BIOS must program this field to 110h. 15:8 Display Bus Number (DBN) — R/W.
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Chipset Configuration Registers 5.1.69 CIR3A6C—Chipset Initialization Register 3A6C Offset Address: Default Value: 3A6C–3A6Fh 00000000h Attribute: Size: Bit Description 31:0 5.1.70 CIR3A6C Field 1 — R/W. BIOS must program this field to 00000001h. CIR3A80—Chipset Initialization Register 3A80 Offset Address: Default Value: 3A80–3A83h 00000000h Attribute: Size: Bit CIR3A80 Field 1 — R/W. BIOS may program this register.
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Chipset Configuration Registers 5.2.1 TIRC0—Thermal Initialization Register C0 Offset Address: Default Value: C0–C3h 00000000h Bit R/W. BIOS must program this field to 8000390Bh. No other values are supported. TIRC4—Thermal Initialization Register C4 Offset Address: Default Value: C4–C7h 00000000h Bit 31:0 5.2.3 TIRC8—Thermal Initialization Register C8 31:0 C8–CBh 00000000h Attribute: Size: R/W 32-bit Description R/W. BIOS must program this field to 05800000h. No other values are supported.
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Chipset Configuration Registers 5.2.7 TIRF0—Thermal Initialization Register F0 Offset Address: Default Value: Bit 31:0 F0–F3h 00000000h Attribute: Size: R/W 32-bit Description R/W. BIOS must program this field to 00000003h. No other values are supported.
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Gigabit LAN Configuration Registers 6 Gigabit LAN Configuration Registers 6.1 Gigabit LAN Configuration Registers (Gigabit LAN—D25:F0) Note: Register address locations that are not shown in Table 6-1 should be treated as Reserved. All GbE registers are located in the VccIOIN power well. / Table 6-1.
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Gigabit LAN Configuration Registers Table 6-1. Gigabit LAN Configuration Registers Address Map (Gigabit LAN—D25:F0) (Sheet 2 of 2) Offset 6.1.
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Gigabit LAN Configuration Registers Bit 6.1.4 Description 7 Wait Cycle Control (WCC) — RO. Hardwired to 0. 6 Parity Error Response (PER) — R/W. 0 = Disable. 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone. 5 Palette Snoop Enable (PSE) — RO. Hardwired to 0. 4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0. 3 Special Cycle Enable (SCE) — RO. Hardwired to 0. 2 Bus Master Enable (BME) — R/W. 0 = Disable.
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Gigabit LAN Configuration Registers Bit 3 2:0 6.1.5 Description Interrupt Status — RO. Indicates status of Hot-Plug and power management interrupts on the root port that result in INTx# message generation. 0 = Interrupt is de-asserted. 1 = Interrupt is asserted. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10).
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Gigabit LAN Configuration Registers 6.1.10 MBARA—Memory Base Address Register A (Gigabit LAN— D25:F0) Address Offset: Default Value: 10h–13h 00000000h Attribute: Size: R/W, RO 32 bits The internal CSR registers and memories are accessed as direct memory mapped offsets from the base address register. SW may only access whole DWord at a time. Bit 31:17 16:4 3 2:1 0 6.1.11 Description Base Address (BA) — R/W. Software programs this field with the base address of this region. Memory Size (MSIZE) — RO.
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Gigabit LAN Configuration Registers 6.1.13 SVID—Subsystem Vendor ID Register (Gigabit LAN— D25:F0) Address Offset: Default Value: 6.1.14 Description Subsystem Vendor ID (SVID) — RO. This value may be loaded automatically from the NVM Word 0Ch upon power up or reset depending on the "Load Subsystem ID" bit field in NVM word 0Ah. A value of 8086h is default for this field upon power up if the NVM does not respond or is not programmed. All functions are initialized to the same value.
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Gigabit LAN Configuration Registers 6.1.18 MLMG—Maximum Latency / Minimum Grant Register (Gigabit LAN—D25:F0) Address Offset: Default Value: 3Eh–3Fh 0000h Bit 7:0 6.1.19 Description STCL—System Time Control Low Register (Gigabit LAN— D25:F0) A0h–A3h 00000000h Attribute: Size: RO 32 bits Bit Description 31:0 System Time Control Low (STCL) — RO. Lower 32 bits of the system time capture used for audio stream synchronization.
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Gigabit LAN Configuration Registers Bit 12:10 9:0 6.1.22 Description Maximum Snoop Latency Scale (MSLS) — R/W. Provides a scale for the value contained within the Maximum Snoop Latency Value field. 000b = Value times 1 ns 001b = Value times 32 ns 010b = Value times 1,024 ns 011b = Value times 32,768 ns 100b = Value times 1,048,576 ns 101b = Value times 33,554,432 ns 110b-111b – Reserved Maximum Snoop Latency (MSL) — R/W. Specifies the maximum snoop latency that a device is permitted to request.
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Gigabit LAN Configuration Registers 6.1.24 PMCS—PCI Power Management Control and Status Register (Gigabit LAN—D25:F0) Address Offset: CCh–CDh Default Value: See bit description Function Level Reset:No (Bit 8 only) Bit 15 R/WC, R/W, RO 16 bits Description PME Status (PMES) — R/WC. This bit is set to 1 when the function detects a wake-up event independent of the state of the PMEE bit. Writing a 1 will clear this bit. 14:13 Data Scale (DSC) — RO.
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Gigabit LAN Configuration Registers 6.1.26 CLIST2—Capabilities List Register 2 (Gigabit LAN— D25:F0) Address Offset: D0h–D1h Default Value: E005h Function Level Reset: No (Bits 15:8 only) Bit 15:8 7:0 6.1.27 Next Capability (NEXT) — R/WO. Value of E0h points to the Function Level Reset capability structure. These bits are not reset by Function Level Reset. Capability ID (CID) — RO. Indicates the linked list item is a Message Signaled Interrupt Register.
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Gigabit LAN Configuration Registers 6.1.30 MDAT—Message Data Register (Gigabit LAN—D25:F0) Address Offset: Default Value: 6.1.31 Attribute: Size: R/W 16 bits Bit Description 31:0 Message Data (MDAT) — R/W. Written by the system to indicate the lower 16 bits of the data written in the MSI memory write DWord transaction. The upper 16 bits of the transaction are written as 0000h.
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Gigabit LAN Configuration Registers 6.1.33 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0) Address Offset: Default Value: E4–E5h 0000h Bit 15:9 8 7:1 0 6.2 Attribute: Size: R/W 16 bits Description Reserved Transactions Pending (TXP) — R/W. 1 = Indicates the controller has issued Non-Posted requests which have not been completed. 0 = Indicates that completions for all Non-Posted requests have been received. Reserved Initiate Function Level Reset — R/W.
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Gigabit LAN Configuration Registers 6.2.1 GBECSR_00—Gigabit Ethernet Capabilities and Status Register 00 Address Offset: Default Value: MBARA + 00h 00100241h Bit 31:25 24 23:0 6.2.2 R/W 32 bit Description Reserved PHY Power Down (PHYPDN) — R/W. When cleared (0b), the PHY power down setting is controlled by the internal logic of Intel® Xeon® Processor D-1500 Product Family.
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Gigabit LAN Configuration Registers 6.2.4 GBECSR_2C—Gigabit Ethernet Capabilities and Status Register 2C Address Offset: Default Value: MBARA + 2Ch 00000000h Bit Description WOL Indication Valid (WIV) — R/W. Set to 1 by BIOS to indicate that the WOL indication setting in bit 30 of this register is valid. 30 WOL Enable Setting by BIOS (WESB) — R/W. 1 = WOL Enabled in BIOS. 0 = WOL Disabled in BIOS.
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Gigabit LAN Configuration Registers 6.2.7 GBECSR_5400—Gigabit Ethernet Capabilities and Status Register 5400 Address Offset: Default Value: MBARA + 5400h XXXXXXXXh Bit 31:0 6.2.8 Description GBECSR_5404—Gigabit Ethernet Capabilities and Status Register 5404 MBARA + 5404h XXXXXXXXh Bit 31 30:16 15:0 Attribute: Size: R/W 32 bits Description Address Valid— R/W. Reserved Receive Address High (RAH)— R/W. The lower 16 bits of the 48 bit Ethernet Address.
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LPC Interface Bridge Registers (D31:F0) 7 LPC Interface Bridge Registers (D31:F0) The LPC bridge function of Intel® Xeon® Processor D-1500 Product Family resides in PCI D31:F0. This function contains many other functional units, such as DMA and Interrupt controllers, Timers, Power Management, System Management, GPIO, RTC, and LPC Configuration Registers. Registers and functions associated with other functional units are described in their respective sections. 7.
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LPC Interface Bridge Registers (D31:F0) Table 7-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2) Offset Mnemonic Register Name Default Attribute 94h–97h ULKMC USB Legacy Keyboard / Mouse Control 00002000h RO, R/WC, R/ W 98h–9Bh LGMR LPC I/F Generic Memory Range 00000000h R/W A0h–CFh 7.1.1 Power Management (See Section 7.8.
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LPC Interface Bridge Registers (D31:F0) 7.1.4 Bit Description 6 Parity Error Response Enable (PERE) — R/W. 0 = No action is taken when detecting a parity error. 1 = Enables Intel® Xeon® Processor D-1500 Product Family LPC bridge to respond to parity errors detected on backbone interface. 5 VGA Palette Snoop (VPS) — RO. Hardwired to 0. 4 Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0. 3 Special Cycle Enable (SCE) — RO. Hardwired to 0. 2 Bus Master Enable (BME) — RO.
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LPC Interface Bridge Registers (D31:F0) 7.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) Offset Address: Default Value: 08h See bit description Bit 7:0 7.1.6 Revision ID (RID) — R/WO. This field indicates the device specific revision identifier. PI—Programming Interface Register (LPC I/F—D31:F0) 09h 00h Bit 7:0 SCC—Sub Class Code Register (LPC I/F—D31:F0) 7:0 0Ah 01h Attribute: Size: RO 8-bit Description Sub Class Code — RO.
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LPC Interface Bridge Registers (D31:F0) 7.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) Offset Address: Default Value: 2Ch–2Fh 00000000h Attribute: Size: R/WO 32 bits This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only once after PLTRST# de-assertion. Bit 7.1.12 Description 31:16 Subsystem ID (SSID) — R/WO. This is written by BIOS. No hardware action taken on this value. 15:0 Subsystem Vendor ID (SSVID) — R/WO.
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LPC Interface Bridge Registers (D31:F0) Bit Description 2:0 SCI IRQ Select (SCI_IRQ_SEL) — R/W. Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20–23, and can be shared with other interrupts.
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LPC Interface Bridge Registers (D31:F0) 7.1.17 Bit Description 0 GPIO Lockdown Enable (GLE) — R/W. This bit enables lockdown of the following GPIO registers: • Offset 00h: GPIO_USE_SEL • Offset 04h: GP_IO_SEL • Offset 0Ch: GP_LVL • Offset 30h: GPIO_USE_SEL2 • Offset 34h: GP_IO_SEL2 • Offset 38h: GP_LVL2 • Offset 40h: GPIO_USE_SEL3 • Offset 44h: GP_IO_SEL3 • Offset 48h: GP_LVL3 • Offset 60h: GP_RST_SEL 0 = Disable. 1 = Enable. When this bit is written from 1-to-0, an SMI# is generated, if enabled.
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LPC Interface Bridge Registers (D31:F0) 7.1.18 SIRQ_CNTL—Serial IRQ Control Register (LPC I/F— D31:F0) Offset Address: Default Value: Lockable: 64h 10h No Attribute: Size: Power Well: Bit Description 7 Serial IRQ Enable (SIRQEN) — R/W. 0 = The buffer is input only and internally SERIRQ will be a 1. 1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ. 6 Serial IRQ Mode Select (SIRQMD) — R/W. 0 = The serial IRQ machine will be in quiet mode.
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LPC Interface Bridge Registers (D31:F0) 7.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function (LPC I/F— D31:F0) Offset Address: Default Value: 6Ch–6Dh 00F8h Attribute: Size: R/W 16 bits Bit Description 15:0 IOxAPIC Bus:Device:Function (IBDF)— R/W. this field specifies the bus:device:function that Intel® Xeon® Processor D-1500 Product Family’s IOxAPIC will be using for the following: • As the Requester ID when initiating Interrupt Messages to the processor.
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LPC Interface Bridge Registers (D31:F0) 7.1.22 LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F— D31:F0) Offset Address: Default Value: 80h 0000h Bit 15:13 12 11:10 9:8 7 6:4 3 2:0 7.1.23 Attribute: Size: R/W 16 bits Description Reserved FDD Decode Range — R/W. Determines which range to decode for the FDD Port 0 = 3F0h–3F5h, 3F7h (Primary) 1 = 370h–375h, 377h (Secondary) Reserved LPT Decode Range — R/W. This field determines which range to decode for the LPT Port.
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LPC Interface Bridge Registers (D31:F0) Bit Description 10 KBC_LPC_EN — R/W. Keyboard Enable. 0 = Disable. 1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used for a microcontroller. 9 GAMEH_LPC_EN — R/W. High Gameport Enable 0 = Disable. 1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is used for a gameport. 8 GAMEL_LPC_EN — R/W. Low Gameport Enable 0 = Disable.
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LPC Interface Bridge Registers (D31:F0) 7.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register (LPC I/F—D31:F0) Offset Address: Default Value: 88h–8Bh 00000000h Bit Description Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored.
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LPC Interface Bridge Registers (D31:F0) 7.1.28 Bit Description 15:2 Generic I/O Decode Range 4 Base Address (GEN4_BASE) — R/W. Note: Intel® Xeon® Processor D-1500 Product Family Does not provide decode down to the word or byte level 1 Reserved 0 Generic Decode Range 4 Enable (GEN4_EN) — R/W. 0 = Disable.
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LPC Interface Bridge Registers (D31:F0) Bit 7.1.29 Description 4 SMI on USB IRQ Enable (USBSMIEN) — R/W. 0 = Disable 1 = Enable. USB interrupt will cause an SMI event. 3 SMI on Port 64 Writes Enable (64WEN) — R/W. 0 = Disable 1 = Enable. A 1 in bit 11 will cause an SMI event. 2 SMI on Port 64 Reads Enable (64REN) — R/W. 0 = Disable 1 = Enable. A 1 in bit 10 will cause an SMI event. 1 SMI on Port 60 Writes Enable (60WEN) — R/W. 0 = Disable 1 = Enable. A 1 in bit 9 will cause an SMI event.
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LPC Interface Bridge Registers (D31:F0) 7.1.31 Bit Description 15:12 BIOS_D8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD8 0000h–FFDF FFFFh FF98 0000h–FF9F FFFFh 11:8 BIOS_D0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD0 0000h–FFD7 FFFFh FF90 0000h–FF97 FFFFh 7:4 BIOS_C8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges.
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LPC Interface Bridge Registers (D31:F0) Bit Description 13 BIOS_E8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS: FFE80000h–FFEFFFFh FFA80000h–FFAFFFFFh 12 BIOS_E0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS: FFE00000h–FFE7FFFFh FFA00000h–FFA7FFFFh 11 BIOS_D8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges. 0 = Disable.
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LPC Interface Bridge Registers (D31:F0) Bit 0 Note: 7.1.33 Description BIOS_40_EN — R/W. Enables decoding two 1-M BIOS memory ranges. 0 = Disable. 1 = Enable the following ranges for the BIOS FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh This register effects the BIOS decode regardless of whether the BIOS is resident on LPC or SPI. The concept of Feature Space does not apply to SPI-based flash.
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LPC Interface Bridge Registers (D31:F0) 7.1.34 FDCAP—Feature Detection Capability ID Register (LPC I/ F—D31:F0) Offset Address: Default Value: E0h–E1h 0009h Bit 15:8 7:0 7.1.35 Next Item Pointer (NEXT) — RO. Configuration offset of the next Capability Item. 00h indicates the last item in the Capability List. Capability ID — RO.
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LPC Interface Bridge Registers (D31:F0) 7.1.38 FVECD—Feature Vector Data Register (LPC I/F—D31:F0) Offset Address: Default Value: E8h–EBh See Description Attribute: Size: Power Well: Bit 31:0 Description Data (DATA) — RO. 32-bit data value that is read from the Feature Vector offset pointed to by FVECIDX. 7.1.39 Feature Vector Space 7.1.39.1 FVEC0—Feature Vector Register 0 FVECIDX.
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LPC Interface Bridge Registers (D31:F0) 7.1.39.3 FVEC2—Feature Vector Register 2 FVECIDX.IDX: Default Value: 0010b See Description Attribute: Size: Power Well: Bit 31:22 21 20:18 17 16:0 7.1.39.4 Description Reserved PCI Express* Ports 7 and 8— RO 0 = Capable 1 = Disabled Reserved Intel® Xeon® Processor D-1500 Product Family Integrated Graphics Support Capability — RO 0 = Capable 1 = Disabled Reserved FVEC3—Feature Vector Register 3 FVECIDX.
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LPC Interface Bridge Registers (D31:F0) Table 7-2.
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LPC Interface Bridge Registers (D31:F0) 7.2.1 DMABASE_CA—DMA Base and Current Address Registers I/O Address: Default Value: Lockable: 7.2.2 Ch. #0 = 00h; Ch. #1 = 02h Ch. #2 = 04h; Ch. #3 = 06h Ch. #5 = C4h Ch. #6 = C8h Ch. #7 = CCh; Undefined No Attribute: Size: R/W 16 bits (per channel), but accessed in two 8 bits quantities Power Well: Core Bit Description 15:0 Base and Current Address — R/W. This register determines the address for the transfers to be performed.
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LPC Interface Bridge Registers (D31:F0) 7.2.3 DMAMEM_LP—DMA Memory Low Page Registers I/O Address: Default Value: Lockable: 7.2.4 Ch. #0 = 87h; Ch. #1 = 83h Ch. #2 = 81h; Ch. #3 = 82h Ch. #5 = 8Bh; Ch. #6 = 89h Ch. #7 = 8Ah; Undefined No Description 7:0 DMA Low Page (ISA Address bits [23:16]) — R/W. This register works in conjunction with the DMA controller's Current Address Register to define the complete 24-bit address for the DMA channel. This register remains static throughout the DMA transfer.
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LPC Interface Bridge Registers (D31:F0) 7.2.6 DMA_WRSMSK—DMA Write Single Mask Register I/O Address: Default Value: Lockable: Ch. #0–3 = 0Ah; Ch. #4–7 = D4h 0000 01xx No Bit 7:3 2 1:0 7.2.7 Attribute: Size: Power Well: WO 8 bits Core Description Reserved. Must be 0. Channel Mask Select — WO. 0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore, only one channel can be masked / unmasked at a time. 1 = Disable DREQ for the selected channel.
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LPC Interface Bridge Registers (D31:F0) 7.2.8 DMA Clear Byte Pointer Register I/O Address: Default Value: Lockable: 7.2.9 7:0 Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the I/O port address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is also cleared by part reset and by the Master Clear command.
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LPC Interface Bridge Registers (D31:F0) Bit Description 3:0 Channel Mask Bits — R/W. This register permits all four channels to be simultaneously enabled/ disabled instead of enabling/disabling each channel individually, as is the case with the Mask Register – Write Single Mask Bit. In addition, this register has a read path to allow the status of the channel mask bits to be read.
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LPC Interface Bridge Registers (D31:F0) Bit 3:1 Description Counter Mode Selection — WO. These bits select one of six possible modes of operation for the selected counter. Bit Value 0 Mode 000b Mode 0 Out signal on end of count (=0) 001b Mode 1 Hardware retriggerable one-shot x10b Mode 2 Rate generator (divide by n counter) x11b Mode 3 Square wave output 100b Mode 4 Software triggered strobe 101b Mode 5 Hardware triggered strobe Binary/BCD Countdown Select — WO.
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LPC Interface Bridge Registers (D31:F0) LTCH_CMD—Counter Latch Command The Counter Latch Command latches the current count value. This command is used to insure that the count read from the counter is accurate. The count value is then read from each counter's count register through the Counter Ports Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2).
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LPC Interface Bridge Registers (D31:F0) Bit Description 3:1 Mode Selection Status — RO. These bits return the counter mode programming. The binary code returned matches the code used to program the counter mode, as listed under the bit function above.
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LPC Interface Bridge Registers (D31:F0) Table 7-3. PIC Registers Port Aliases A1h A5h, A9h, ADh, B1h, B5h, B9h, BDh Default Value Type Slave PIC ICW2 Init. Cmd Word 2 Register Name Undefined WO Slave PIC ICW3 Init. Cmd Word 3 Undefined WO Slave PIC ICW4 Init.
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LPC Interface Bridge Registers (D31:F0) 7.4.3 ICW2—Initialization Command Word 2 Register Offset Address: Default Value: Master Controller – 21h Slave Controller – A1h All bits undefined Attribute: Size: WO 8 bits /controller ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address.
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LPC Interface Bridge Registers (D31:F0) 7.4.5 ICW3—Slave Controller Initialization Command Word 3 Register Offset Address: Default Value: A1h All bits undefined Bit 7.4.6 WO 8 bits Description 7:3 0 = These bits must be programmed to 0. 2:0 Slave Identification Code — WO. These bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing edge of the second internal INTA# pulse.
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LPC Interface Bridge Registers (D31:F0) 7.4.8 OCW2—Operational Control Word 2 Register Offset Address: Default Value: Master Controller – 020h Attribute: Slave Controller – 0A0h Size: Bit[4:0]=undefined, Bit[7:5]=001 WO 8 bits Following a part reset or ICW initialization, the controller enters the fully nested mode of operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI mode are disabled following initialization. 7.4.
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LPC Interface Bridge Registers (D31:F0) 7.4.10 Bit Description 1:0 Register Read Command — WO. These bits provide control for reading the In-Service Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port address read will be “read IRR”.
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LPC Interface Bridge Registers (D31:F0) Bit Description 6 IRQ14 ECL — R/W. 0 = Edge 1 = Level 5 Reserved. Must be 0. 4 IRQ12 ECL — R/W. 0 = Edge 1 = Level 3 IRQ11 ECL — R/W. 0 = Edge 1 = Level 2 IRQ10 ECL — R/W. 0 = Edge 1 = Level 1 IRQ9 ECL — R/W. 0 = Edge 1 = Level 0 Reserved. Must be 0. 7.5 Advanced Programmable Interrupt Controller (APIC) 7.5.1 APIC Register Map The APIC is accessed using an indirect addressing scheme.
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LPC Interface Bridge Registers (D31:F0) Table 7-5. 7.5.2 APIC Indirect Registers Index Mnemonic ... ... 3E–3F REDIR_TBL23 40–FF — Register Name Size Type ... ... 64 bits R/W, RO — RO ... Redirection Table 23 Reserved IND—Index Register Memory Address Default Value: FEC_ _0000h 00h Attribute: Size: R/W 8 bits The Index Register will select which APIC indirect register to be manipulated by software. The selector values for the indirect registers are listed in Table 7-5.
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LPC Interface Bridge Registers (D31:F0) Bit 31:8 7:0 7.5.5 Description Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC will check this field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
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LPC Interface Bridge Registers (D31:F0) 32 bit quantities) The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message. The APIC will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the I/O APIC is set.
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LPC Interface Bridge Registers (D31:F0) 001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode can be edge or level. 010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge triggered. The vector information is ignored but must be programmed to all 0s for future compatibility: not supported 011 = Reserved 100 = NMI.
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LPC Interface Bridge Registers (D31:F0) 73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not needed, it may be disabled. 2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. Port 70h is not directly readable. The only way to read this register is through Alt Access mode.
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LPC Interface Bridge Registers (D31:F0) Bit 7.6.2.2 Description 6:4 Division Chain Select (DV[2:0]) — R/W. These three bits control the divider chain for the oscillator, and are not affected by RSMRST# or any other reset signal. 010 = Normal Operation 11X = Divider Reset 101 = Bypass 15 stages (test mode only) 100 = Bypass 10 stages (test mode only) 011 = Bypass 5 stages (test mode only) 001 = Invalid 000 = Invalid 3:0 Rate Select (RS[3:0]) — R/W. Selects one of 13 taps of the 15 stage divider chain.
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LPC Interface Bridge Registers (D31:F0) 7.6.2.3 Bit Description 2 Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation. This bit is not affected by RSMRST# nor any other reset signal. 0 = BCD 1 = Binary 1 Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is not affected by RSMRST# nor any other reset signal. 0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and PM as one. 1 = Twenty-four hour mode.
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LPC Interface Bridge Registers (D31:F0) Table 7-8. Processor Interface PCI Register Address Map Offset 7.7.
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LPC Interface Bridge Registers (D31:F0) 7.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) Register I/O Address: Default Value: Lockable: Note: 70h 80h No 7 6:0 Description NMI Enable (NMI_EN) — R/W (special). 0 = Enable NMI sources. 1 = Disable All NMI sources. Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to the RTC to select which register or CMOS RAM address is being accessed. PORT92—Init Register I/O Address: Default Value: Lockable: 92h 00h No Bit 7:2 7.7.
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LPC Interface Bridge Registers (D31:F0) Bit Description 3 Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PCH_PWROK going low (with RSMRST# high), or after two TCO timeouts. 0 = Intel® Xeon® Processor D-1500 Product Family will keep SLP_S3#, SLP_S4# and SLP_S5# high. 1 = Intel® Xeon® Processor D-1500 Product Family will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3–5 seconds.
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LPC Interface Bridge Registers (D31:F0) Table 7-9. 7.8.1.
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LPC Interface Bridge Registers (D31:F0) 7.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0) Offset Address: Default Value: Lockable: Bit 15:13 A2–A3h 2000h No Attribute: Size: Usage: Power Well: R/W, RO, R/WC 16 bits ACPI, Legacy RTC, SUS Description Reserved 12 AG3_PP_EN - R/W. After G3 PHY Power Enable. • When this bit is cleared (default), SLP_LAN# will be driven low upon exiting G3. • When this bit is set, SLP_LAN# value is dependant on DSX_PP_DIS and Sx_PP_EN setting.
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LPC Interface Bridge Registers (D31:F0) Bit Description 2 Minimum SLP_S4# Assertion Width Violation Status — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset A4h:bits 5:4). Intel® Xeon® Processor D-1500 Product Family begins the timer when SLP_S4# is asserted during S4/S5 entry or when the RSMRST# input is de-asserted during SUS well power-up.
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LPC Interface Bridge Registers (D31:F0) Bit 12 Description Disable SLP Stretching After SUS Well Power Up (DIS_SLP_STRCH_SUS_UP): R/WL 0 = Enables stretching on SLP signals after SUS power failure as enabled and configured in other fields. 1 = Disables stretching on SLP signals when powering up after a SUS well power loss. regardless of the state of the SLP_S4# Assertion Stretch Enable (bit 3). This bit is cleared by the RTCRST# pin. Notes: 1.
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LPC Interface Bridge Registers (D31:F0) Bit Description 5:4 SLP_S4# Minimum Assertion Width(SLP_S4_MIN_ASST_WDTH)— R/WL. This field indicates the minimum assertion width of the SLP_S4# signal to ensure that the DRAM modules have been safely power-cycled. Valid values are: 11 = 1 second 10 = 2 seconds 01 = 3 seconds 00 = 4 seconds This value is used in two ways: 1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to read when S0 is entered. 2.
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LPC Interface Bridge Registers (D31:F0) 7.8.1.5 Bit Description 2 SLP Stretching Policy Lock-Down (SLP_STR_POL_LOCK) — R/WLO. When set to 1, this bit locks down the Disable SLP Stretching After SUS Well Power Up, SLP_S3# Minimum Assertion Width, SLP_S4# Minimum Assertion Width, SLP_S4# Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored.
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LPC Interface Bridge Registers (D31:F0) Bit 1:0 7.8.1.8 Description Reserved GPI_ROUT—GPI Routing Control Register (PM—D31:F0) Offset Address: Default Value: Lockable: B8h–BBh 00000000h No Bit Attribute: Size: Power Well: R/W 32 bits Suspend Description 31:30 GPI 15 Route — R/W. See bits 1:0 for description. 29:28 GPI 14 Route — R/W. See bits 1:0 for description. 27:26 Reserved 25:24 GPI 12 Route — R/W. See bits 1:0 for description. 23:22 GPI 11 Route — R/W. See bits 1:0 for description.
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LPC Interface Bridge Registers (D31:F0) Bit Description 7:6 GPI22 Route — R/W. See bits 1:0 for description. 5:4 GPI21 Route — R/W. See bits 1:0 for description. 3:2 GPI19 Route — R/W. See bits 1:0 for description. 1:0 GPI17 Route — R/W. If the corresponding GPIO is implemented and is configured as an Input, then a ‘1’ in the corresponding GP_LVL bit can be routed to cause an interrupt.
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LPC Interface Bridge Registers (D31:F0) 7.8.3 Power Management I/O Registers Table 7-11 shows the registers associated with ACPI and Legacy power management support. These registers locations are all offsets from the ACPI base address defined in the PCI Device 31: Function 0 space (PMBASE), and can be moved to any 128-byte aligned I/O location. In order to access these registers, the ACPI Enable bit (ACPI_EN) must be set. The registers are defined to support the ACPI 4.
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LPC Interface Bridge Registers (D31:F0) Bit Description 15 Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the system is in one of the sleep states (using the SLP_EN bit) and an enabled wake event occurs. Upon setting this bit, Intel® Xeon® Processor D-1500 Product Family will transition the system to the ON state.
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LPC Interface Bridge Registers (D31:F0) Bit Description 4 Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI or SMI#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by Intel® Xeon® Processor D-1500 Product Family when a Intel® Xeon® Processor D-1500 Product Family-visible bus master requests access to memory or the BMBUSY# signal is active. 3:1 0 7.8.3.2 Reserved Timer Overflow Status (TMROF_STS) — R/WC.
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LPC Interface Bridge Registers (D31:F0) 7.8.3.3 PM1_CNT—Power Management 1 Control Register I/O Address: PMBASE + 04h Default Value: Lockable: Power Well: 00000000h No Bits 0–9, 13-31: Core, Bits 10–12: RTC Bit 31:14 13 12:10 7.8.3.4 Reserved Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system should enter when the SLP_EN bit is set to 1.
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LPC Interface Bridge Registers (D31:F0) 7.8.3.5 Bit Description 23:0 Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then continues counting as long as the system is in the S0 state. After an S1 state, the counter will not be reset (it will continue counting from the last value in S0 state.
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LPC Interface Bridge Registers (D31:F0) Bit Description 31:16 GPIn_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = These bits are set any time the corresponding GPIO is set up as an input and the corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the corresponding enable bit is set in the GPE0_EN register, then when the GPI[n]_STS bit is set: • If the system is in an S1–S5 state, the event will also wake the system.
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LPC Interface Bridge Registers (D31:F0) Bit Description 7 SMBus Wake Status (SMB_WAK_STS) — R/WC. Software clears this bit by writing a 1 to it. 0 = Wake event not caused by Intel® Xeon® Processor D-1500 Product Family’s SMBus logic. 1 = Set by hardware to indicate that the wake event was caused by Intel® Xeon® Processor D1500 Product Family’s SMBus logic. The SMI handler should then clear this bit. NOTES: 6 5:3 7.8.3.6 1.
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LPC Interface Bridge Registers (D31:F0) Bit Description 31:16 GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to cause a SCI, and/or wake event. These bits are cleared by RSMRST#. Note: Mapping is as follows: bit 31 corresponds to GPI15... and bit 16 corresponds to GPI0. 15:14 Reserved 13 PME_B0_EN — R/W. 0 = Disable Note: 12 Reserved 11 PME_EN — R/W. 0 = Disable. 1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
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LPC Interface Bridge Registers (D31:F0) Bit 29:28 27 26:19 Description Reserved GPIO_UNLOCK_SMI_EN— R/WO. Setting this bit will cause Intel® Xeon® Processor D-1500 Product Family to generate an SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS register. Once written to 1, this bit can only be cleared by PLTRST#. Reserved 18 INTEL_USB2_EN — R/W. 0 = Disable 1 = Enables Intel-Specific EHCI SMI logic to cause SMI#. 17 LEGACY_USB2_EN — R/W.
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LPC Interface Bridge Registers (D31:F0) Bit 1 Description End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI signal to the processor. This bit must be set for Intel® Xeon® Processor D-1500 Product Family to assert SMI# low to the processor after SMI# has been asserted previously. 0 = Once Intel® Xeon® Processor D-1500 Product Family asserts SMI# low, the EOS bit is automatically cleared.
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LPC Interface Bridge Registers (D31:F0) Bit Description 16 SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by writing a 1 to it. 0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must wait at least 15.63 μs after the initial assertion of this bit before clearing it. 1 = Indicates that the SMI# was caused by: 1. The SMBus Slave receiving a message that an SMI# should be caused, or 2.
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LPC Interface Bridge Registers (D31:F0) Bit 3 LEGACY_USB_STS — RO. This bit is a logical OR of each of the SMI status bits in the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. 0 = SMI# was not generated by USB Legacy event. 1 = SMI# was generated by USB Legacy event. 2 BIOS_STS — R/WC. 0 = No SMI# generated due to ACPI software requesting attention.
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LPC Interface Bridge Registers (D31:F0) 7.8.3.12 Bit Description 1 SWGPE_CTRL— R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set back to 1 by hardware.
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LPC Interface Bridge Registers (D31:F0) Bit 0 7.8.3.14 Description Arbiter Disable (ARB_DIS) — R/W This bit is a scratchpad bit for legacy software compatibility. ALT_GPI_SMI_EN2 - Alternate GPI SMI Enable 2 Register I/O Address: Default Value: Lockable: Power Well: PMBASE + 5Ch 0000h No Suspend Bit 15:8 7 7.8.3.15 R/W, RO 16 bits ACPI Description Reserved Alternate GPI[60] SMI Enable (ALT_GPI60_SMI_EN) — R/W. Refer to bit [0] in this register for description.
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LPC Interface Bridge Registers (D31:F0) Bit Alternate GPI[17] SMI Status (ALT_GPI17_SMI_STS) - R/W. These bits report the status of the corresponding GPIOs. 0 = Inactive. Software clears this bit by writing a 1 to it. 1 = Active These bits are sticky. If the following conditions are true, then an SMI# will be generated and the GPE0_STS bit set: • The corresponding bit in the ALT_GPI_SMI_EN2 register (PMBASE + 5Ch) is set • The corresponding GPIO must be routed in the GPI_ROUT2 register to cause an SMI.
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LPC Interface Bridge Registers (D31:F0) Bit 9:0 7.9.2 Description TCO Timer Value — R/W. Reading this register will return the current count of the TCO timer. Writing any value to this register will reload the timer to prevent the timeout. TCO_DAT_IN—TCO Data In Register I/O Address: Default Value: Lockable: TCOBASE +02h 00h No Bit 7:0 7.9.
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LPC Interface Bridge Registers (D31:F0) Bit Description 8 BIOSWR_STS — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Intel® Xeon® Processor D-1500 Product Family sets this bit and generates and SMI# to indicate an invalid attempt to write to the BIOS. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or b) any write is attempted to the BIOS and the BIOSWP bit is also set.
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LPC Interface Bridge Registers (D31:F0) Bit Description 2 BOOT_STS — R/WC. 0 = Cleared by Intel® Xeon® Processor D-1500 Product Family based on RSMRST# or by software writing a 1 to this bit. Software should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit. 1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the first instruction.
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LPC Interface Bridge Registers (D31:F0) Bit 9 8 7:0 7.9.7 Description NMI2SMI_EN — R/W. 0 = Normal NMI functionality. 1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table: NMI_EN GBL_SMI_EN 0b 0b 0b 1b SMI# will be caused due to NMI events 1b 0b No SMI# at all because GBL_SMI_EN = 0 1b 1b No SMI# due to NMI because NMI_EN = 1 NMI_NOW — R/WC.
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LPC Interface Bridge Registers (D31:F0) 7.9.9 TCO_WDCNT—TCO Watchdog Control Register Offset Address: Default Value: Power Well: TCOBASE + 0Eh 00h Resume Attribute: Size: Bit 7:0 7.9.10 Description The BIOS or system management software can write into this register to indicate more details on the boot progress. The register will reset to 00h based on a RSMRST# (but not PLTRST#). The external microcontroller can read this register to monitor boot progress.
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LPC Interface Bridge Registers (D31:F0) Table 7-13. Registers to Control GPIO Address Map (Sheet 2 of 2) GPIOBASE + Offset Mnemonic 20h–23h GP_SB_CMDSTS 24h–27h 28h–29h 2Ah–2Bh GPI_NMI_STS 2Ch–2Fh GPI_INV GPIO Signal Invert 30h–33h GPIO_USE_SEL2 GPIO Use Select 2 Register Name Default Attribute GP Serial Blink Command Status 00080000h R/W GP_SB_DATA GP Serial Blink Data 00000000h R/W GPI_NMI_EN GPI NMI Enable 0000h R/W 0000h R/WC 00000000h R/W GPI NMI Status R/W 020300FFh 7.
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LPC Interface Bridge Registers (D31:F0) Bit Description 12:0 GPIO_USE_SEL[12:0] — R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. Notes: 7.10.2 1. The following bits are always 1 because they are always unmultiplexed: 8, 15, 24, 27, and 28. 2.
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LPC Interface Bridge Registers (D31:F0) 7.10.4 Bit Description 12:0 GP_LVL[12:0]— R/W. These registers are implemented as dual read/write with dedicated storage each. Write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin.
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LPC Interface Bridge Registers (D31:F0) 7.10.5 GP_SER_BLINK—GP Serial Blink Register Offset Address: Default Value: Lockable: R/W 32 bits Core for 0:7, 16:23, Resume for 8:15, 24:31 Description 31:14 GP_SER_BLINK[31:14] — R/W. The setting of this bit has no effect if the corresponding GPIO is programmed as an input or if the corresponding GPIO has the GPO_BLINK bit set. When set to a 0, the corresponding GPIO will function normally.
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LPC Interface Bridge Registers (D31:F0) Bit 7:1 0 7.10.7 Description Reserved Go — R/W. This bit is set to 1 by software to start the serialization process. Hardware clears the bit after the serialized data is sent. Writes of 0 to this register have no effect. Software should not write this bit to 1 unless the Busy status bit is cleared. GP_SB_DATA—GP Serial Blink Data Register Offset Address: Default Value: Lockable: 7.10.
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LPC Interface Bridge Registers (D31:F0) 7.10.10 GPI_INV—GPIO Signal Invert Register Offset Address: Default Value: Lockable: GPIOBASE +2Ch 00000000h No Bit R/W 32 bits Core for 17, 16, 7:0 Description 31:16 Reserved 15:14 Input Inversion (GP_INV[n]) — R/W. This bit only has effect if the corresponding GPIO is used as an input and used by the GPE logic, where the polarity matters. When set to ‘1’, then the GPI is inverted as it is sent to the GPE logic that is using it.
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LPC Interface Bridge Registers (D31:F0) 7.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register Offset Address: Default Value: Lockable: GPIOBASE +34h 1F57FFF4h Yes Attribute: R/W Power Well: Core for 0:7, 16:23, Resume for 8:15, 24:31 This register corresponds to GPIO[63:32]. Bit 31:0 Description GP_IO_SEL2[63:32] — R/W. 0 = GPIO signal is programmed as an output. 1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is programmed as an input.
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LPC Interface Bridge Registers (D31:F0) Bit 11:0 Description GPIO_USE_SEL3[75:64]— R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO. Notes: 7.10.15 1. The following bit is always 1 because it is always unmultiplexed: 8 2. If GPIO[n] does not exist, then, the (n-64) bit in this register will always read as 0 and writes will have no effect. 3.
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LPC Interface Bridge Registers (D31:F0) Bit Description 11:0 GP_LVL[75:64] — R/W. These registers are implemented as dual read/write with dedicated storage each. Write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will drive a high or low value on the output pin.
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LPC Interface Bridge Registers (D31:F0) Bit Description 14:8 GP_RST_SEL[46:40] — R/W. 0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or SYS_RESET# assertion. 1 = Corresponding GPIO registers will be reset by RSMRST# assertion only. 7:0 7.10.
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SATA Controller Registers (D31:F2) 8 SATA Controller Registers (D31:F2) 8.1 PCI Configuration Registers (SATA–D31:F2) Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 8-1.
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SATA Controller Registers (D31:F2) Table 8-1.
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SATA Controller Registers (D31:F2) 8.1.3 PCICMD—PCI Command Register (SATA–D31:F2) Address Offset: Default Value: 04h–05h 0000h Bit 15:11 10 9 8.1.4 RO, R/W 16 bits Description Reserved Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 1 = Internal INTx# messages will not be generated. Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
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SATA Controller Registers (D31:F2) Bit 5 66MHz Capable (66MHZ_CAP) — RO. Hardwired to 1. 4 Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities list. The minimum requirement for the capabilities list must be PCI power management for the SATA controller. 3 Interrupt Status (INTS) — RO. Reflects the state of INTx# messages, IRQ14 or IRQ15. 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register [offset 04h]).
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SATA Controller Registers (D31:F2) 8.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h Address Offset: Default Value: 09h 01h Attribute: Size: Bit 7:0 8.1.7 Description Interface (IF) — RO. Indicates that the SATA Controller is an AHCI HBA that has a major revision of 1.
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SATA Controller Registers (D31:F2) 8.1.11 PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2) Address Offset: Default Value: 10h–13h 00000001h Bit 31:16 15:3 2:1 0 Note: 8.1.12 Description Base Address — R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
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SATA Controller Registers (D31:F2) Bit 1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Note: 8.1.15 Description This 4-byte I/O space is used in native mode for the Secondary Controller’s Control Block.
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SATA Controller Registers (D31:F2) Note: 8.1.16.2 The ABAR register must be set to a value of 0001_0000h or greater. When SCC is 01h When the programming interface is IDE, the register becomes an I/O BAR allocating 16 bytes of I/O space for the I/O-mapped registers defined in Section 8.2. Although 16 bytes of locations are allocated, only 8 bytes are used as SINDX and SDATA registers; with the remaining 8 bytes preserved for future enhancement.
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SATA Controller Registers (D31:F2) 8.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) Address Offset: 3Ch Default Value: 00h Function Level Reset:No Bit 7:0 8.1.21 R/W 8 bits Description Interrupt Line — R/W. This field is used to communicate to software the interrupt line that the interrupt pin is connected to. Interrupt Line register is not reset by FLR. INT_PN—Interrupt Pin Register (SATA–D31:F2) Address Offset: Default Value: 3Dh See Register Description Bit 7:0 8.1.
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SATA Controller Registers (D31:F2) 8.1.24 SDMA_CNT—Synchronous DMA Control Register (SATA– D31:F2) Address Offset: Default Value: Note: 48h 00h Description 7:4 Reserved 3:0 SDMA_CNT Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. SDMA_TIM—Synchronous DMA Timing Register (SATA– D31:F2) Address Offset: Default Value: Note: 4Ah–4Bh 0000h Description Reserved 13:12 SDMA_TIM Field 4— R/W.
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SATA Controller Registers (D31:F2) 8.1.27 PID—PCI Power Management Capability Identification Register (SATA–D31:F2) Address Offset: Default Value: 70h–71h See Register Description Bits 15:8 7:0 8.1.28 RO 16 bits Description Next Capability (NEXT) — R/W. A8h is the location of the Serial ATA capability structure. A8h is the recommended setting for non-IDE mode. If the controller is to operate in IDE mode, BIOS is requested to program this field to 00h. Note: Refer to the SGC.
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SATA Controller Registers (D31:F2) Bits Description 8 PME Enable (PMEE) — R/W. When set, the SATA controller asserts PME# when exiting D3HOT on a wake event. Note: When SCCSCC = 01h, hardware will automatically change the attribute of this bit to RO 0. Software is advised to clear PMEE and PMES together prior to changing SCC thru MAP.SMS. This bit is not reset by Function Level Reset. 7:4 3 2 1:0 8.1.30 Reserved No Soft Reset (NSFRST) — RO.
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SATA Controller Registers (D31:F2) Bits 15:8 7 6:4 Description Reserved 64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only. Multiple Message Enable (MME) — RO. = 000 (and MSIE is set), a single MSI message will be generated for all SATA ports, and bits [15:0] of the message vector will be driven from MD[15:0].
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SATA Controller Registers (D31:F2) 8.1.33 MSIMD—Message Signaled Interrupt Message Data Register (SATA–D31:F2) Address Offset: Default Value: Note: 88h–89h 0000h R/W 16 bits There is no support for MSI when the software is operating in legacy (IDE) mode when AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make sure that MSI is disabled. Bits 15:0 8.1.34 Attribute: Size: Description Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is enabled.
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SATA Controller Registers (D31:F2) 8.1.35 PCS—Port Control and Status Register (SATA–D31:F2) Address Offset: 92h–93h Default Value: 0000h Function Level Reset: No Attribute: Size: R/W, RO 16 bits By default, the SATA ports are set to the disabled state (bits [5:0] = 0). When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. When disabled, the port is in the “off” state and cannot detect any devices.
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SATA Controller Registers (D31:F2) Bits 5 4 3 Description Port 5 Enabled (P5E) — R/W / RO. 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. Notes: 1. This bit takes precedence over P5CMD.SUD (offset ABAR+398h:bit 1) 2. If MAP.SC is 0, SCC is 01h, MAP.SPD[5] is 1h,or set to a PCIe* Port then this bit will be read only 0. Port 4 Enabled (P4E) — R/W / RO. 0 = Disabled.
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SATA Controller Registers (D31:F2) Bit Description 29:24 Port Clock Disable (PCD) — R/W. 0 = All clocks to the associated port logic will operate normally. 1 = The backbone clock driven to the associated port logic is gated and will not toggle. Bit 29: Port 5 Bit 28: Port 4 Bit 27: Port 3 BIt 26: Port 2 Bit 25: Port 1 Bit 24: Port 0 If a port is not available, software shall set the corresponding bit to 1. Software can also set the corresponding bits to 1 on ports that are disabled.
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SATA Controller Registers (D31:F2) Bit 19:16 15:8 7:0 Description Minor Revision (MINREV) — RO. Minor revision number of the SATA Capability Pointer implemented. Next Capability Pointer (NEXT) — R/WO. Points to the next capability structure. These bits are not reset by Function Level Reset. Capability ID (CAP)— RW. The value 00h indicates the final item in the SATA Capability List. Note: 8.1.39 Refer to the SGC.REGLOCK description in order to lock the register to become RO.
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SATA Controller Registers (D31:F2) 8.1.41 FLRCLV—FLR Capability Length and Version Register (SATA–D31:F2) Address Offset: B2–B3h Attribute: Default Value: xx06h Size: Function Level Reset:No (Bit 9:8 Only when FLRCSSEL = 0) RO, R/WO 16 bits When FLRCSSEL (RCBA+3410h:bit 12) = 1, this register is RO: Bit 15:10 Reserved 9 FLR Capability — R/WO. 1 = Support for Function Level reset. This bit is not reset by the Function Level Reset. 8 TXP Capability — R/WO.
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SATA Controller Registers (D31:F2) 8.1.44 ATS—APM Trapping Status Register (SATA–D31:F2) Address Offset: C4h Default Value: 00h Function Level Reset:No Attribute: Size: R/WC 8 bits . Bit 7:4 8.1.45 Description Reserved 3 Secondary Slave Trap (SST) — R/WC. Indicates that a trap occurred to the secondary slave device. 2 Secondary Master Trap (SPT) — R/WC. Indicates that a trap occurred to the secondary master device. 1 Primary Slave Trap (PST) — R/WC.
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SATA Controller Registers (D31:F2) Bits Description 12 Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit field, Intel® Xeon® Processor D-1500 Product Family initiates a BIST FIS to the device on Port 2, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 2 is present and ready (not partial/slumber state).
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SATA Controller Registers (D31:F2) 8.1.47 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) Address Offset: Default Value: 8.1.48 E4h–E7h 00000000h R/W 32 bits Bits Description 31:0 BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form the contents of the second DWord of any BIST FIS initiated by Intel® Xeon® Processor D-1500 Product Family. This register is not port specific—its contents will be used for BIST FIS initiated on any port.
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SATA Controller Registers (D31:F2) 8.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) Address Offset: Default Value: Primary: BAR + 00h Secondary: BAR + 08h 00h Bit 7:4 3 2:1 0 8.2.2 Attribute: R/W Size: 8 bits Description Reserved. Returns 0. Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master transfer. This bit must NOT be changed when the bus master function is active. 0 = Memory reads 1 = Memory writes Reserved. Returns 0.
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SATA Controller Registers (D31:F2) Bit 8.2.3 Description 1 Error — R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when the controller encounters a target abort or master abort when transferring data on PCI. 0 Bus Master IDE Active (ACT) — RO. 0 = This bit is cleared by Intel® Xeon® Processor D-1500 Product Family when the last transfer for a region is performed, where EOT for that region is set in the region descriptor.
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SATA Controller Registers (D31:F2) 8.3 Serial ATA Index/Data Pair Superset Registers All of these I/O registers are in the core well. They are exposed only when SCC is 01h (that is, IDE programming interface). These are Index/Data Pair registers that are used to access the SerialATA superset registers (SerialATA Status (PxSSTS), SerialATA Control (PxSCTL) and SerialATA Error (PxSERR)). The I/O space for these registers is allocated through SIDPBA.
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SATA Controller Registers (D31:F2) 8.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) Address Offset: Default Value: Attribute: Size: 00000000h RO 32 bits SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state of the interface and host. Intel® Xeon® Processor D-1500 Product Family updates it continuously and asynchronously. When Intel® Xeon® Processor D-1500 Product Family transmits a COMRESET to the device, this register is updated to its reset values.
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SATA Controller Registers (D31:F2) Bit Description 11:8 Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which power states Intel® Xeon® Processor D-1500 Product Family is allowed to transition to: Value Description 0h No interface restrictions 1h Transitions to the PARTIAL state disabled 2h Transitions to the SLUMBER state disabled 3h Transitions to both PARTIAL and SLUMBER states disabled All other values reserved 7:4 Speed Allowed (SPD) — R/W.
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SATA Controller Registers (D31:F2) Bit Description 25 Unrecognized FIS Type (F): Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized. 24 Transport state transition error (T): Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared.
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SATA Controller Registers (D31:F2) The registers are broken into two sections – generic host control and port control. The port control registers are the same for all ports, and there are as many registers banks as there are ports. Table 8-3.
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SATA Controller Registers (D31:F2) Bit Description 28 Supports Mechanical Presence Switch (SMPS) — R/WO. When set to 1, indicates whether the SATA controller supports mechanical presence switches on its ports for use in Hot-Plug operations. This value is loaded by platform BIOS prior to OS initialization. If this bit is set, BIOS must also map the SATAGP pins to the SATA controller through GPIO space. 27 Supports Staggered Spin-up (SSS) — R/WO.
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SATA Controller Registers (D31:F2) 8.4.1.2 GHC—Global Intel® Xeon® Processor D-1500 Product Family Control Register (D31:F2) Address Offset: Default Value: Attribute: Size: R/W, RO 32 bits Bit Description 31 AHCI Enable (AE) — R/W. When set, this bit indicates that an AHCI driver is loaded and the controller will be talked to using AHCI mechanisms.
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SATA Controller Registers (D31:F2) 8.4.1.4 Bit Description 4 Interrupt Pending Status Port[4] (IPS[4]) — R/WC. 0 = No interrupt pending. 1 = Port 4 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt. 3 Interrupt Pending Status Port[3] (IPS[3]) — R/WC. 0 = No interrupt pending. 1 = Port 3 has an interrupt pending. Software can use this information to determine which ports require service after an interrupt.
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SATA Controller Registers (D31:F2) 8.4.1.5 VS—AHCI Version Register (D31:F2) Address Offset: Default Value: ABAR + 10h–13h 00010300h Attribute: Size: RO 32 bits This register indicates the major and minor version of the AHCI specification. It is BCD encoded. The upper two bytes represent the major version number, and the lower two bytes represent the minor version number. Example: Version 3.12 would be represented as 00030102h. The current version of the specification is 1.30 (00010300h).
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SATA Controller Registers (D31:F2) Bit 19 SGPIO Enclosure Management Messages (SUPP.SGPIO) — RO. 1 = The SATA controller supports the SGPIO register interface message type. 18 SES-2 Enclosure Management Messages (SUPP.SES2) — RO. 1 = The SATA controller supports the SES-2 message type. 17 SAF-TE Enclosure Management Messages (SUPP.SAFTE) — RO. 1 = The SATA controller supports the SAF-TE message type. 16 LED Message Types (SUPP.LED) — RO. 1 = The SATA controller supports the LED message type.
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SATA Controller Registers (D31:F2) Table 8-5.
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SATA Controller Registers (D31:F2) Table 8-5.
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SATA Controller Registers (D31:F2) 8.4.2.1 PxCLB—Port [5:0] Command List Base Address Register (D31:F2) Address Offset: Default Value: 100h Attribute: R/W 180h 200h (if port available; see Section 1.3) 280h (if port available; see Section 1.3) 300h 380h Size: 32 bits Bit Description Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the command list for this port. This base is used when fetching commands to execute. The structure pointed to by this address range is 1 KB in length.
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SATA Controller Registers (D31:F2) 8.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits Register (D31:F2) Address Offset: Default Value: Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR Undefined + + + + + + Bit 31:0 8.4.2.5 Description FIS Base Address Upper (FBU) — R/W. Indicates the upper 32-bits for the received FIS base for this port. These bits are not reset on a controller reset.
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SATA Controller Registers (D31:F2) 8.4.2.6 Bit Description 6 Port Connect Change Status (PCS) — RO. This bit reflects the state of PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this register, this bit is only cleared when PxSERR.DIAG.X is cleared. 0 = No change in Current Connect Status. 1 = Change in Current Connect Status. 5 Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has transferred all its data. 4 Unknown FIS Interrupt (UFS) — RO.
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SATA Controller Registers (D31:F2) 8.4.2.7 Bit Description 7 Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, Intel® Xeon® Processor D1500 Product Family will generate an interrupt. For systems that do not support an mechanical presence switch, this bit shall be a read-only 0. 6 Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS are set, Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
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SATA Controller Registers (D31:F2) Bit Description 27 Aggressive Slumber / Partial (ASP) — R/W. When set to 1, and the ALPE bit (bit 26) is set, Intel® Xeon® Processor D-1500 Product Family shall aggressively enter the slumber state when it clears the PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is set, Intel® Xeon® Processor D-1500 Product Family will aggressively enter the partial state when it clears the PxCI register and the PxSACT register is cleared. If CAP.
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SATA Controller Registers (D31:F2) Bit 12:8 7:5 8.4.2.8 Description Current Command Slot (CCS) — RO. Indicates the current command slot Intel® Xeon® Processor D-1500 Product Family is processing. This field is valid when the ST bit is set in this register, and is constantly updated by Intel® Xeon® Processor D-1500 Product Family.
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SATA Controller Registers (D31:F2) Bit 7:0 8.4.2.9 Description Status (STS) — RO. Contains the latest copy of the task file status register. Fields in this register that affect AHCI.
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SATA Controller Registers (D31:F2) Bit 11:8 Description Interface Power Management (IPM) — RO. Indicates the current interface state: Value Description 0h Device not present or communication not established 1h Interface in active state 2h Interface in PARTIAL power management state 6h Interface in SLUMBER power management state All other values reserved. 7:4 Current Interface Speed (SPD) — RO. Indicates the negotiated interface communication speed.
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SATA Controller Registers (D31:F2) Bit Description 11:8 Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which power states Intel® Xeon® Processor D-1500 Product Family is allowed to transition to: Value Description 0h No interface restrictions 1h Transitions to the PARTIAL state disabled 2h Transitions to the SLUMBER state disabled 3h Transitions to both PARTIAL and SLUMBER states disabled All other values reserved 7:4 Speed Allowed (SPD) — R/W.
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SATA Controller Registers (D31:F2) Bit 31:27 Description Reserved 26 Exchanged (X) — R/WC. When set to 1, this bit indicates that a change in device presence has been detected since the last time this bit was cleared. This bit shall always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit. 25 Unrecognized FIS Type (F) — R/WC. Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized.
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SATA Controller Registers (D31:F2) 8.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2) Address Offset: Default Value: 8.4.2.14 Port 0: ABAR Port 1: ABAR Port 2: ABAR Port 3: ABAR Port 4: ABAR Port 5: ABAR 00000000h + + + + + + 134h Attribute: R/W 1B4h 234h (if port available; see Section 1.3) 2B4h (if port available; see Section 1.3) 334h 3B4h Size: 32 bits Bit Description 31:0 Device Status (DS) — R/W.
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SATA Controller Registers (D31:F2) 370 Intel® Xeon® Processor D-1500 Product Family Datasheet - Volume 1 of 4: Integrated Platform Controller Hub March 2015
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SATA Controller Registers (D31:F5) 9 SATA Controller Registers (D31:F5) 9.1 PCI Configuration Registers (SATA–D31:F5) Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 9-1.
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SATA Controller Registers (D31:F5) Table 9-1.
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SATA Controller Registers (D31:F5) Bit 9.1.4 Description 5 VGA Palette Snoop (VPS) — RO. Hardwired to 0. 4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0. 3 Special Cycle Enable (SCE) — RO. Hardwired to 0. 2 Bus Master Enable (BME) — R/W. This bit controls Intel® Xeon® Processor D-1500 Product Family ability to act as a PCI master for IDE Bus Master transfers. This bit does not impact the generation of completions for split transaction commands. 1 Memory Space Enable (MSE) — RO.
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SATA Controller Registers (D31:F5) 9.1.5 RID—Revision Identification Register (SATA—D31:F5) Offset Address: Default Value: 08h See bit description Bit 7:0 9.1.6 Attribute: Size: RO 8 bits Description Revision ID — RO. This field indicates the device specific revision identifier. PI—Programming Interface Register (SATA–D31:F5) Address Offset: Default Value: 09h 85h Attribute: Size: RO 8 bits When SCC = 01h Bit 7 6:4 9.1.
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SATA Controller Registers (D31:F5) 9.1.9 PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F5) Address Offset: Default Value: 10h–13h 00000001h Bit 31:16 15:3 2:1 0 Note: 9.1.10 Description Base Address — R/W. This field provides the base address of the I/O space (8 consecutive I/O locations). Reserved Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
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SATA Controller Registers (D31:F5) Bit 1 Reserved 0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space. Note: 9.1.13 Description This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block.
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SATA Controller Registers (D31:F5) 9.1.15 SVID—Subsystem Vendor Identification Register (SATA– D31:F5) Address Offset: 2Ch–2Dh Default Value: 0000h Lockable: No Function Level Reset:No Bit 15:0 9.1.16 Description SID—Subsystem Identification Register (SATA–D31:F5) 2Eh–2Fh 0000h No Bit 15:0 R/WO 16 bits Core Description CAP—Capabilities Pointer Register (SATA–D31:F5) 34h 70h Bit 7:0 Attribute: Size: RO 8 bits Description Capabilities Pointer (CAP_PTR) — RO.
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SATA Controller Registers (D31:F5) 9.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5) Address Offset: Default Value: Primary: 40h–41h Secondary: 42h–43h 0000h Attribute: R/W Size: 16 bits Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These bits have no effect on hardware. Bit 15 14:12 IDE_TIM Field 2 — R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 11:10 Reserved 9:0 9.1.
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SATA Controller Registers (D31:F5) 9.1.23 IDE_CONFIG—IDE I/O Configuration Register (SATA– D31:F5) Address Offset: Default Value: Note: 54h–57h 00000000h Description 31:24 Reserved 23:16 IDE_CONFIG Field 6 — R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 15 Reserved 14 IDE_CONFIG Field 5 — R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. 13 Reserved 12 IDE_CONFIG Field 4 — R/W.
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SATA Controller Registers (D31:F5) Bits 5 Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-specific initialization is required. 4 Reserved 3 PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to generate PME#. 2:0 9.1.26 Description Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI Power Management Specification.
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SATA Controller Registers (D31:F5) 9.1.27 MAP—Address Map Register (SATA–D31:F5) Address Offset: 90h–91h Default Value: 0000h Function Level Reset: No (Bits 9:8 only) Bits 15:8 9.1.28 Attribute: Size: R/W, R/WO, RO bits Description Reserved 7:6 SATA Mode Select (SMS) — R/W. Software programs these bits to control the mode in which the SATA Controller should operate. 00b = IDE Mode All other combinations are reserved. 5:2 Reserved 1:0 Map Value (MV)— Reserved.
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SATA Controller Registers (D31:F5) Bits 0 9.1.29 Description Port 4 Enabled (P4E) — R/W. 0 = Disabled. The port is in the ‘off’ state and cannot detect any devices. 1 = Enabled. The port can transition between the on, partial, and slumber states and can detect devices. This bit is read-only 0 when MAP.SPD[0]= 1 or is a PCIe Port.
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SATA Controller Registers (D31:F5) 9.1.32 FLRCLV—FLR Capability Length and Value Register (SATA– D31:F5) Address Offset: B2h–B3h Default Value: 2006h Function Level Reset:No (Bits 9:8 only) Attribute: Size: RO, R/WO 16 bits When FLRCSSEL = 0, this register is RO: Bit 15:10 Reserved 9 FLR Capability — R/WO. This field indicates support for Function Level Reset. 8 TXP Capability — R/WO. This field indicates support for the Transactions Pending (TXP) bit. TXP must be supported if FLR is supported.
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SATA Controller Registers (D31:F5) 9.2 Bus Master IDE I/O Registers (D31:F5) The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR register, located in D31:F2 Configuration space, offset 20h. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). These registers are only used for legacy operation.
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SATA Controller Registers (D31:F5) Bit Description 0 Start/Stop Bus Master (START) — R/W. 0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped and then resumed.
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SATA Controller Registers (D31:F5) 9.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F5) Address Offset: Default Value: Attribute: R/W Size: 32 bits Bit Description 31:2 Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits [31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor Table must be DWordaligned. The Descriptor Table must not cross a 64-K boundary in memory. 1:0 9.
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SATA Controller Registers (D31:F5) 9.3.2.1 Bit Description 31:0 Data (DATA)— R/W. This Data register is a “window” through which data is read or written to the memory mapped registers. A read or write to this Data register triggers a corresponding read or write to the memory mapped register pointed to by the Index register. The Index register must be setup prior to the read or write to this Data register.
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SATA Controller Registers (D31:F5) 9.3.2.2 PxSCTL — Serial ATA Control Register (D31:F5) Address Offset: Default Value: Attribute: Size: 00000004h R/W, RO 32 bits SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software controls SATA capabilities. Writes to the SControl register result in an action being taken by Intel® Xeon® Processor D1500 Product Family or the interface. Reads from the register return the last value written to it.
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SATA Controller Registers (D31:F5) 9.3.2.3 PxSERR—Serial ATA Error Register (D31:F5) Address Offset: Default Value: 00000000h Attribute: Size: R/WC 32 bits SDATA when SINDx.RIDX is 02h. Bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bits 11:0 contain error information used by host software in determining the appropriate response to the error condition.
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SATA Controller Registers (D31:F5) 390 Intel® Xeon® Processor D-1500 Product Family Datasheet - Volume 1 of 4: Integrated Platform Controller Hub March 2015
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EHCI Controller Registers (D29:F0) 10 EHCI Controller Registers (D29:F0) 10.1 USB EHCI Configuration Registers (USB EHCI— D29:F0) Note: Prior to BIOS initialization of Intel® Xeon® Processor D-1500 Product Family USB subsystem, the EHCI controllers will appear as Function 7. After BIOS initialization, the EHCI controllers will be Function 0. Note: Register address locations that are not shown in Table 10-1 should be treated as Reserved (see Section 4.2 for details). Table 10-1.
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EHCI Controller Registers (D29:F0) Table 10-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F0) (Sheet 2 of 2) Offset Mnemonic 64h PDO Register Name Port Disable Override Register Attribute 0000h R/W, RO 66h RMHDEVR 0000h R/W, RO 68h–6Bh LEG_EXT_CAP USB EHCI Legacy Support Extended Capability 00000001h R/W, RO 6Ch–6Fh LEG_EXT_CS USB EHCI Legacy Extended Support Control/Status 00000000h R/W, R/WC, RO 70h–73h SPECIAL_SMI Intel Specific USB 2.
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EHCI Controller Registers (D29:F0) Bit Description 8 SERR# Enable (SERR_EN) — R/W. 0 = Disables EHC’s capability to generate an SERR#. 1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR# in the following cases: • When it receive a completion status other than “successful” for one of its DMA initiated memory reads on it’s internal interface. • When it detects an address or command parity error and the Parity Error Response bit is set.
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EHCI Controller Registers (D29:F0) Bit Description 12 Received Target Abort (RTA) — R/WC. 0 = No target abort received by EHC on memory access. 1 = This bit is set when EHC, as a master, receives a target abort status on a memory access. This is treated as a Host Error and halts the DMA engines. This event can optionally generate an SERR# by setting the SERR# Enable bit (D29:F0:04h, bit 8). 11 Signaled Target Abort (STA) — RO.
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EHCI Controller Registers (D29:F0) 10.1.8 BCC—Base Class Code Register (USB EHCI—D29:F0) Address Offset: Default Value: 0Bh 0Ch Bit 7:0 10.1.9 Base Class Code (BCC) — RO. 0Ch = Serial bus controller. PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F0) 0Dh 00h Bit 7:0 Attribute: Size: RO 8 bits Description Master Latency Timer Count (MLTC) — RO. Hardwired to 00h.
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EHCI Controller Registers (D29:F0) 10.1.12 SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F0) Address Offset: Default Value: Reset: 2Ch–2Dh XXXXh None Bit 15:0 Subsystem Vendor ID (SVID) — R/W. This register, in combination with the USB 2.0 Subsystem ID register, enables the operating system to distinguish each subsystem from the others. Writes to this register are enabled when the WRT_RDONLY bit (D29:F0:80h, bit 0) is set to 1.
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EHCI Controller Registers (D29:F0) 10.1.16 INT_PN—Interrupt Pin Register (USB EHCI—D29:F0) Address Offset: Default Value: 3Dh See Description Bit 7:0 Interrupt Pin — RO. This reflects the value of D29IP.E1IP (Chipset Config Registers:Offset 3108:bits 3:0) or D26IP.E2IP (Chipset Config Registers:Offset 3114:bits 3:0). Note: As a single function device, only INTA# may be used while the other three interrupt lines have no meaning. (refer to PCI 3.0 specification, Section 2.2.6, Interrupt Pins).
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EHCI Controller Registers (D29:F0) Bit 5 Description Device Specific Initialization (DSI)— RO. Intel® Xeon® Processor D-1500 Product Family reports 0, indicating that no device-specific initialization is required. 4 Reserved 3 PME Clock (PME_CLK) — RO. Intel® Xeon® Processor D-1500 Product Family reports 0, indicating that no PCI clock is required to generate PME#. 2:0 Version (VER) — RO. Intel® Xeon® Processor D-1500 Product Family reports 010b, indicating that it complies with Revision 1.
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EHCI Controller Registers (D29:F0) 10.1.21 DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F0) Address Offset: Default Value: 10.1.22 58h 0Ah Bit Description Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a Debug Port Capability structure. NXT_PTR2—Next Item Pointer #2 Register (USB EHCI— D29:F0) Bit 7:0 RO 8 bits Next Item Pointer 2 Capability — RO. This register points to the next capability in the Function Level Reset capability structure.
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EHCI Controller Registers (D29:F0) is operating yields undefined results. It should not be reprogrammed by USB system software unless the default or BIOS programmed values are incorrect, or the system is restoring the register while returning from a suspended state. These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset. Bit 10.1.26 Description 7:6 Reserved — RO. These bits are reserved for future use and should read as 00b. 5:0 Frame Length Timing Value — R/W.
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EHCI Controller Registers (D29:F0) 10.1.27 PDO—Port Disable Override Register Address Offset: Default Value: Power Well: 64h 0000h Suspend Bit 15:8 7:0 10.1.28 Description USB Port Disable: A ‘1’ in a bit position prevents the corresponding USB port from reporting a Device Connection to the hub. Attempts to enable the port will be ignored by the hardware when this bit is 1. This register cannot be written when the USB Per-Port Registers Write Enable bit (in Power Management I/O Space) is 0.
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EHCI Controller Registers (D29:F0) 10.1.30 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F0) Address Offset: 6C–6Fh Default Value: 00000000h Power Well: Suspend Function Level Reset: No Note: R/W, R/WC, RO 32 bits These bits are not reset by a D3-to-D0 warm rest or a core well reset. Bit Description 31 SMI on BAR — R/WC. Software clears this bit by writing a 1 to it. 0 = Base Address Register (BAR) not written.
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EHCI Controller Registers (D29:F0) 10.1.31 Bit Description 5 SMI on Async Advance Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F0:6Ch, bit 21) is a 1, the host controller will issue an SMI immediately. 4 SMI on Host System Error Enable — R/W. 0 = Disable. 1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F0:6Ch, bit 20) is a 1, the host controller will issue an SMI. 3 SMI on Frame List Rollover Enable — R/W. 0 = Disable.
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EHCI Controller Registers (D29:F0) Bit 16 10.1.32 Description SMI on HCReset — R/WC. Software clears this bit by writing a 1 it. 0 = HCRESET did Not transitioned to 1. 1 = HCRESET transitioned to 1. 15:6 SMI on PortOwner Enable — R/W. 0 = Disable. 1 = Enable. When any of these bits are 1 and the corresponding SMI on PortOwner bits are 1, then the host controller will issue an SMI. Unused ports should have their corresponding bits cleared. 5 SMI on PMSCR Enable — R/W. 0 = Disable. 1 = Enable.
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EHCI Controller Registers (D29:F0) Bit 15:08 Description OC1Mapping Each bit position maps OC1 (EHCI 1) to a set of ports as follows: EHCI 1: Map OC1 Bit: Port: 15 X 14 13 12 11 10 9 8 X X X 3 2 1 0 It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin.
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EHCI Controller Registers (D29:F0) Bit Description 0 10.1.35 WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally read-only registers in the EHC function to be written by software. Registers that may only be written when this mode is entered are noted in the summary tables and detailed description as “Read/Write-Special”. The registers fall into two categories: 1. System-configured parameters 2.
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EHCI Controller Registers (D29:F0) 10.1.38 FLR_CLV—Function Level Reset Capability Length and Version Register (USB EHCI—D29:F0) Address Offset: 9Ah–9Bh Default Value: 0306h Function Level Reset: No Attribute: Size: R/WO, RO 16 bits When FLRCSSEL = 0, this register is defined as follows: Bit 15:10 Reserved 9 FLR Capability — R/WO. 1 = Support for Function Level Reset (FLR). 8 TXP Capability — R/WO. 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. 7:0 10.
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EHCI Controller Registers (D29:F0) Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory range are ignored and result a master abort. Similarly, if the Memory Space Enable (MSE) bit (D29:F0:04h, bit 1) is not set in the Command register in configuration space, the memory range will not be decoded by Intel® Xeon® Processor D-1500 Product Family enhanced host controller (EHC).
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EHCI Controller Registers (D29:F0) 10.2.1.2 HCIVERSION—Host Controller Interface Version Number Register Offset: Default Value: MEM_BASE + 02h–03h 0100h Bit 15:0 10.2.1.3 Host Controller Interface Version Number — RO. This is a two-byte register containing a BCD encoding of the version number of interface that this host controller interface conforms.
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EHCI Controller Registers (D29:F0) Bit Description 3 Reserved 2 Asynchronous Schedule Park Capability — RO. This bit is hardwired to 0 indicating that the host controller does not support this optional feature 1 Programmable Frame List Flag — RO. 0 = System software must use a frame list length of 1024 elements with this host controller. The USB2.0_CMD register (D29:F0:CAPLENGTH + 20h, bits 3:2) Frame List Size field is a read-only register and must be cleared to 0.
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EHCI Controller Registers (D29:F0) The second set at offsets MEM_BASE + 60h to the end of the implemented register space are implemented in the Suspend power well. Unless otherwise noted, the suspend well registers are reset by the assertion of either of the following: • Suspend well hardware reset • HCRESET 10.2.2.1 USB2.0_CMD—USB 2.
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EHCI Controller Registers (D29:F0) Bit Description 4 Periodic Schedule Enable — R/W. This bit controls whether the host controller skips processing the Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. 3:2 Frame List Size — RO. This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one. This field specifies the size of the frame list.
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EHCI Controller Registers (D29:F0) Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has no effect. Bit 31:16 15 Description Reserved Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the Asynchronous Schedule. 0 = Disabled. (Default) 1 = Enabled.
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EHCI Controller Registers (D29:F0) Bit 0 10.2.2.3 Description USB Interrupt (USBINT) — R/WC. 0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set. No short packet is detected. 1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set.
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EHCI Controller Registers (D29:F0) 10.2.2.4 FRINDEX—Frame Index Register Offset: Default Value: MEM_BASE + 2Ch–2Fh 00000000h Attribute: Size: R/W, RO 32 bits The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. Refer to Section 4 of the EHCI specification for a detailed explanation of the SOF value management requirements on the host controller. The value of FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token value.
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EHCI Controller Registers (D29:F0) 10.2.2.6 Bit Description 11:0 Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when forming a control data structure address. PERIODICLISTBASE—Periodic Frame List Base Address Register Offset: Default Value: MEM_BASE + 34h–37h 00000000h Attribute: Size: R/W 32 bits This 32-bit register contains the beginning address of the Periodic Frame List in the system memory.
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EHCI Controller Registers (D29:F0) 10.2.2.9 Note: Bit Description 0 Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process of configuring the Host controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below. See Chapter 4 of the EHCI specification for operation details. 0 = Compatibility debug only (default). 1 = Port routing control logic default-routes all ports to this host controller.
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EHCI Controller Registers (D29:F0) Bit Description 19:16 Port Test Control — R/W. When this field is 0s, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value.
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EHCI Controller Registers (D29:F0) Bit 7 Description Suspend — R/W. 0 = Port not in suspend state.(Default) 1 = Port in suspend state. Port Enabled Bit and Suspend bit of this register define the port states as follows: Port Enabled Suspend Port State 0 X Disabled 1 0 Enabled 1 1 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset.
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EHCI Controller Registers (D29:F0) Bit 0 10.2.3 Description Current Connect Status — RO. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 0 = No device is present. (Default) 1 = Device is present on port. USB 2.0-Based Debug Port Registers The Debug port’s registers are located in the same memory area, defined by the Base Address Register (MEM_BASE), as the standard EHCI registers.
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EHCI Controller Registers (D29:F0) Bit Description 11 Reserved 10 IN_USE_CNT — R/W. Set by software to indicate that the port is in use. Cleared by software to indicate that the port is free and may be used by other software. This bit is cleared after reset. (This bit has no affect on hardware.) 9:7 EXCEPTION_STS — RO. This field indicates the exception when the ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS bit is 0. 000 =No Error.
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EHCI Controller Registers (D29:F0) Bit 15:8 7:0 10.2.3.3 Description SEND_PID_CNT[15:8] — R/W. Hardware sends this PID to begin the data packet when sending data to USB (that is, WRITE_READ#_CNT is asserted). Software typically sets this field to either DATA0 or DATA1 PID values. TOKEN_PID_CNT[7:0] — R/W. Hardware sends this PID as the Token PID for each USB transaction. Software typically sets this field to either IN, OUT, or SETUP PID values.
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xHCI Controller Registers (D20:F0) 11 xHCI Controller Registers (D20:F0) 11.1 USB xHCI Configuration Registers (USB xHCI— D20:F0) Note: Register address locations that are not shown in Table 11-1 should be treated as Reserved (see Section 4.2 for details). Note: “Multiple” in the Power Well column means that multiple power wells apply to this register since the individual fields in the register may be on different power wells. Table 11-1.
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xHCI Controller Registers (D20:F0) Table 11-1.
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xHCI Controller Registers (D20:F0) Bit 11.2.3 Description 9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. 8 SERR# Enable (SERR_EN) — R/W. 0 = Disables xHC’s capability to generate an SERR#. 1 = The xHCI Host controller (xHC) is capable of generating (internally) SERR# in the following cases: — When it receive a completion status other than “successful” for one of its DMA initiated memory reads on its internal interface.
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xHCI Controller Registers (D20:F0) Bit 10:9 DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for DEVSEL# assertion. 8 Master Data Parity Error Detected (DPED) — R/WC. 0 = No data parity error detected on USB read completion packet. 1 = This bit is set by Intel® Xeon® Processor D-1500 Product Family when a data parity error is detected on a xHC read completion packet on the internal interface to the xHCI host controller and bit 6 of the Command register is set to 1.
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xHCI Controller Registers (D20:F0) 11.2.8 PMLT—Primary Master Latency Timer Register (USB xHCI—D20:F0) Address Offset: Default Value: 0Dh 00h Bit 7:0 11.2.9 Description HEADTYP—Header Type Register (USB xHCI—D20:F0) 0Eh 00h Bit 7 6:0 Attribute: Size: RO 8 bits Description Multi-Function Device — RO. When set to ‘1’ indicates this is a multifunction device: 0 = Single-function device 1 = Multi-function device. Configuration Layout.
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xHCI Controller Registers (D20:F0) 11.2.12 SVID—USB xHCI Subsystem Vendor ID Register (USB xHCI—D20:F0) Address Offset: Default Value: Reset: 2Ch–2Dh 0000h None Bit 15:0 11.2.13 Subsystem Vendor ID (SVID) — R/W. This register, in combination with the xHC Subsystem ID register, enables the operating system to distinguish each subsystem from the others. SID—USB xHCI Subsystem ID Register (USB xHCI— D20:F0) 2Eh–2Fh 0000h None 15:0 Subsystem ID (SID) — R/W.
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xHCI Controller Registers (D20:F0) 11.2.17 XHCC—xHC System Bus Configuration Register (USB xHCI—D20:F0) Address Offset: Default Value: 40-43h 0000F0FDh Bit 31:25 Description Reserved Master/Target Abort SERR (RMTASERR) — R/W. When set, this bit allows the out-of-band error reporting from the xHCI Controller to be reported as SERR# (if SERR# reporting is enabled) and thus setting the STS.SSE bit. 23 Unsupported Request Detected (URD) — R/WC.
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xHCI Controller Registers (D20:F0) 11.2.20 FL_ADJ—Frame Length Adjustment Register (USB xHCI— D20:F0) Address Offset: 61h Default Value: 20h Function Level Reset: No Attribute: Size: R/W 8 bits This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written into these six bits, the length of the frame is adjusted.
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xHCI Controller Registers (D20:F0) 11.2.22 NXT_PTR1—Next Item Pointer #1 Register (USB xHCI— D20:F0) Address Offset: Default Value: 11.2.23 71h 80h Attribute: Size: R/W 8 bits Bit Description 7:0 Next Item Pointer 1 Value — R/W (special). This register defaults to 80h, which indicates that the next capability registers begin at configuration offset 80h. This register is writable when the ACCTRL bit (D20:F0:40h, bit 31) is ‘0’.
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xHCI Controller Registers (D20:F0) 11.2.24 PWR_CNTL_STS—Power Management Control / Status Register (USB xHCI—D20:F0) Address Offset: Default Value: 74h–75h 0000h Bit 15 Attribute: Size: R/W, R/WC, RO 16 bits Description PME Status — R/WC. This bit is set when Intel® Xeon® Processor D-1500 Product Family xHC would normally assert the PME# signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear it and cause the internal PME to de-assert (if enabled).
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xHCI Controller Registers (D20:F0) 11.2.27 MSI_MCTL— MSI Message Control Register (USB xHCI— D20:F0) Address Offset: Default Value: 82h-83h 0086h Bit 15:8 7 Description Reserved. 64 Bit Address Capable (C64) — RO. Capable of generating 64-bit messages. Multiple Message Enable (MME) — RW. Indicates the number of messages the controller should assert. This device supports multiple message MSI. 3:1 Multiple Message Capable (MMC) — RO.
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xHCI Controller Registers (D20:F0) 11.2.31 U2OCM1 - XHCI USB2 Overcurrent Mapping Register1 (USB xHCI—D20:F0) Address Offset: Default Value: Attribute: Size: Bit Description OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin.
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xHCI Controller Registers (D20:F0) 11.2.33 Bit Description 13:8 OC5 Mapping Each bit position maps OC5 to a set of ports as follows: The OC5 pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin.
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xHCI Controller Registers (D20:F0) 11.2.34 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2 (USB xHCI—D20:F0) Address Offset: Default Value: CC–CFh 00000000h Attribute: Size: Bit Description 31:30 Reserved 29:24 OC7 Mapping Each bit position maps OC7 to a set of ports as follows: The OC7 pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin.
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xHCI Controller Registers (D20:F0) 11.2.36 XUSB2PRM—xHC USB 2.0 Port Routing Mask Register (USB xHCI—D20:F0) Address Offset: Default Value: Note: D4–D7h 00000000h Description 31:15 14:0 Reserved. USB 2.0 Host Controller Selector Mask (USB2HCSELM) — R/W. This bit field allows the BIOS to communicate to the OS which USB 2.0 ports can be switched from the EHC controller to the xHC controller. When set to 1, the OS may switch the USB 2.
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xHCI Controller Registers (D20:F0) 11.2.39 Bit Description 5:0 USB 2.0 Host Controller Selector Mask (USB2HCSELM) — R/W. This bit field allows the BIOS to communicate to the OS which USB 3.0 ports can have the SuperSpeed capabilities enabled. When set to 1, the OS may enable or disable the SuperSpeed capabilities by modifying the corresponding USB3PSSEN bit (D20:F0:D8h, bit 3:0). When cleared to 0, the OS shall not modify the corresponding USB3PSSEN bit. Bit 0 = USB 3.0 Port 1 Bit 1 = USB 3.
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xHCI Controller Registers (D20:F0) should not be forwarded to PCI as the address space is known to be allocated to USB. Attempting to access the xHCI controller Memory-Mapped I/O space using locked memory transactions will result in undefined behavior. Note: When the xHCI function is in the D3 PCIe power state, accesses to the xHCI memory range are ignored and result in a master abort.
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xHCI Controller Registers (D20:F0) 11.3.1.3 HCSPARAMS1—Host Controller Structural Parameters #1 Register Offset: Default Value: RW/L 32 bits Description 31:24 Number of Ports (MaxPorts)— RW/L. This field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register Space. Default value = 15h 23:19 Reserved 7:0 Number of Interrupters (MaxIntrs) — RW/L.
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xHCI Controller Registers (D20:F0) Bit 7:0 Description U1 Device Exit Latency (U1DEL) — RW/L. Worst case latency to transition a root hub Port Link State (PLS) from U1 to U0. Applies to all root hub ports. The following are permissible values: Value Description 00h Zero 01h Less than 1 μs 02h Less than 2 μs ... 0800h-FFFFh 11.3.1.
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xHCI Controller Registers (D20:F0) 11.3.1.7 dBOFF—Doorbell Offset Register Offset: Default Value: Attribute: Size: Description 31:2 Doorbell Array Offset — RO. This field defines the DWord offset of the Doorbell Array base address from the Base (that is, the base address of the xHCI Capability register address space). Reserved. RTSOFF—Runtime Register Space Offset Register Offset: Default Value: MEM_BASE + 18h–1Bh 00001000h Attribute: Size: Bit 31:2 1:0 11.3.2 RO 32 bits Bit 1:0 11.3.1.
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xHCI Controller Registers (D20:F0) Table 11-3.
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xHCI Controller Registers (D20:F0) Bit Description 2 Interrupter Enable (INTE) — R/W. This bit provides system software with a means of enabling or disabling the host system interrupts generated by interrupters. When this bit is set to 1b, then Interrupter host system interrupt generation is allowed, such that the xHC shall issue an interrupt at the next interrupt threshold if the host system interrupt mechanism (such that MSI, MSIX, and so on) is enabled.
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xHCI Controller Registers (D20:F0) Bit Description 9 Restore State Status (RSS) ⎯ RO. When the Controller Restore State (CRS) flag in the USB_CMD register is written with 1b this bit shall be set to 1b and remain set while the xHC restores its internal state. Note: When the Restore State operation is complete, this bit shall be cleared to 0b. 8 Save State Status (SSS) ⎯ RO.
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xHCI Controller Registers (D20:F0) 11.3.2.5 CRCRL—Command Ring Control Low Register Offset: Default Value: MEM_BASE + 98h–9Bh 00000000h Attribute: Size: Bit 31:6 5:4 R/W, RO 32 bits Description Command Ring Pointer — R/W. This field defines low order bits of the initial value of the 64-bit Command Ring Dequeue Pointer. Notes: 1. Writes to this field are ignored when Command Ring Running bit (CRR) = 1b. 2.
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xHCI Controller Registers (D20:F0) 11.3.2.6 CRCRH—Command Ring Control High Register Offset: Default Value: MEM_BASE + 9Ch–9Fh 00000000h Bit 31:0 11.3.2.7 Command Ring Pointer — R/W. This field defines high order bits of the initial value of the 64-bit Command Ring Dequeue Pointer. Notes: 1. Writes to this field are ignored when Command Ring Running bit (CRR) = 1b. 2.
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xHCI Controller Registers (D20:F0) 11.3.2.10 PORTSCNUSB2—Port N Status and Control USB2 Register Offset: There are 15 USB2 PORTSC registers at offsets: 480h, 490h, 4A0h, 4B0h, 4C0h, 4D0h, 4E0h, 4F0h, 500h, 510h, 520h, 530h, 540h, 550h, 560h Attribute: Default Value: R/W, R/WC, RO, R/WO, R/WOC 000002A0h Size: 32 bits A host controller must implement one or more port registers. Software uses the N_Port information from the Structural Parameters Register to determine how many ports need to be serviced.
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xHCI Controller Registers (D20:F0) Bit Description 23 Port Config Error Change (CEC) — R/WOC. This flag indicates that the port failed to configure its link partner. Software shall clear this bit by writing a 1 to it. Note: This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0 capable-only ports. Note: This bit is in the Suspend Well. 22 Port Link State Change (PLC) — R/WC.
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xHCI Controller Registers (D20:F0) Bit 18 Description Port Enabled/Disabled Change (PEC) — R/WC. 0 = No change. (Default) 1 = There is a change to PED bit. Notes: 1. 17 Software shall clear this bit by writing a 1 to it. 3. For a USB 2.0-only port, this bit shall be set to 1 only when the port is disabled due to the appropriate conditions existing at the EOF2 point. (See Chapter 11 of the USB Specification for the definition of a port error). 4. For a USB 3.
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xHCI Controller Registers (D20:F0) Bit Description 8:5 Port Link State (PLS) — R/W. This field is used to power manage the port and reflects its current link state. When the port is in the Enabled state, system software may set the link U-state by writing this field. System software may also write this field to force a Disabled to Disconnected state transition of the port. Write Value Description 0 The link shall transition to a U0 state from any of the U-states. 2 USB 2.0 ports only.
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xHCI Controller Registers (D20:F0) 11.3.2.11 Bit Description 3 Overcurrent Active (OCA)— RO. 0 = This port does not have an overcurrent condition. (Default) 1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0 when the over current condition is removed. Intel® Xeon® Processor D-1500 Product Family automatically disables the port when the overcurrent active bit is 1. Note: This bit is in the Suspend Well. 2 Reserved. 1 Port Enabled/Disabled — R/W.
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xHCI Controller Registers (D20:F0) Bit 15:8 L1 Device Slot — R/W. System software sets this field to indicate the ID of the Device Slot associated with the device directly attached to the Root Hub port. A value of 0 indicates there is no device present. Note: This bit is in the Suspend Well. 7:4 Host Initiated Resume Duration (HIRD) — R/W. System software sets this field to indicate to the recipient device how long the xHC will drive resume if it (the xHC) initiates an exit from L1.
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xHCI Controller Registers (D20:F0) Bit Description 27 Wake on Over-current Enable (WOE) — R/W. 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to over-current conditions as system wake-up events. Note: This bit is in the Suspend Well. 26 Wake on Disconnect Enable (WDE) — R/W. 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device disconnects as system wake-up events. Note: This bit is in the Suspend Well.
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xHCI Controller Registers (D20:F0) Bit 21 Description Port Reset Change (PRC) — R/WC. This flag is set to ‘1’ due a '1' to '0' transition of Port Reset (PR); such as when any reset processing on this port is complete. 0 = No change 1 = Reset Complete Notes: 1. This bit shall not be set to 1b if the reset processing was forced to terminate due to software clearing the PP bit or PED bit to 0b. 2. Software shall clear this bit by writing a 1 to it. 3. This bit is in the Suspend Well.
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xHCI Controller Registers (D20:F0) Bit 13:10 Description Port Speed (Port_Speed). A device attached to this port operates at a speed defined by the following codes: Value Speed 0100 SuperSpeed (5 Gb/s) All other values reserved. Please refer to the eXtensible Host Controller Interface for Universal Serial Bus Specification for additional details. 9 Port Power (PP) — RO. Read-only with a value of 1. This indicates that the port does have power. Note: This bit is in the Suspend Well.
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xHCI Controller Registers (D20:F0) 11.3.2.13 Bit Description 4 Port Reset (PR) — R/W. When software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long enough to ensure the reset sequence completes as specified in the USB Specification, Revision 2.0. USB 3.0 ports shall execute the Hot Reset sequence as defined in the USB 3.
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xHCI Controller Registers (D20:F0) Bit Description 7:0 U1 Timeout — R/W. Timeout value for U1 inactivity timer. If equal to FFh, the port is disabled from initiating U1 entry. This field shall be cleared to 0 by the assertion of PR to 1. Refer to Section 4 of the xHCI Specification for more information on U1 Timeout operation. The following are permissible values: Value Description 00h Zero (default) 01h 1 μs 02h 2 μs ... 7Fh 80h-FEh FFh 11.3.2.14 127 μs Reserved Infinite PORTLIX— USB 3.
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xHCI Controller Registers (D20:F0) 11.3.3.1 MFINDEX—Microframe Index Register Offset: Default Value: Runtime Base + 00h-03h 00000000h Bit 31:14 13:0 11.3.3.2 Note: Reserved. Microframe Index — RO. The value in this register increments at the end of each microframe (such as 125 us.). Bits 13:3 may be used to determine the current 1ms. Frame Index.
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xHCI Controller Registers (D20:F0) 11.3.3.4 Bit Description 31:16 Interrupt Moderation Counter (IMODC) — R/W. Down counter. Loaded with Interval Moderation value (value of bits 15:0) whenever the IP bit is cleared to 0b, counts down to ‘0’, and stops. The associated interrupt shall be signaled whenever this counter is ‘0’, the Event Ring is not empty, the IE and IP bits = 1, and EHB = 0. This counter may be directly written by software at any time to alter the interrupt rate.
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xHCI Controller Registers (D20:F0) 11.3.3.6 ERSTBAH—Event Ring Segment Table Base Address High X Register Offset: 1: 2: 3: 4: 5: 6: 7: 8: Attribute: Default Value: Note: 11.3.3.7 R/W 00000000h Size: 32 bits There are 8 ERSTBAH registers. Bit Description 31:0 Event Ring Segment Table Base Address Register (ERSTBA_HI) — R/W. This field defines the low order bits of the start address of the Event Ring Segment Table. This field shall not be modified if HCHalted (HCH) = 0.
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xHCI Controller Registers (D20:F0) 11.3.3.8 ERDPH—Event Ring Dequeue Pointer High X Register Offset: 1: 2: 3: 4: 5: 6: 7: 8: Attribute: Default Value: Note: 11.3.4 Runtime Runtime Runtime Runtime Runtime Runtime Runtime Runtime Base Base Base Base Base Base Base Base + + + + + + + + 3Ch–3Fh 5Ch–5Fh 7Ch–7Fh 9Ch–9Fh BCh–BFh DCh–DFh FCh–FFh 11Ch–11Fh R/W 00000000h Size: 32 bits There are 8 ERDPH registers. Bit Description 31:0 Event Ring Dequeue Pointer — R/W.
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xHCI Controller Registers (D20:F0) Bit Description 31:16 dB Stream ID — R/W. If the endpoint of a Device Context Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the doorbell reference is targeting. System software is responsible for ensuring that the value written to this field is valid. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is written to this field, the doorbell reference shall be ignored.
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xHCI Controller Registers (D20:F0) 464 Intel® Xeon® Processor D-1500 Product Family Datasheet - Volume 1 of 4: Integrated Platform Controller Hub March 2015
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SMBus Controller Registers (D31:F3) 12 SMBus Controller Registers (D31:F3) 12.1 PCI Configuration Registers (SMBus—D31:F3) Table 12-1.
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SMBus Controller Registers (D31:F3) 12.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) Address: Default Value: 04h–05h 0000h Attributes: Size: Bit 15:11 10 12.1.4 Description Reserved Interrupt Disable — R/W. 0 = Enable 1 = Disables SMBus to assert its PIRQB# signal. 9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. 8 SERR# Enable (SERR_EN) — R/W. 0 = Enables SERR# generation. 1 = Disables SERR# generation. 7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
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SMBus Controller Registers (D31:F3) 3 2:0 12.1.5 Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent from the state of the Interrupt Enable bit in the PCI Command register. Reserved RID—Revision Identification Register (SMBus—D31:F3) Offset Address: Default Value: 08h See bit description Bit 7:0 12.1.6 Revision ID — RO. This field indicates the device specific revision identifier.
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SMBus Controller Registers (D31:F3) 12.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1 Register (SMBus—D31:F3) Address Offset: Default Value: 14h–17h 00000000h Bit 31:0 12.1.11 Description SMB_BASE—SMBus Base Address Register (SMBus— D31:F3) 20–23h 00000001h Bit 31:16 15:5 4:1 0 R/W, RO 32-bits Reserved — RO Base Address — R/W. This field provides the 32-byte system I/O base address for Intel® Xeon® Processor D-1500 Product Family ’s SMB logic. Reserved — RO IO Space Indicator — RO.
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SMBus Controller Registers (D31:F3) 12.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3) Address Offset: Default Value: 12.1.15 3Ch 00h Description 7:0 Interrupt Line (INT_LN) — R/W. This data is not used by Intel® Xeon® Processor D-1500 Product Family . It is to communicate to software the interrupt line that the interrupt pin is connected to PIRQB#. INT_PN—Interrupt Pin Register (SMBus—D31:F3) 3Dh See description Bit 7:0 Attributes: Size: RO 8 bits Description Interrupt PIN (INT_PN) — RO.
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SMBus Controller Registers (D31:F3) Table 12-2. SMBus I/O and Memory Mapped I/O Register Address Map SMB_BASE + Offset 12.2.
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SMBus Controller Registers (D31:F3) 12.2.2 Bit Description 6 INUSE_STS — R/W. This bit is used as semaphore among various independent software threads that may need to use Intel® Xeon® Processor D-1500 Product Family ’s SMBus logic, and has no other effect on hardware. 0 = After a full PCI reset, a read to this bit returns a 0. 1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has no effect.
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SMBus Controller Registers (D31:F3) Bit Description 6 START — WO. 0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset 00h) can be used to identify when Intel® Xeon® Processor D-1500 Product Family has finished the command. 1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers should be setup prior to writing a 1 to this bit position. 5 LAST_BYTE — WO. This bit is used for Block Read commands.
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SMBus Controller Registers (D31:F3) 12.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) Register Offset: Default Value: SMB_BASE + 03h 00h Bit 7:0 12.2.4 Attribute: Size: R/W 8 bits Description This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol during the execution of any command.
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SMBus Controller Registers (D31:F3) 12.2.7 Host_BLOCK_dB—Host Block Data Byte Register (SMBus— D31:F3) Register Offset: Default Value: 12.2.8 R/W 8 bits Bit Description Block Data (BDTA) — R/W. This is either a register, or a pointer into a 32-byte block array, depending upon whether the E32B bit is set in the Auxiliary Control register. When the E32B bit (offset SMB_BASE + 0Dh, bit 1) is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read.
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SMBus Controller Registers (D31:F3) 12.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) Register Offset: Default Value: Lockable: SMB_BASE + 0Ah–0Bh 0000h No Attribute: Size: Power Well: RO 16 bits Resume This register contains the 16-bit data value written by the external SMBus master. The processor can then read the value from this register. This register is reset by RSMRST#, but not PLTRST#. Bit 15:8 7:0 12.2.11 Description Data Message Byte 1 (DATA_MSG1) — RO. See Section 3.20.
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SMBus Controller Registers (D31:F3) 12.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register (SMBus— D31:F3) Register Offset: Default Value: Note: SMB_BASE + 0Eh See Description Attribute: Size: R/W, RO 8 bits This register is in the resume well and is reset by RSMRST#. This register is only applicable in the TCO compatible mode. Bit 7:3 12.2.14 Description Reserved 2 SMLINK_CLK_CTL — R/W.
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SMBus Controller Registers (D31:F3) All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. Bit 7:1 0 12.2.16 Description Reserved HOST_NOTIFY_STS — R/WC. Intel® Xeon® Processor D-1500 Product Family sets this bit to a 1 when it has completely received a successful Host Notify Command on the SMBus pins.
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SMBus Controller Registers (D31:F3) 12.2.18 NOTIFY_DLOW—Notify Data Low Byte Register (SMBus— D31:F3) Register Offset: Default Value: Note: 12.2.19 RO 8 bits Bit Description 7:0 DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set to 1.
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PCI Express* Configuration Registers 13 PCI Express* Configuration Registers 13.1 PCI Express* Configuration Registers (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Note: This section assumes the default PCI Express Function Number-to-Root Port mapping is used. Function numbers for a given root port are assignable through the Root Port Function Number and Hide for PCI Express Root Ports register (RCBA+0404h).
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PCI Express* Configuration Registers Table 13-1.
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PCI Express* Configuration Registers 13.1.1 VID—Vendor Identification Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 00h–01h 8086h Attribute: Size: Bit 15:0 13.1.2 Description Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h DID—Device Identification Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 13.1.
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PCI Express* Configuration Registers 13.1.4 Bit Description 2 Bus Master Enable (BME) — R/W. 0 = Disable. Memory and I/O requests received at a Root Port must be handled as Unsupported Requests. 1 = Enable. Allows the root port to forward Memory and I/O Read/Write cycles onto the backbone from a PCI Express* device.
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PCI Express* Configuration Registers 13.1.5 RID—Revision Identification Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) Offset Address: Default Value: 08h See bit description Bit 7:0 13.1.6 Description PI—Programming Interface Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) 09h 00h Bit 7:0 RO 8 bits Programming Interface — RO. 00h = No specific register level programming interface defined.
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PCI Express* Configuration Registers 13.1.10 PLT—Primary Latency Timer Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 0Dh 00h Bit 13.1.11 Latency Count. Reserved per the PCI Express* Base Specification. 2:0 Reserved HEADTYP—Header Type Register (PCI Express*—D28:F0/ F1/F2/F3/F4/F5/F6/F7) 0Eh 81h Bit 7 6:0 Multi-Function Device — RO. 0 = Single-function device. 1 = Multi-function device. Configuration Layout— RO.
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PCI Express* Configuration Registers 13.1.15 Bit Description 11:8 I/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support 32-bit I/ O addressing. 7:4 I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. 3:0 I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not support 32-bit I/ O addressing.
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PCI Express* Configuration Registers Bit 19:16 15:4 3:0 13.1.17 Description Reserved Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value of the range.
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PCI Express* Configuration Registers 13.1.20 CAPP—Capabilities List Pointer Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 34h 40h Attribute: Size: Bit 7:0 13.1.21 Description Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space.
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PCI Express* Configuration Registers Bit 13.1.23 Description 4 VGA 16-Bit Decode (V16) — R/W. 0 = VGA range is enabled. 1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled, and only the base I/O ranges can be decoded. 3 VGA Enable (VE)— R/W. 0 = The ranges below will not be claimed off the backbone by the root port.
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PCI Express* Configuration Registers 13.1.25 DCAP—Device Capabilities Register (PCI Express*— D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 44h–47h 00008000h Bit Reserved 27:26 Captured Slot Power Limit Scale (CSPS) — RO. Not supported. 25:18 Captured Slot Power Limit Value (CSPV) — RO. Not supported. 15 14:12 R/WO, RO 32 bits Description 31:28 17:16 Reserved Role Based Error Reporting (RBER) — RO.
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PCI Express* Configuration Registers Bit 13.1.27 Description 1 Non-Fatal Error Reporting Enable (NFE) — R/W. 0 = The root port will ignore non-fatal errors. 1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. 0 Correctable Error Reporting Enable (CEE) — R/W. 0 = The root port will ignore correctable errors.
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PCI Express* Configuration Registers 13.1.28 LCAP—Link Capabilities Register (PCI Express*—D28:F0/ F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 4Ch–4Fh See bit description Attribute: Size: R/WO, RO/V, RO 32 bits Bit Description 31:24 Port Number (PN) — RO/V. Indicates the port number for the root port.
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PCI Express* Configuration Registers Bit Description 11:10 Active State Power Management Support (APMS) — R/WO. Indicates what level of active state link power management is supported on the root port. Value 00b 9:4 Definition Reserved 01b L0s Entry Supported 10b Reserved 11b Both L0s and L1 Entry Supported Maximum Link Width (MLW) — RO/V. These bits are set by the PCIEPCS1[1:0] soft strap in the PCHSTRP9 record.
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PCI Express* Configuration Registers Bit Description 5 Retrain Link (RL) — R/W. 0 = This bit always returns 0 when read. 1 = The root port will train its downstream link. Note: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5/F6/F7:52, bit 11) to check the status of training. Note: It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register.
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PCI Express* Configuration Registers Bit 3:0 13.1.31 Description Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI Express* link. 0001b = Link is 2.5 Gb/s 0010b = Link is 5.0 Gb/s SLCAP—Slot Capabilities Register (PCI Express*—D28:F0/ F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: R/WO, RO 32 bits Bit Description Physical Slot Number (PSN) — R/WO. This is a value that is unique to the slot number.
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PCI Express* Configuration Registers Bit Description 3 Presence Detect Changed Enable (PDE) — R/W. 0 = Hot-Plug interrupts based on presence detect logic changes is disabled. 1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence detect logic changes state. 2:0 13.1.33 Reserved SLSTS—Slot Status Register (PCI Express*—D28:F0/F1/ F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 5Ah–5Bh 0000h Bit 15:9 8 13.1.
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PCI Express* Configuration Registers Bit 13.1.35 Description 1 System Error on Non-Fatal Error Enable (SNE) — R/W. 0 = An SERR# will not be generated. 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0~F7:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. 0 System Error on Correctable Error Enable (SCE) — R/W. 0 = An SERR# will not be generated. 1 = An SERR# will be generated, assuming CMD.
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PCI Express* Configuration Registers 13.1.37 DCTL2—Device Control 2 Register (PCI Express*—D28:F0/ F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 68h–69h 0000h Bit 15:11 10 9:5 Attribute: Size: RO, R/W 16 bits Description Reserved LTR Mechanism Enable (LTREN) — RW. A value of 1b enables support for the optional Latency Tolerance Reporting (LTR) mechanism. Reserved 4 Completion Timeout Disable (CTD) — R/W. When set to 1b, this bit disables the Completion Timeout mechanism.
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PCI Express* Configuration Registers Bit Description 12 Compliance De-Emphasis (CD) — R/W. This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Encodings: 0 = -6 dB 1 = -3.5 dB When the Link is operating at 2.5 GT/s, the setting of this bit has no effect. The default value of this bit is 0b. This bit is intended for debug, compliance testing purposes.
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PCI Express* Configuration Registers 13.1.39 LSTS2—Link Status 2 Register (PCI Express*—D28:F0/F1/ F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 72h–73h 0000h Bit 15:1 0 13.1.40 Description Current De-emphasis Level (CDL) — RO. When the Link is operating at 5 GT/s speed, this bit reflects the level of de-emphasis. Encodings: 0 = -6 dB 1 = -3.5 dB The value in this bit is undefined when the Link is operating at 2.5 GT/s speed.
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PCI Express* Configuration Registers 13.1.43 MD—Message Signaled Interrupt Message Data Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 88h–89h 0000h Bit 15:0 13.1.44 Description SVCAP—Subsystem Vendor Capability Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) 90h–91h A00Dh Bit 15:8 7:0 R/WO, RO 16 bits Next Capability (NEXT) — R/WO. Indicates the location of the next pointer in the list.
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PCI Express* Configuration Registers 13.1.47 PMC—PCI Power Management Capabilities Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: A2h–A3h C803h Attribute: Size: RO 16 bits Bit Description 15:11 PME_Support (PMES) — RO. Indicates PME# is supported for states D0, D3HOT and D3COLD. The root port does not generate PME#, but reporting that it does is necessary for some legacy operating systems to enable PME# in devices connected behind this root port.
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PCI Express* Configuration Registers 13.1.49 MPC2—Miscellaneous Port Configuration Register 2 (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: D4h–D7h 00000800h Bit 31:5 4 Attribute: Size: R/W, RO 32 bits Description Reserved ASPM Control Override Enable (ASPMCOEN) — R/W. 1 = Root port will use the values in the ASPM Control Override registers 0 = Root port will use the ASPM Registers in the Link Control register.
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PCI Express* Configuration Registers Bit Description 24 BME Receive Check Enable (BMERCE) — R/W. When set, the receive transaction layer will treat the TLP as an Unsupported Request error if a memory read or write request is received and the Bus Master Enable bit is not set. Messages, I/O, Config, and Completions are never checked for BME. 23 Reserved 22 Detect Override (FORCEDET) — R/W. 0 = Normal operation. Detected output from AFE is sampled for presence detection. 1 = Override mode.
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PCI Express* Configuration Registers 13.1.51 SMSCS—SMI/SCI Status Register (PCI Express*—D28:F0/ F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: Description Power Management SCI Status (PMCS) — R/WC. 1 = PME control logic needs to generate an interrupt, and this interrupt has been routed to generate an SCI. 30 Hot-Plug SCI Status (HPCS) — R/WC. 1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been routed to generate an SCI.
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PCI Express* Configuration Registers Bit 13.1.54 Description 1 Subtractive Decode Compatibility Device ID (SDCDID) — R/W. 0 = This function reports the device Device ID value assigned to the PCI Express Root Ports. 1 = This function reports a Device ID of 244Eh. If subtractive decode (SDE) is enabled, having this bit as '0' allows the function to present a Device ID that is recognized by the operating system. 0 Subtractive Decode Enable (SDE) — R/W.
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PCI Express* Configuration Registers Bit 20 Unsupported Request Error Mask (URE) — R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled. 1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is masked. 19 ECRC Error Mask (EE) — RO. ECRC is not supported. 18 Malformed TLP Mask (MT) — R/WO. 0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is enabled.
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PCI Express* Configuration Registers Bit 12 11:5 4 3:1 0 13.1.57 Description Poisoned TLP Severity (PT) — R/W. 0 = Error considered non-fatal. (Default) 1 = Error is fatal. Reserved Data Link Protocol Error Severity (DLPE) — R/W. 0 = Error considered non-fatal. 1 = Error is fatal. (Default) Reserved Training Error Severity (TE) — R/W. TE is not supported.
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PCI Express* Configuration Registers Bit 5:1 0 13.1.59 Description Reserved Receiver Error Mask (RE) — R/WO. Mask for receiver errors. AECC—Advanced Error Capabilities and Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 118h–11Bh 00000000h Bit 31:9 8 Description ECRC Check Enable (ECE) — RO. ECRC is not supported. ECRC Check Capable (ECC) — RO. ECRC is not supported. 6 ECRC Generation Enable (EGE) — RO. ECRC is not supported.
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PCI Express* Configuration Registers Bit 21 20:0 13.1.62 Description PECR2 Field 1 — R/W. BIOS must set this bit to 1b. Reserved PEETM—PCI Express* Extended Test Mode Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) Address Offset: Default Value: 324h–327h See Description Bit 31:5 4 RO 32 bits Description Reserved Lane Reversal (LR) — RO. This register reads the setting of the PCIELR1 soft strap for port 1 and the PCIELR2 soft strap for port 5. 0 = No Lane reversal (default).
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PCI Express* Configuration Registers 510 Intel® Xeon® Processor D-1500 Product Family Datasheet - Volume 1 of 4: Integrated Platform Controller Hub March 2015
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High Precision Event Timer Registers 14 High Precision Event Timer Registers The timer registers are memory-mapped in a non-indexed scheme. This allows the processor to directly access each register without having to use an index register. The timer register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation with IA64 processors. There are four possible memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h, 4) FED0_3000h.
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High Precision Event Timer Registers Table 14-1.
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High Precision Event Timer Registers Bit Description 1 Legacy Replacement Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, then the interrupts will be routed as follows: • Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC • Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC • Timer 2-n is routed as per the routing in the timer n config registers.
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High Precision Event Timer Registers 14.1.4 MAIN_CNT—Main Counter Value Register Address Offset: Default Value: 0F0h N/A Attribute: Size: R/W 64 bits . Bit 63:0 14.1.5 Description Counter Value (COUNTER_VAL[63:0]) — R/W. Reads return the current value of the counter. Writes load the new value to the counter. Notes: 1. Writes to this register should only be done while the counter is halted. 2. Reads to this register return the current value of the main counter. 3.
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High Precision Event Timer Registers Bit Description 13:9 Timer n Interrupt Rout (Tn_INT_ROUT_CNF) — R/W / RO. This 5-bit field indicates the routing for the interrupt to the 8259 or I/O (x) APIC. Software writes to this field to select which interrupt in the 8259 or I/O (x) will be used for this timer’s interrupt. If the value is not supported by this particular timer, then the value read back will not match what is written. The software must only write valid values.
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High Precision Event Timer Registers Bit Description 1 Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W. 0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is generated. If another interrupt occurs, another edge will be generated. 1 = The timer interrupt is level triggered. This means that a level-triggered interrupt is generated. The interrupt will be held active until it is cleared by writing to the bit in the General Interrupt Status Register.
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High Precision Event Timer Registers 14.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message Interrupt Rout Register Address Offset: Default Value: Note: Timer Timer Timer Timer Timer Timer Timer Timer N/A 0: 1: 2: 3: 4: 5: 6: 7: 110–117h, 130–137h, 150–157h, 170–177h, 190–197h, 1B0–1B7h, 1D0–1D7h, 1F0–1F7h, Attribute: R/W Size: 64 bit The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7.
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High Precision Event Timer Registers 518 Intel® Xeon® Processor D-1500 Product Family Datasheet - Volume 1 of 4: Integrated Platform Controller Hub March 2015
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Serial Peripheral Interface (SPI) 15 Serial Peripheral Interface (SPI) The Serial Peripheral Interface resides in memory mapped space. This function contains registers that allow for the setup and programming of devices that reside on the SPI interface. Note: All registers in this function (including memory-mapped registers) must be addressable in byte, word, and DWord quantities.
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Serial Peripheral Interface (SPI) Table 15-1. Serial Peripheral Interface (SPI) Register Address Map (SPI Memory Mapped Configuration Registers) (Sheet 2 of 2) 15.1.
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Serial Peripheral Interface (SPI) 15.1.2 HSFS—Hardware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 04h 0000h Bit Attribute: Size: RO, R/WC, R/W 16 bits Description 15 Flash Configuration Lock-Down (FLOCKDN) — R/W/L. When set to 1, those Flash Program Registers that are locked down by this FLOCKDN bit cannot be written.
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Serial Peripheral Interface (SPI) 15.1.3 HSFC—Hardware Sequencing Flash Control Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Note: SPIBAR + 06h 0000h Description 15 Flash SPI SMI# Enable (FSMIE) — R/W. When set to 1, the SPI asserts an SMI# request whenever the Flash Cycle Done bit is 1. 14 Reserved 13:8 Flash Data Byte Count (FdBC) — R/W. This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle.
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Serial Peripheral Interface (SPI) 15.1.5 FDATA0—Flash Data 0 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: 15.1.6 SPIBAR + 10h 00000000h Bit Description Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle. This register also shifts in the data from the Master-In Slave-Out pin into this register during the data portion of the SPI cycle.
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Serial Peripheral Interface (SPI) 15.1.8 Bit Description 23:16 BIOS Master Read Access Grant (BMRAG) — R/W. Each bit [28:16] corresponds to Master[7:0]. BIOS can grant one or more masters read access to the BIOS region 1 overriding the read permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved.
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Serial Peripheral Interface (SPI) 15.1.10 FREG2—Flash Region 2 (Intel® ME) Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Note: SPIBAR + 5Ch 00000000h Description 31:29 Reserved 28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG2.Region Limit. 15:13 Reserved 12:0 Region Base (RB) — RO.
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Serial Peripheral Interface (SPI) 15.1.13 PR0—Protected Range 0 Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Note: Description 31 Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared.
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Serial Peripheral Interface (SPI) Bit Description 31 Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit fields in this register are valid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardware. The base and limit fields are ignored when this bit is cleared. 30:29 28:16 15 14:13 12:0 15.1.16 Reserved Protected Range Limit — R/W.
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Serial Peripheral Interface (SPI) Bit 28:16 15 14:13 12:0 15.1.18 Description Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Read Protection Enable — R/W.
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Serial Peripheral Interface (SPI) Bit Description 18:16 15 SPI SMI# Enable (SME) — R/W. When set to 1, the SPI asserts an SMI# request whenever the Cycle Done Status bit is 1. 14 Data Cycle (DS) — R/W. When set to 1, there is data that corresponds to this transaction. When 0, no data is delivered for this cycle, and the dBC and data fields themselves are don’t cares. 13:8 7 15.1.20 SPI Cycle Frequency (SCF) — R/W.
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Serial Peripheral Interface (SPI) 15.1.21 OPTYPE—Opcode Type Configuration Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + 96h 0000h Attribute: Size: R/W 16 bits Entries in this register correspond to the entries in the Opcode Menu Configuration register. Note: The definition below only provides write protection for opcodes that have addresses associated with them.
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Serial Peripheral Interface (SPI) Bit 15:8 7:0 Description Allowable Opcode 1 — R/W. See the description for bits 7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use when initiating SPI commands through the Control Register. This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15) is set. 15.1.
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Serial Peripheral Interface (SPI) 15.1.25 FDOD—Flash Descriptor Observability Data Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: Note: SPIBAR + B4h 00000000h 31:0 Description Flash Descriptor Section Data (FDSD) — RO. Returns the DW of data to observe as selected in the Flash Descriptor Observability Control.
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Serial Peripheral Interface (SPI) 15.1.28 Bit Description 4 Write Enable on Write Status (LWEWS) — R/W. This register is locked by the Vendor Component Lock (LVCL) bit. 0 = No automatic write of 00h will be made to the SPI flash’s status register) 1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the Status register. Notes: 1.
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Serial Peripheral Interface (SPI) Bit Description 4 Write Enable on Write Status (UWEWS) — R/W. This register is locked by the Vendor Component Lock (UVCL) bit. 0 = No automatic write of 00h will be made to the SPI flash’s status register) 1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the Status register. Notes: 3 2 1:0 15.1.29 1.
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Serial Peripheral Interface (SPI) 15.1.30 SRDL—Soft Reset Data Lock Register (SPI Memory Mapped Configuration Registers) Memory Address: Default Value: SPIBAR + F0h 00000000h Bit 31:1 0 15.1.31 Description Set_Stap Lock (SSL) — R/WL. 0 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers are writeable. 1 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers are locked. Note: That this bit is reset to ‘0’ on CF9h resets.
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Serial Peripheral Interface (SPI) computer leaves the manufacturing floor. Intel® Xeon® Processor D-1500 Product Family Flash controller does not read this information. FFh is suggested to reduce programming time. 15.4 GbE SPI Flash Program Registers The GbE Flash registers are memory-mapped with a base address MBARB found in the GbE LAN register chapter Device 25: Function 0: Offset 14h. The individual registers are then accessible at MBARB + Offset as indicated in the following table.
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Serial Peripheral Interface (SPI) 15.4.1 GLFPR –Gigabit LAN Flash Primary Region Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 00h 00000000h Bit 31:29 RO 32 bits Description Reserved 28:16 GbE Flash Primary Region Limit (PRL)— RO. This specifies address bits 24:12 for the Primary Region Limit. The value in this register loaded from the contents in the Flash Descriptor.FLREG3.Region Limit 15:13 Reserved 12:0 15.4.
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Serial Peripheral Interface (SPI) 15.4.3 Bit Description 1 Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program register access is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or until hardware reset occurs due to a global reset or host partition reset in an Intel ME enabled system.
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Serial Peripheral Interface (SPI) 15.4.5 FDATA0—Flash Data 0 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: 15.4.6 MBARB + 10h 00000000h Attribute: Size: R/W 32 bits Bit Description 31:0 Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out Slave-In Data pin during the data portion of the SPI cycle.
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Serial Peripheral Interface (SPI) 15.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: MBARB + 54h 00000000h Bit Description Reserved 28:16 Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit. The value in this register is loaded from the contents in the Flash Descriptor.FLREG0.Region Limit. 12:0 Reserved Region Base (RB) — RO.
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Serial Peripheral Interface (SPI) Bit 12:0 15.4.11 Description Region Base (RB) — RO. This specifies address bits 24:12 for the Region 3 Base The value in this register is loaded from the contents in the Flash Descriptor.FLREG3.Region Base. PR0—Protected Range 0 Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Note: R/W 32 bits Bit Description 31 Write Protection Enable — R/W.
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Serial Peripheral Interface (SPI) 15.4.13 SSFS—Software Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) Memory Address: Default Value: Note: MBARB + 90h 00h 7:5 Description Reserved 4 Access Error Log (AEL) — RO. This bit reflects the value of the Hardware Sequencing Status AEL register. 3 Flash Cycle Error (FCERR) — R/WC.
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Serial Peripheral Interface (SPI) 15.4.15 Bit Description 3 Sequence Prefix Opcode Pointer (SPOP) — R/W. This field selects one of the two programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes register. By making this programmable, Intel® Xeon® Processor D-1500 Product Family supports flash devices that have different opcodes for enabling writes to the data space versus status register.
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Serial Peripheral Interface (SPI) Bit Description 5:4 Opcode Type 2 — R/W. See the description for bits 1:0 3:2 Opcode Type 1 — R/W. See the description for bits 1:0 1:0 Opcode Type 0 — R/W. This field specifies information about the corresponding Opcode 0. This information allows the hardware to 1) know whether to use the address field and 2) provide BIOS and Shared Flash protection capabilities.
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Thermal Sensor Registers (D31:F6) 16 Thermal Sensor Registers (D31:F6) 16.1 PCI Bus Configuration Registers Table 16-1. Thermal Sensor Register Address Map Offset 16.1.
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Thermal Sensor Registers (D31:F6) 16.1.2 DID—Device Identification Register Offset Address: Default Value: 02h–03h 3A32h Attribute: Size: Bit 15:0 16.1.3 Description Device ID (DID) — RO. Indicates the device number assigned by the SIG. CMD—Command Register Address Offset: Default Value: 04h–05h 0000h Attribute: Size: Bit 15:11 10 16.1.4 RO, R/W 16 bits Description Reserved Interrupt Disable (ID) — R/W. Enables the device to assert an INTx#. 0 = When cleared, the INTx# signal may be asserted.
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Thermal Sensor Registers (D31:F6) Bit Description 3 Interrupt Status (IS) — RO. Reflects the state of the INTx# signal at the input of the enable/ disable circuit. This bit is a 1 when the INTx# is asserted. This bit is a 0 after the interrupt is cleared (independent of the state of the Interrupt Disable bit in the command register). 2:0 16.1.5 Reserved RID—Revision Identification Register Address Offset: Default Value: 08h 00h Bit 7:0 16.1.6 Revision ID (RID) — RO.
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Thermal Sensor Registers (D31:F6) 16.1.10 LT—Latency Timer Register Address Offset: Default Value: 0Dh 00h Bit 7:0 16.1.11 RO 8 bits Description Latency Timer (LT) — RO. Does not apply to PCI Bus Target-only devices. HTYPE—Header Type Register Address Offset: Default Value: 0Eh 00h Bit 7 6:0 16.1.12 Attribute: Size: Attribute: Size: RO 8 bits Description Multi-Function Device (MFD) — RO.
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Thermal Sensor Registers (D31:F6) 16.1.14 SVID—Subsystem Vendor ID Register Address Offset: Default Value: 2Ch–2Dh 0000h Attribute: Size: R/WO 16 bits This register should be implemented for any function that could be instantiated more than once in a given system. The SVID register, in combination with the Subsystem ID register, enables the operating environment to distinguish one subsystem from the other(s). Software (BIOS) will write the value to this register.
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Thermal Sensor Registers (D31:F6) 16.1.18 INTPN—Interrupt Pin Register Address Offset: Default Value: 3Dh See description Bit 16.1.19 Attribute: Size: RO 8 bits Description 7:4 Reserved 3:0 Interrupt Pin — RO. This reflects the value of the Device 31 interrupt pin bits 27:24 (TTIP) in chipset configuration space.
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Thermal Sensor Registers (D31:F6) 16.1.22 PC—Power Management Capabilities Register Address Offset: Default Value: 52h–53h 0023h Bit 15:11 PME_Support — RO. Indicates PME# is not supported D2_Support — RO. The D2 state is not supported. 9 D1_Support — RO. The D1 state is not supported. Aux_Current — RO. PME# from D3COLD state is not supported, therefore this field is 000b. 5 Device Specific Initialization (DSI) — RO. Indicates that device-specific initialization is required.
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Thermal Sensor Registers (D31:F6) Table 16-2. Thermal Memory Mapped Configuration Register Address Map 16.2.
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Thermal Sensor Registers (D31:F6) 16.2.3 TSS—Thermal Sensor Status Register Offset Address: Default Value: TBARB+06h 00h Attribute: Size: RO, R/W 8 bit This register provides statuses of the thermal sensor. Bit 7:5 Reserved 4 Thermal Sensor Dynamic Shutdown Status (TSDSS) — RO. This bit indicates the status of the thermal sensor circuit when TSEL.ETS=1. 1 = thermal sensor is fully operational 0 = thermal sensor is in a dynamic shutdown state 3 GPE Status (GPES) — R/WC.
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Thermal Sensor Registers (D31:F6) 16.2.6 TSMIC—Thermal Sensor SMI Control Register Offset Address: Default Value: Attribute: Size: Description 7 Policy Lock-Down Bit — R/W. When written to 1, this bit prevents anymore writes to this register. 0 Reserved SMI Enable on Alert Thermal Sensor Trip — R/W. 1 = Enables SMI# assertions on alert thermal sensor events for either low-to-high or high-to-low events. Both edges are enabled by this one bit. 0 = Disables SMI# assertions for alert thermal events.
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Thermal Sensor Registers (D31:F6) Bit Description 29 TT Enable (TTEN) – R/W. When set the thermal throttling states are enabled. At reset, BIOS must set bits 28:0 and then do a separate write to set bit 29 to enable throttling. SW may set bit 31 at the same time it sets bit 29 if it wishes to lock the register. If SW wishes to change the values of 28:0, it must first clear the TTEN bit, then change the values in 28:0; and then re-enable TTEN. It is legal to set bits 31, 30 and 29 with the same write.
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Thermal Sensor Registers (D31:F6) Bit 16.2.14 Description 1 Alert High-to-Low Event (AHLE) — R/WC. 1 = Indicates that a Hot Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point. 0 = No trip for this event Software must write a 1 to clear this status bit. 0 Alert Low-to-High Event (ALHE) — R/WC. 1 = Indicates that an Aux Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17 Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.1 First Intel® Management Engine Interface (Intel® MEI) Configuration Registers (Intel® MEI 1 — D22:F0) 17.1.1 PCI Configuration Registers (Intel® MEI 1—D22:F0) / Table 17-1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Table 17-1. Intel® MEI 1 Configuration Registers Address Map (Intel® MEI 1—D22:F0) (Sheet 2 of 2) 17.1.1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.1.1.4 PCISTS—PCI Status Register (Intel® MEI 1—D22:F0) Address Offset: Default Value: 06h–07h 0010h Bit 15:5 Description Reserved Capabilities List (CL) — RO. Indicates the presence of a capabilities list, hardwired to 1. 3 Interrupt Status (IS) — RO. Indicates the interrupt status of the device. 0 = Interrupt is deasserted. 1 = Interrupt is asserted.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.1.1.9 SVID—Subsystem Vendor ID Register (Intel® MEI 1—D22:F0) Address Offset: Default Value: 17.1.1.10 15:0 Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Note: Register must be written as a Word write or as a DWord write with SID register.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 15:12 Error Code: If set to nonzero value the Intel® ME firmware has encountered a fatal error and stopped normal operation. 0 – No Error 1 – Uncategorized Failure – The Intel® ME firmware has experienced an uncategorized error. Further details of the failure can be found in the Extended Status Data. 2 – Disabled – Firmware was disabled on this platform. 3 – Image Failure - The Intel® ME firmware stored in the system flash is not valid.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 5:0 17.1.1.15 Description Intel ME UMA Size (MUSZ)—RO. This field reflect Intel Server Platform Services’ FW desired size of Intel ME UMA memory region. This field is set by Intel Server Platform Services FW prior to core power bring up allowing BIOS to initialize memory.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.1.1.16 H_GS—Host General Status Register (Intel® MEI 1—D22:F0) Address Offset: Default Value: 4Ch–4Fh 00000000h Bit 31:28 27:0 17.1.1.17 Command: Command code. Data: Command specific data. PID—PCI Power Management Capability ID Register (Intel® MEI 1— D22:F0) 50h–51h 8C01h Bit 15:8 7:0 Attribute: Size: RO 16 bits Description Next Capability (NEXT) — RO. Value of 8Ch indicates the location of the next pointer. Capability ID (CID) — RO.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit Description 3 No_Soft_Reset (NSR) — RO. This bit indicates that when the Intel MEI host controller is transitioning from D3hot to D0 due to a power state command, it does not perform an internal reset. Configuration context is preserved. 2 1:0 17.1.1.20 Reserved Power State (PS) — R/W. This field is used both to determine the current power state of the Intel MEI host controller and to set a new power state.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.1.1.25 H_GS3—Host General Status Register 3 (Intel® MEI 1—D22:F0) Address Offset: Default Value: 17.1.1.26 74h–77h 00000000h Description 31:0 Host General Status 3 (H_GS3)— R/W. General Status of Host, this field is not used by Hardware MID—Message Signaled Interrupt Identifiers Register (Intel® MEI 1— D22:F0) 8Ch-8Dh 0005h Bit 15:8 7:0 RO 16 bits Description Capability ID (CID) — RO. Capabilities ID indicates MSI.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.1.1.30 MD—Message Signaled Interrupt Message Data Register (Intel® MEI 1—D22:F0) Address Offset: Default Value: 98h–99h 0000h Bit 15:0 17.1.1.31 Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is enabled. Its content is driven during the data phase of the MSI memory write transaction.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.1.2 MEI0_MBAR—Intel® MEI 1 MMIO Registers These MMIO registers are accessible starting at the Intel MEI 1 MMIO Base Address (MEI0_MBAR) which gets programmed into D22:F0:Offset 10–17h. These registers are reset by PLTRST# unless otherwise noted. Table 17-2. Intel® MEI 1 MMIO Register Address Map 17.1.2.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 17.1.2.3 Description 1 Host Interrupt Status (H_IS) — R/WC. Hardware sets this bit to 1 when ME_IG bit is set to 1. Host clears this bit to 0 by writing a 1 to this bit position. H_IE has no effect on this bit. 0 Host Interrupt Enable (H_IE) — R/W. Host sets this bit to 1 to enable the host interrupt (INTR# or MSI) to be asserted when H_IS is set to 1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.2 Second Intel® Management Engine Interface (Intel® MEI 2) Configuration Registers (Intel® MEI 2—D22:F1) 17.2.1 PCI Configuration Registers (Intel® MEI 2—D22:F2) Table 17-3.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Table 17-3. Intel® MEI 2 Configuration Registers Address Map (Intel® MEI 2—D22:F1) (Sheet 2 of 2) Offset 17.2.1.1 Mnemonic A0h HIDM BC–BFh HERES C0–DFh HER[1:8] Register Name Intel MEI Interrupt Delivery Mode 15:0 RO Intel MEI Extended Register DW[1:8] 00000000h RO Attribute: Size: RO 16 bits Description Vendor ID (VID) — RO. This is a 16-bit value assigned to Intel.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 4 Capabilities List (CL) — RO. Indicates the presence of a capabilities list, hardwired to 1. 3 Interrupt Status — RO. Indicates the interrupt status of the device. 0 = Interrupt is deasserted. 1 = Interrupt is asserted. 2:0 17.2.1.5 Description Reserved RID—Revision Identification Register (Intel® MEI 2—D22:F1) Offset Address: Default Value: 08h See bit description Bit 7:0 17.2.1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.2.1.9 SVID—Subsystem Vendor ID Register (Intel® MEI 2—D22:F1) Address Offset: Default Value: 17.2.1.10 2Ch–2Dh 0000h Description 15:0 Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit Description 7:1 Cores Disabled: The number of physical processor cores that should be disabled on each processor socket. NOTE: These bits are valid only if bit 31 ‘NM Enabled’ is set. 0 17.2.1.14 BIOS Booting Mode: This bit is controlled by NM boot time policy. Two modes are supported: 0 – BIOS should run in power optimized mode.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.2.1.18 PMCS—PCI Power Management Control and Status Register (Intel® MEI 2—D22:F1) Address Offset: Default Value: 15 PME Status (PMES) — R/WC. Bit is set by Intel Server Platform Services FW. Host software clears bit by writing 1 to bit. This bit is reset when CL_RST# is asserted. 7:4 3 2 1:0 Reserved PME Enable (PMEE) — R/W. This bit is read/write and is under the control of host SW. It does not directly have an effect on PME events.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.2.1.21 MA—Message Signaled Interrupt Message Address Register (Intel® MEI 2—D22:F1) Address Offset: Default Value: 90h–93h 00000000h Bit 31:2 1:0 17.2.1.22 Address (ADDR) — R/W. Lower 32 bits of the system specified message address, always DW aligned. Reserved MUA—Message Signaled Interrupt Upper Address Register (Intel® MEI 2—D22:F1) 94h–97h 00000000h R/W 32 bits Description 31:0 Upper Address (UADDR) — R/W.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 3:0 17.2.1.26 Description Extend Register Algorithm (ERA)- RO. This field indicates the hash algorithm used in the FW measurement extend operations.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.2.2.2 H_CSR—Host Control Status Register (Intel® MEI 2 MMIO Register) Address Offset: Default Value: RO, R/W, R/WC 32 bits Description 31:24 Host Circular Buffer Depth (H_CBD) — RO. This field indicates the maximum number of 32 bit entries available in the host circular buffer (H_CB).
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 15:8 7:5 Description Intel ME CB Read Pointer Host Read Access (ME_CBRP_HRA). Host read only access to ME_CBRP. Reserved 4 Intel ME Reset Host Read Access (ME_RST_HRA). Host read access to ME_RST. 3 Intel ME Ready Host Read Access (ME_RDY_HRA). Host read access to ME_RDY. 2 Intel ME Interrupt Generate Host Read Access (ME_IG_HRA). Host read only access to ME_IG. 1 Intel ME Interrupt Status Host Read Access (ME_IS_HRA).
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Table 17-5. IDE Redirect Function IDER Register Address Map (Sheet 2 of 2) 17.3.1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 4 Capabilities List (CL)—RO. This bit indicates that there is a capabilities pointer implemented in the device. 3 Interrupt Status (IS)—RO. This bit reflects the state of the interrupt in the function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is a 1 and ID bit is 0 is the INTc interrupt asserted to the Host. 2:0 17.3.1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.1.9 PCTLBA—Primary Control Block Base Address Register (IDER— D22:F2) Address Offset: Default Value: 14–17h 00000001h Bit 31:16 15:2 17.3.1.10 Reserved Base Address (BAR)—R/W. Base Address of the BAR1 I/O space (4 consecutive I/O locations) 1 Reserved 0 Resource Type Indicator (RTE)—RO.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.1.13 SVID—Subsystem Vendor ID Register (IDER—D22:F2) Address Offset: Default Value: 17.3.1.14 15:0 Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor identifier. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This field can only be cleared by PLTRST#. Note: Register must be written as a DWord write with SID register.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.1.18 PC—PCI Power Management Capabilities Register (IDER—D22:F2) Address Offset: Default Value: CA–CBh 0023h Bit 15:11 10:9 8:6 5 Description PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the function may assert PME#. IDER can assert PME# from any D-state except D1 or D2 which are not supported by IDER. Reserved Aux_Current (AC) — RO.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.1.21 MC—Message Signaled Interrupt Message Control Register (IDER— D22:F2) Address Offset: Default Value: D2–D3h 0080h Bit 15:8 7 Description Reserved 64-Bit Address Capable (C64) — RO. Capable of generating 64-bit and 32-bit messages. Multiple Message Enable (MME) — R/W. These bits are R/W for software compatibility, but only one message is ever sent by the PT function. 3:1 Multiple Message Capable (MMC) — RO.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.2 IDER BAR0 Registers Table 17-6. IDER BAR0 Register Address Map Address Offset 17.3.2.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.2.2 IDEERD1—IDE Error Register DEV1 (IDER—D22:F2) Address Offset: Default Value: 01h 00h Attribute: Size: R/W 8 bits This register implements the Error register of the command block of the IDE function. This register is read only by the HOST interface when DEV = 1 (slave device). Bit 7:0 17.3.2.3 Description IDE Error Data (IDEED) — R/W. Drive reflects its error/ diagnostic code to the host using this register at different times.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.2.6 IDESCOR1—IDE Sector Count Out Register Device 1 Register (IDER— D22:F2) Address Offset: Default Value: 02h 00h Attribute: Size: R/W 8 bits This register is read by the HOST interface if DEV = 1. Intel Server Platform Services Firmware writes to this register at the end of a command of the selected device. When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this register is updated. 17.3.2.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) When the host writes to the IDE Sector Number In Register (IDESNIR), this register is updated with that value. Bit 7:0 17.3.2.10 Description IDE Sector Number Out DEV 1 (IDESNO1) — R/W. Sector Number Out register for Slave device. IDESNIR—IDE Sector Number In Register (IDER—D22:F2) Address Offset: Default Value: 03h 00h Attribute: Size: R/W 8 bits This register implements the Sector Number register of the command block of the IDE function.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.2.13 IDCLOR0—IDE Cylinder Low Out Register Device 0 Register (IDER— D22:F2) Address Offset: Default Value: 04h 00h Attribute: Size: R/W 8 bits This register is read by the Host if DEV = 0. Intel Server Platform Services Firmware writes to this register at the end of a command of the selected device. When the host writes to the IDE Cylinder Low In Register (IDECLIR), this register is updated with that value. 17.3.2.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.2.17 Bit Description 7:0 IDE Cylinder High Data (IDECHD) — R/W. Cylinder High data register for IDE command block. IDEDHIR—IDE Drive/Head In Register (IDER—D22:F2) Address Offset: Default Value: 06h 00h Attribute: Size: R/W 8 bits This register implements the Drive/Head register of the command block of the IDE. This register can be written only by the Host.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 7:0 17.3.2.20 Description IDE Drive Head Out DEV 0 (IDEDHO0) — R/W. Drive/Head Out register of Master device. IDESD0R—IDE Status Device 0 Register (IDER—D22:F2) Address Offset: Default Value: 07h 80h Attribute: Size: R/W 8 bits This register implements the status register of the Master device (DEV = 0). This register is read only by the Host. Host read of this register clears the Master device's interrupt.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.2.22 Bit Description 1 Index (IDX) — R/W. This bit is set once per rotation of the medium when the index mark passes under the read/write head. 0 Error (ERR) — R/W. When set, this bit indicates an error occurred in the process of executing the previous command.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.3.2 IDASR—IDE Alternate Status Register (IDER—D22:F2) Address Offset: Default Value: 2h 00h Attribute: Size: RO 8 bits This register implements the Alternate Status register of the Control block of the IDE function. This register is a mirror register to the status register in the command block.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.4.1 IDEPBMCR—IDE Primary Bus Master Command Register (IDER— D22:F2) Address Offset: Default Value: 00h 00h Attribute: Size: RO, R/W 8 bits This register implements the bus master command register of the primary channel. This register is programmed by the Host. Bit 7:4 3 2:1 0 17.3.4.2 Description Reserved Read Write Command (RWC) — R/W. This bit sets the direction of bus master transfer.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.4.4 IDEPBMDS1R—IDE Primary Bus Master Device Specific 1 Register (IDER—D22:F2) Address Offset: Default Value: 03h 00h Bit 7:0 17.3.4.5 Device Specific Data1 (DSD1) — R/W. Device Specific Data. IDEPBMDTPR0—IDE Primary Bus Master Descriptor Table Pointer Byte 0 Register (IDER—D22:F2) Attribute: Size: R/W 8 bits Description 7:0 Descriptor Table Pointer Byte 0 (DTPB0) — R/W.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.4.9 IDESBMCR—IDE Secondary Bus Master Command Register (IDER— D22:F2) Address Offset: Default Value: 08h 00h Bit 7:4 3 2:1 0 17.3.4.10 Reserved Read Write Command (RWC) — R/W. This bit sets the direction of bus master transfer. When 0, Reads are performed from system memory; when 1, writes are performed to System Memory. This bit should not be changed when the bus master function is active. Reserved Start/Stop Bus Master (SSBM) — R/W.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.3.4.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor Table Pointer Byte 0 Register (IDER—D22:F2) Address Offset: Default Value: 17.3.4.14 R/W 8 bits Description 7:0 Descriptor Table Pointer Byte 0 (DTPB0) — R/W. This register implements the Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the secondary channel. This register is read/write by the HOST interface.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.4 Serial Port for Remote Keyboard and Text (KT) Redirection (KT — D22:F3) 17.4.1 PCI Configuration Registers (KT — D22:F3) Table 17-9. Serial Port for Remote Keyboard and Text (KT) Redirection Register Address Map Address Offset 17.4.1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.4.1.3 CMD—Command Register (KT—D22:F3) Address Offset: Default Value: 04–05h 0000h Bit 15:11 17.4.1.4 Reserved 10 Interrupt Disable (ID)— R/W. This bit disables pin-based INTx# interrupts. This bit has no effect on MSI operation. 1 = Internal INTx# messages will not be generated. 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled. 9:3 Reserved 2 Bus Master Enable (BME)— R/W.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.4.1.7 CLS—Cache Line Size Register (KT—D22:F3) Address Offset: Default Value: 0Ch 00h Attribute: Size: RO 8 bits This register defines the system cache line size in DWORD increments. Mandatory for master which use the Memory-Write and Invalidate command. Bit 7:0 17.4.1.8 Description Cache Line Size (CLS)— RO. All writes to system memory are Memory Writes.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.4.1.12 CAP—Capabilities Pointer Register (KT—D22:F3) Address Offset: Default Value: 34h C8h Attribute: Size: RO 8 bits This optional register is used to point to a linked list of new capabilities implemented by the device. Bit 7:0 17.4.1.13 Description Capability Pointer (CP)— RO. This field indicates that the first capability pointer is offset C8h (the power management capability).
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.4.1.16 MID—Message Signaled Interrupt Capability ID Register (KT—D22:F3) Address Offset: Default Value: D0–D1h 0005h Attribute: Size: RO 16 bits Message Signaled Interrupt is a feature that allows the device/function to generate an interrupt to the host by performing a DWORD memory write to a system specified address with system specified data. This register is used to identify and configure an MSI capable device. Bit 15:8 7:0 17.4.1.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.4.1.20 MD—Message Signaled Interrupt Message Data Register (KT—D22:F3) Address Offset: Default Value: DC–DDh 0000h Attribute: Size: R/W 16 bits This 16-bit field is programmed by system software if MSI is enabled Bit 15:0 17.4.2 Description Data (DATA)— R/W. This MSI data is driven onto the lower word of the data bus of the MSI memory write transaction. KT IO/Memory Mapped Device Registers Table 17-10.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) THR: When host wants to transmit data in the non-FIFO mode, it writes to this register. In FIFO mode, writes by host to this address cause the data byte to be written by hardware to Intel ME memory (THR FIFO). Bit 7:0 17.4.2.3 Description Transmit Holding Register (THR)— WO. Implements the Transmit Data register of the Serial Interface. If the Host does a write, it writes to the Transmit Holding Register.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit 7:0 17.4.2.6 Description Divisor Latch MSB (DLM)— R/W. Implements the Divisor Latch MSB register of the Serial Interface. KTIIR—KT Interrupt Identification Register (KT—D22:F3) Address Offset: Default Value: 02h 00h Attribute: Size: RO 8 bits The KT IIR register prioritizes the interrupts from the function into 4 levels and records them in the IIR_STAT field of the register.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 17.4.2.8 KTLCR—KT Line Control Register (KT—D22:F3) Address Offset: Default Value: 03h 03h Attribute: Size: R/W 8 bits The line control register specifies the format of the asynchronous data communications exchange and sets the DLAB bit. Most bits in this register have no affect on hardware and are only used by the FW. Bit Description 7 Divisor Latch Address Bit (DLAB)— R/W.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) Bit Description 5 Transmit Holding Register Empty (THRE)— RO. This bit is always set when the mode (FIFO/ Non-FIFO) is changed by the Host. This bit is active only when the THR operation is enabled by the FW. This bit has acts differently in the different modes: Non FIFO: This bit is cleared by hardware when the Host writes to the THR registers and set by hardware when the FW reads the THR register.
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Intel® Management Engine Subsystem Registers (D22:F[3:0]) 608 Intel® Xeon® Processor D-1500 Product Family Datasheet - Volume 1 of 4: Integrated Platform Controller Hub March 2015