Intel® Core™2 Extreme Quad-Core Processor QX6800Δ Datasheet — on 65 nm Process in the 775-land LGA Package supporting Intel® 64 and Intel® Virtualization Technology± April 2007 Document Number: 316852-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Packaging Terminology ............................................................. 10 1.2 References .......................................................................................................
5.3 5.2.5 THERMTRIP# Signal ................................................................................78 Platform Environment Control Interface (PECI) ......................................................79 5.3.1 Introduction ...........................................................................................79 5.3.1.1 Key Difference with Legacy Diode-Based Thermal Management .......79 5.3.2 PECI Specifications .................................................................................
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VCC Static and Transient Tolerance ............................................................................. 20 VCC Overshoot Example Waveform ............................................................................. 21 Differential Clock Waveform ...................................................................................... 28 Differential Clock Crosspoint Specification ...................................................................
Intel® Core™2 Extreme Quad-Core Processor QX6800 Features • Available at 2.
Revision History Revision Number -001 Description • Initial release Date April 2007 §§ Datasheet 7
Datasheet
Introduction 1 Introduction The Intel® Core™2 Extreme quad-core processor QX6800 is a desktop quad core processor that combines the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, and gaming experiences. The Intel® Core™2 Extreme quad-core processor QX6800 is a 64bit processor that maintains compatibility with IA-32 software.
Introduction 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Intel® Core™2 Extreme quad-core processor QX6800 — Quad core processor in the FC-LGA6 package with a 2x4 MB L2 cache. • Processor — For this document, the term processor is the generic form of the Intel® Core™2 Extreme quad-core processor QX6800. The processor is a single package that contains one or more execution units.
Introduction this virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need for binary translation. Thus, it helps eliminate associated performance overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to common standards and to be more robust. See the Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture for more details. 1.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.3 Voltage Identification The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins (see Chapter 2.5.3 for VCC overshoot specifications). Refer to Table 12 for the DC specifications for these signals.
Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.9250 0 1 1 0 0 0 1.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.5 Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.5.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol VID Range Parameter VID Processor number VCC QX6800 2.93 GHz VCC_BOOT Default VCC voltage for initial power up VCCPLL PLL VCC Typ Max Unit 0.8500 — 1.5 V 3 Refer to Table 5 and Figure 1 V 4, 5, 6 — 1.10 — V - 5% 1.50 + 5% — — Processor number ICC ITCC VTT VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT QX6800 2.
Electrical Specifications Table 5. VCC Static and Transient Tolerance Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.38 mΩ Minimum Voltage 1.45 mΩ 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.045 10 -0.013 -0.033 -0.053 15 -0.020 -0.040 -0.060 20 -0.026 -0.047 -0.067 25 -0.033 -0.053 -0.074 30 -0.039 -0.060 -0.082 35 -0.046 -0.067 -0.089 40 -0.052 -0.074 -0.096 45 -0.059 -0.081 -0.103 50 -0.065 -0.088 -0.
Electrical Specifications Figure 1. VCC Static and Transient Tolerance Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 Vcc Maximum VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 Vcc [V] VID - 0.100 Vcc Typical VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 Vcc Minimum VID - 0.163 VID - 0.175 VID - 0.188 VID - 0.200 VID - 0.213 VID - 0.225 NOTES: 1.
Electrical Specifications Figure 2. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.5.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands.
Electrical Specifications 2.6.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[3:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. 4.
Electrical Specifications Table 10. GTL+ Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 GTLREF – 0.10 V 2, 3 GTLREF + 0.10 VTT + 0.10 V 3, 4, 5 Output High Voltage VTT – 0.10 VTT V 3, 5 IOL Output Low Current N/A VTT_MAX/ [(RTT_MIN)+(2*RON_MIN)] A - ILI Input Leakage Current N/A ± 200 µA 6 ILO Output Leakage Current N/A ± 200 µA 7 RON Buffer On Resistance 10 13 Ω VIH Input High Voltage VOH NOTES: 1.
Electrical Specifications Table 12. CMOS Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 3, 4, 5 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 3, 5, 6 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications Table 13. GTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF_PU GTLREF pull up on 975X and 96x chipset family boards 124 * 0.99 124 124 * 1.01 Ω 2 GTLREF_PD GTLREF pull down on 975X and 96x chipset family boards 210 * 0.99 210 210 * 1.01 Ω 2 GTLREF_PU GTLREF pull up on Bearlake chipset family boards 100 * 0.99 100 100 * 1.01 Ω 2 GTLREF_PD GTLREF pull down resistor on Bearlake chipset family boards 200 * 0.99 200 200 * 1.
Electrical Specifications Table 14. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency Core Frequency (266 MHz BCLK/ 1066 MHz FSB) Notes1, 2 1/6 1.60 GHz - 1/7 1.87 GHz - 1/8 2.13 GHz - 1/9 2.40 GHz - 1/10 2.66 GHz - 1/11 2.93 GHz - 1/12 3.20 GHz - NOTES: 1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necessarily committed production frequencies. 2.7.
Electrical Specifications 2.7.4 BCLK[1:0] Specifications Table 16. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 2 VL Input Low Voltage -0.30 N/A N/A V 3 VH Input High Voltage N/A N/A 1.15 V 3 2 V 3, 4 3,4, 5 VCROSS(abs) Absolute Crossing Point ΔVCROSS 0.300 N/A 0.550 Range of Crossing Points N/A N/A 0.140 V 3, 4 - VOS Overshoot N/A N/A 1.4 V 3 6 VUS Undershoot -0.
Electrical Specifications 2.8 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die.
Electrical Specifications 30 Datasheet
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 6.
Package Mechanical Specifications Figure 7.
Package Mechanical Specifications Figure 8.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 6 and Figure 7 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 10 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 10.
Package Mechanical Specifications 38 Datasheet
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 11 and Figure 12. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 11.
Land Listing and Signal Descriptions Figure 12.
Land Listing and Signal Descriptions Table 21. Land Name 42 Alphabetical Land Assignments Land Signal # Buffer Type Table 21.
Land Listing and Signal Descriptions Table 21. Land Name Datasheet Alphabetical Land Assignments Land Signal # Buffer Type Table 21.
Land Listing and Signal Descriptions Table 21. Land Name 44 Alphabetical Land Assignments Land Signal # Buffer Type Table 21.
Land Listing and Signal Descriptions Table 21. Land Name Datasheet Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 21.
Land Listing and Signal Descriptions Table 21. Land Name 46 Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 21.
Land Listing and Signal Descriptions Table 21.
Land Listing and Signal Descriptions Table 21. Land Name 48 Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 21.
Land Listing and Signal Descriptions Table 21. Land Name Datasheet Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 21.
Land Listing and Signal Descriptions Table 21. Land Name 50 Alphabetical Land Assignments Land Signal # Buffer Type Direction Table 21.
Land Listing and Signal Descriptions Table 21.
Land Listing and Signal Descriptions Table 22. 52 Numerical Land Assignment Table 22.
Land Listing and Signal Descriptions Table 22. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type C26 VTT C27 VTT C28 Table 22.
Land Listing and Signal Descriptions Table 22. 54 Numerical Land Assignment Land # Land Name Signal Buffer Type F23 RESERVED F24 TESTHI7 Power/Other F25 TESTHI2 Power/Other F26 TESTHI0 F27 Table 22.
Land Listing and Signal Descriptions Table 22. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type J18 VCC J19 VCC J20 Table 22.
Land Listing and Signal Descriptions Table 22. 56 Numerical Land Assignment Land # Land Name Signal Buffer Type P8 VCC P23 P24 Table 22.
Land Listing and Signal Descriptions Table 22. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type W26 VCC W27 VCC W28 Table 22.
Land Listing and Signal Descriptions Table 22. 58 Numerical Land Assignment Land # Land Name Signal Buffer Type AD30 VCC Power/Other Table 22.
Land Listing and Signal Descriptions Table 22. Land # Datasheet Numerical Land Assignment Land Name Signal Buffer Type Table 22.
Land Listing and Signal Descriptions Table 22. 60 Numerical Land Assignment Land # Land Name Signal Buffer Type AK18 VCC AK19 AK20 Table 22.
Land Listing and Signal Descriptions Table 22. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AN11 VCC AN12 VCC AN13 Table 22.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 23. Signal Description (Sheet 1 of 9) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 2 of 9) Name BPM[5:0]# BPMb[3:0]# Type Input/ Output Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# and BPMb[3:0]# should connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 4 of 9) Name DEFER# DRDY# Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 5 of 9) Name HIT# HITM# IERR# Type Input/ Output Input/ Output Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 6 of 9) Name Type Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. LOCK# Input/ Output PECI Input/ Output PECI is a proprietary one-wire bus interface. See Section 5.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 7 of 9) Name Type Description RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents. SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 8 of 9) Name Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 23. Signal Description (Sheet 9 of 9) Name Type Description Output This land is tied high on the processor package and is used by the VR to choose the proper VID table. Refer to the Voltage RegulatorDown (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information. VRDSEL Input This input should be left as a no connect in order for the processor to boot.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 24 instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2.
Thermal Specifications and Design Considerations Table 25. Datasheet Thermal Profile 130 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 37.9 34 42.32 68 46.74 102 51.16 2 38.16 36 42.58 70 47 104 51.42 4 38.42 38 42.84 72 47.26 106 51.68 6 38.68 40 43.1 74 47.52 108 51.94 8 38.94 42 43.36 76 47.78 110 52.2 10 39.2 44 43.62 78 48.04 112 52.46 12 39.46 46 43.88 80 48.
Thermal Specifications and Design Considerations Figure 13. Thermal Profile 130 W Processors 60.0 55.0 TC (°C) 50.0 Tc = 0.13*P + 37.9 45.0 40.0 35.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 24. This temperature specification is meant to help ensure proper operation of the processor. Figure 14 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Core™2 Extreme Quad-Core Processor QX6800 TMDG. Figure 14.
Thermal Specifications and Design Considerations under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# Time The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode.
Thermal Specifications and Design Considerations the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the OnDemand mode. 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature.
Thermal Specifications and Design Considerations 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps).
Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The PECI register resides at address 30h. Note that the address also supports two domains (Domain 0 and Domain 1). For more information on PECI domains, refer to the Platform Environment Control Interface (PECI) External Architecture Specification. 5.3.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 27. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 17.
Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
Features 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Stop Grant Snoop State and Extended HALT Snoop State. 6.2.4.
Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will Not be supplied with a cooling solution. For more information on designing a component level thermal solution, refer to the Intel® Core™2 Extreme Quad-Core Processor QX6800 TMDG.
Boxed Processor Specifications 86 Datasheet
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 88 Datasheet
