Datasheet

Register Description
34 Datasheet
Table 2-18. Device 6, Function 2: Integrated Memory Controller Channel 2
Rank Registers
DID VID 00h MC_RIR_WAY_CH2_0 80h
PCISTS PCICMD 04h MC_RIR_WAY_CH2_1 84h
CCR RID 08h MC_RIR_WAY_CH2_2 88h
HDR 0Ch MC_RIR_WAY_CH2_3 8Ch
10h MC_RIR_WAY_CH2_4 90h
14h MC_RIR_WAY_CH2_5 94h
18h MC_RIR_WAY_CH2_6 98h
1Ch MC_RIR_WAY_CH2_7 9Ch
20h MC_RIR_WAY_CH2_8 A0h
24h MC_RIR_WAY_CH2_9 A4h
28h MC_RIR_WAY_CH2_10 A8h
SID SVID 2Ch MC_RIR_WAY_CH2_11 ACh
30h MC_RIR_WAY_CH2_12 B0h
34h MC_RIR_WAY_CH2_13 B4h
38h MC_RIR_WAY_CH2_14 B8h
3Ch MC_RIR_WAY_CH2_15 BCh
MC_RIR_LIMIT_CH2_0 40h MC_RIR_WAY_CH2_16 C0h
MC_RIR_LIMIT_CH2_1 44h MC_RIR_WAY_CH2_17 C4h
MC_RIR_LIMIT_CH2_2 48h MC_RIR_WAY_CH2_18 C8h
MC_RIR_LIMIT_CH2_3 4Ch MC_RIR_WAY_CH2_19 CCh
MC_RIR_LIMIT_CH2_4 50h MC_RIR_WAY_CH2_20 D0h
MC_RIR_LIMIT_CH2_5 54h MC_RIR_WAY_CH2_21 D4h
MC_RIR_LIMIT_CH2_6 58h MC_RIR_WAY_CH2_22 D8h
MC_RIR_LIMIT_CH2_7 5Ch MC_RIR_WAY_CH2_23 DCh
60h MC_RIR_WAY_CH2_24 E0h
64h MC_RIR_WAY_CH2_25 E4h
68h MC_RIR_WAY_CH2_26 E8h
6Ch MC_RIR_WAY_CH2_27 ECh
70h MC_RIR_WAY_CH2_28 F0h
74h MC_RIR_WAY_CH2_29 F4h
78h MC_RIR_WAY_CH2_30 F8h
7Ch MC_RIR_WAY_CH2_31 FCh