Datasheet

4 Datasheet
2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1
TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3
TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5
TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7................................58
2.10 Integrated Memory Controller Channel Control Registers.........................................59
2.10.1 MC_CHANNEL_0_DIMM_RESET_CMD
MC_CHANNEL_1_DIMM_RESET_CMD
MC_CHANNEL_2_DIMM_RESET_CMD.......................................................59
2.10.2 MC_CHANNEL_0_DIMM_INIT_CMD
MC_CHANNEL_1_DIMM_INIT_CMD
MC_CHANNEL_2_DIMM_INIT_CMD..........................................................60
2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS
MC_CHANNEL_1_DIMM_INIT_PARAMS
MC_CHANNEL_2_DIMM_INIT_PARAMS.....................................................61
2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS
MC_CHANNEL_1_DIMM_INIT_STATUS
MC_CHANNEL_2_DIMM_INIT_STATUS .....................................................62
2.10.5 MC_CHANNEL_0_DDR3CMD
MC_CHANNEL_1_DDR3CMD
MC_CHANNEL_2_DDR3CMD....................................................................63
2.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT......................................64
2.10.7 MC_CHANNEL_0_MRS_VALUE_0_1
MC_CHANNEL_1_MRS_VALUE_0_1
MC_CHANNEL_2_MRS_VALUE_0_1..........................................................64
2.10.8 MC_CHANNEL_0_MRS_VALUE_2
MC_CHANNEL_1_MRS_VALUE_2
MC_CHANNEL_2_MRS_VALUE_2 .............................................................65
2.10.9 MC_CHANNEL_0_RANK_PRESENT
MC_CHANNEL_1_RANK_PRESENT
MC_CHANNEL_2_RANK_PRESENT............................................................65
2.10.10 MC_CHANNEL_0_RANK_TIMING_A
MC_CHANNEL_1_RANK_TIMING_A
MC_CHANNEL_2_RANK_TIMING_A ..........................................................66
2.10.11 MC_CHANNEL_0_RANK_TIMING_B
MC_CHANNEL_1_RANK_TIMING_B
MC_CHANNEL_2_RANK_TIMING_B ..........................................................69
2.10.12 MC_CHANNEL_0_BANK_TIMING
MC_CHANNEL_1_BANK_TIMING
MC_CHANNEL_2_BANK_TIMING..............................................................70
2.10.13 MC_CHANNEL_0_REFRESH_TIMING
MC_CHANNEL_1_REFRESH_TIMING
MC_CHANNEL_2_REFRESH_TIMING.........................................................70
2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING
MC_CHANNEL_2_CKE_TIMING................................................................71
2.10.15 MC_CHANNEL_0_ZQ_TIMING
MC_CHANNEL_1_ZQ_TIMING
MC_CHANNEL_2_ZQ_TIMING .................................................................71
2.10.16 MC_CHANNEL_0_RCOMP_PARAMS
MC_CHANNEL_1_RCOMP_PARAMS
MC_CHANNEL_2_RCOMP_PARAMS...........................................................72
2.10.17 MC_CHANNEL_0_ODT_PARAMS1
MC_CHANNEL_1_ODT_PARAMS1
MC_CHANNEL_2_ODT_PARAMS1.............................................................72
2.10.18 MC_CHANNEL_0_ODT_PARAMS2
MC_CHANNEL_1_ODT_PARAMS2
MC_CHANNEL_2_ODT_PARAMS2.............................................................73