In December 1973 Intel shipped the first 8-bit, N-channel microprocessor, the 8080. Since then it has become the most widely used microprocessor in the industry. Applications of the 8080 span from large, intelligent systems terminals to decompression computers for deep sea divers. This 8080 Microcomputer Systems User's Manual presents all of the 8080 system components. Over twenty-five devices are described in detail.
CONTENTS INTRODUCTION General . Advantages of Designing with Microcomputers . . Microcomputer Design Aids Application Example . . . . . . . . . . . . . . . . . . . Application Table .. . . . . . . . . . . . . . . . . . . . ii iii iii iv CHAPTER 1THE FUNCTIONS OF A COMPUTER A Typical Computer System The Architecture of a CPU Computer Operations. . . . . . . . . . . . . . . . . . . 1-1 1-1 1-3 CHAPTER 2THE 8080 CENTRAL PROCESSING UNIT General . . . . . . . . . . . . . . . . . . . . . . Architectu.
ROMs 8702A Erasable PROM (256 x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8708/8704 Erasable PROM (1 K x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8302 Mask ROM (256 x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8308 Mask ROM (1 K x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8316A Mask ROM (2K x 8) Data Sheet . . . . . . . . . . . . . . . . . . RAMs 8101-2 Static RAM (256 x 4) Data Sheet. . . . . . . . . . . . . . . . . . 8111-2 Static RAM (256 x 4) Data Sheet . . . . . . . . .
Since their inception, digital computers have continuously become more efficient, expanding into new applications with each major technological improvement. The advent of minicomputers enabled the inclusion of digital computers as a permanent part of various process control systems. Unfortunately, the size and cost of minicomputers in "dedicated" applications has limited their use. Another approach has been the use of custom built systems made up of "random logic" (i .e.
CONVENTIONAL SYSTEM Product definition System and logic design Debug Done with logic diagrams Done with conventional Lab Instrumentation PC card layout Documentation Cooling and packaging Power distribution Engineering changes PROGRAMMED LOGIC Simpl ified because of ease of incorporating features Can be programmed with design aids (compilers, assemblers, editors) Software and hardware aids reduce time Fewe r cards to layout Less hardware to document Reduced system size and power consumption eases job Les
APPLICATIONS EXAMPLE the control unit (as shown in Figure 0-1), the only "custom" logic will be that of the interface circuits. These circuits are usually quite simple, providing electrical buffering for the input and output signals. The 8080 can be used as the basis for a wide variety of calculation and control systems. The system configurations for particular applications will differ in the nature of the peripheral devices used and in the amount and the type of memory required.
APPLICATION PERIPHERAL DEVICES ENCOUNTERED Intelligent Terminals Cathode Ray Tube Display Printing Units Synchronous and Asynchronous data lines Cassette Tape Unit Keyboards Gaming Machines Keyboards, push buttons and switches Various display devices Coin acceptors Coin dispensers Cash Registers Keyboard or Input Switch Array Change Dispenser Digital Display Ticket Printer Magnetic Card reader Communication interface Accounting and Billing Machines Keyboard Printer Unit Cassette or other magnetic t
This chapter introduces certain basic computer concepts. It provides background information and definitions which will be useful in later chapters of this manual. Those already familiar with computers may skip this material, at their option. peripheral storage device, such as a floppy disk unit, or the output may constitute process control signals that direct the operations of another system, such as an automated assembly line. Like input ports, output ports are addressable.
cessor loads the address specified in the Call into its Program Counter. The next instruction fetched will therefore be the first step of the subroutine. registers eliminates the need to "shuffle" intermediate results back and forth between memory and the accumulator, thus improving processing speed and efficiency. The last instruction in any subroutine is a Return. Such an instruction need specify no address.
performs the arithmetic and logical operations on the binary data. Code or Operation Code. An eight-bit word used as an instruction code can distinguish between 256 alternative actions, more than adequate for most processors. The ALU must contain an Adder which is capable of combining the contents of two registers in accordance with the logic of binary arithmetic. This provision permits the processor to perform arithmetic manipulations on the data it obtains from memory and from its other inputs.
with a clearly defined activity is called a State. And the interval between pulses of the timing oscillator is referred to as a Clock Period. As a general rule, one or more clock periods are necessary for the completion of a state, and there are several states in a cycle. had time to respond, it frees the processor's READY line, and the instruction cycle proceeds.
from memory to output devices goes by way of the processor. having the device accomplish the transfer directly. The processor must temporarily suspend its operation during such a transfer, to prevent conflicts that would arise if processor and peripheral device attempted to access memory simultaneously. It is for this reason that a hold provision is included on some processors.
The 8080 is a complete 8-bit parallel, central processor unit (CPU) for use in general purpose digital computer systems. It is fabricated on a single LSI chip (see Figure 2-1). using Intel's n-channel silicon gate MaS process. The 8080 transfers data and internal state information via an 8-bit, bidirectional 3- state Data Bus (00-07). Memory and peripheral device addresses are transmitted over a separate 16- bit 3-state Address Bus (AO-A 15).
ARCHITECTURE OF THE 8080 CPU matically during every instruction fetch. The stack pointer maintains the address of the next available stack location in memory. The stack pointer can be initialized to use any portion of read-write memory as a stack. The stack pointer is decremented when data is "pushed" onto the stack and incremented when data is "popped" off the stack (Le., the stack grows "downward").
THE PROCESSOR CYCLE Arithmetic and Logic Unit (ALU): An instruction cycle is defined as the time required to fetch and execute an instruction. During the fetch, a selected instruction (one, two or three bytes) is extracted from memory and deposited in the CPU's instruction register. During the execution phase, the instruction is decoded and translated into specific processing activities.
be synchronized with the pulses of the driving clock. Thus, the duration of all states are integral multiples of the clock period. the contents of its Hand L registers. The eight-bit data word returned during this MEMORY READ machine cycle is placed in a temporary register inside the 8080 CPU. By now three more clock periods (states) have elapsed. In the seventh and final state, the contents of the temporary register are added to those of the accumulator.
While no one instruction cycle will consist of more then five machine cycles, the following ten different types of machine cycles may occur within an instruction cycle: (1 ) FETCH (M1) (2) MEMORY READ (3) MEMORYWRITE (4) STACK REAO (5) STACK WRITE (6) INPUT (7) OUTPUT (8) INTERRUPT (9) HALT (10) basic transition sequence. In the present discussion, we are concerned only with the basic sequence and with the READY function. The HOLD and INTERRUPT functions will be discussed later.
Instructions for the 8080 require from one to five machine cycles for complete execution. The 8080 sends out 8 bit of status informatton on the data bus at the beginning of each machine cycle (during SYNC time). The following table defines the status information. 8080 STATUS LATCH o o 0, o STATUS INFORMATION DEFINITION Data Bus Symbols Bit Definition INTA* 00 Acknowledge signal for INTERRUPT request. Signal should be used to gate a restart instruction onto the data bus when OBIN is active.
Till G)_RESET READY + HLTA (2) YES READY. HLTA NO ~~ READY -------------~ READY I... INT. INTE YES SET INTERNAL HOLD F/F SET INTERNAL HOLD F/F (3) I I I I (31 HOLD I HOLD I MODE I 7 I I ?~~---- I __ .J RESET INTERNAL HOLD F/F YES NO RESET HLTA NO HOLD NO RESET INTERNAL HOLD F/F SET INTERNAL INT F/F (1),NTE F/F IS RESET IF INTERNAL INT F/F IS SET. (2),NTERNAL INT F/F IS RESET IF INTE F/F IS RESET. (3)SEE PAGE 2-13. Figure 2-4.
The events that take place during the T3 state are determined by the kind of machine cycle in progress. In a FETCH machine cycle, the processor interprets the data on its data bus as an instruction. During a MEMORY READ or a STACK READ, data on this bus is interpreted as a data word. The processor outputs data on this bus during a MEMORY WRITE machine cycle. During I/O operations, the processor may either transmit or receive data, depending on whether an OUTPUT or an INPUT operation is involved.
411 _n~---frr\~----Ifn~~n~~n,-- . . . . .n-.--.......n,--~n~---.n~ . . . . .n~----4 ~ _.J\._J\.J\.J\.L.IlLi\.~~l.-.l:1cd:J. A15·0 ....._ ....... -~-- \UNKNOWN BYTE ONE ~.....- -..,.....- -...,~ - FLOATING \. SYNC WR , ~_~J I ~ . __ J ' - I L \ DBIN WAIT I INPUT DATA TO ACCUMULATOR ---..-.-+---............--....---, . , _J -W READY X BYTE TWO "1" "0" "1" STATUS INFORMATION NOTE: ® Refer to Status Word Chart on Page 2-6. Figure 2-6.
"data output delay" interval (tOO) following the 2 clock's leading edge. Data on the bus remains stable throughout the remainder of the machine cycle, until replaced by updated status information in the subsequent T 1 state. Observe that a READY signal is necessary for completion of an OUTPUT machine cycle. Unless such an indication is present, the processor enters the TW state, following the T2 state.
INTERRUPT SEQUENCES In this way, the pre-interrupt status of the program counter is preserved, so that data in the counter may be restored by the interrupted program after the interrupt request has been processed. The 8080 has the built-in capacity to handle external interrupt requests. A peripheral device can initiate an interrupt simply by driving the processor's interrupt (INT) line high.
Mn l--OR~ ¢l_n ¢2 n ~n i I : 1 I : I ! ! I I ~ \ ' i \ .- HOLD U ~ REQUEST OJ·O I I ~ n -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL ! A'5·0 n ~ Mn +1 1 (1) I I I -:- - - - - - - - - -:- - - - - - - - FLOATING I .1 -I----------I----------......--~ -..II I I 1 : i HOLD ..... 1 1 I ' i i READY HOLD F/F INTERNAL -+- +--_J --+- HLDA I (1) *T4 AND T5 OPERATION CAN BE DONE INTERNALLY. SEE ATTACHED ELECTRICAL CHARACTERISTICS. I I Figure 2-9.
HOLD SEQUENCES The SOSOA CPU contains provisions for Direct Memory Access (DMA) operations. By applying a HO LD to the appropriate control pin on the processor, an external device can cause the CPU to suspend its normal operations and relinquish control of the address and data busses. The processor responds to a request of this kind by floating its address to other devices sharing the busses. At the same time, the processor acknowledges the HO LD by placing a high on its HLDA outpin pin.
T, Tl TWH 91 92 PC A1S·0 ~--..-----~-- 07-0 ----- - SYNC OBIN WAIT STATUS INFORMATION NOTE: ® Refer to Status Word Chart on Page 2-6 Figure 2-11. HALT Timing TO STATE NO TW orT3 TO STATE Tl YES TO STATE Tl Figure 2-12. HALT Sequence Flow Chart. 2-14 ,...
Tn Tn+1 Tn+(i-1) Tn +3 Tn+2 Tn+i cP1 ~~~~t==p----~--·_-~--- A15.0~ _ _.1 (1) RESET ,--~~-----+-----""'----"'~-+---""" INTERNAL RESET SYNC DBIN -+- ..... ..... -+- -/~-----~---- ....- _ . . . . I -+-----.....-----.....----....-----/~-----~---- ....-----I---.....I (0 STATUS INFORMATION I I 11lWHEN RESET SIGNAL IS ACTIVE, ALL OF CONTROL OUTPUT SIGNALS WILL BE RESET IMMEDIATELY OR SOME CLOCK PERIODS LATER. THE RESET SIGNAL MUST BE ACTIVE FOR A MINIMUM OF THREE CLOCK CYCLES.
MNEMONIC M1[1] OP CODE M2 T3 T1 MOVr1,r2 o o 0 o S S MOVr,M o o 0 o o MOVM,r o o S S S (SSS)-TMP 001 (HL) SPHL 1 1 1 1 PC OUT STATUS PC == PC +1 (SSS)-TMP INST-TMP/IR X [3] ~ MVI r.
M3 PC OUT STATUS[6] PC = PC + 1 PC = PC + 1 PC = PC + 1 PC = PC + 1 M5 M4 [9] [9] [9] 2-17
MNEMONIC 07 0 6 0 5 0 4 ANI data 1 1 1 0 XAAr 1 0 1 0 0 1 0 XRAM XRI data 03 0 2 0 1 DO 0 1 1 PC OUT STATUS T2[2] T3 PC = PC + 1 INST-TMP/IA S S S (A)-ACT (SSS)-TMP (ACT)+(TPM)-A 1 0 (A)-ACT 1 0 (A)-ACT PC (ACT)+(TMP)-A 1 0 S S S (A)-ACT (SSS)-TMP 1 0 1 1 0 1 1 0 (A)-ACT 0 1 0 (A)-ACT 0 1 1 CMPM 1 0 1 1 CPI data 1 1 RLC 0 0 RRC 0 0 0 RAL 0 0 0 0 AAA 0 0 1 1 CMA 0 0 1 1 CMC 0 0 STC 0 0 JMP addr 1 1 0 0 0 0 0 0 0 J cond addr[17
M3 M5 M4 T1 (ACT)+(TMP)-A [9] [9 WZOUT STATUS[ll] (WZ) + 1-PC PC OUT STATUS[6] PC:: PC + 1 ~iA~~[ll,12] (WZ) + 1- PC PC OUT STATUS[6] PC:: PC + 1 ~iA~~~[11] (WZ) + 1-PC ~~~TUJS[6] PC:: PC + 1 ~iA~~~[11,12] (WZ) + 1-PC ~~2~JS[15] Sp:: SP + 1 ~A~~~[ll] (WZ) +l-PC SPOUT STATUS[15] Sp:: SP + 1 ~A~~1[11,12] (WZ) + 1- PC ~iA~~~[11] (WZ) + 1-PC SP OUT STATUS[15] SP :: SP + 1 SP OUT STATUS[15] SP :: SP + 1 SPOUT STATUS[15] WZOUT STATUS[18] 2-19
NOTES: 12. If the condition was met, the contents of the register pair WZ are output on the address lines (Ao-1S ) instead of the contents of the program counter (PC). 1. The first memory cycle (M 1) is always an instruction fetch; the first (or only) byte, containing the op code, is fetched during this cycle. 13. If the condition was not met, sub-cycles M4 and M5 are skipped; the processor instead proceeds immediately to the instruction fetch (Ml) of the next instruction cycle. 2.
This chapter will illustrate, in detail, how to interface the 8080 CPU with Memory and I/O. It will also show the benefits and tradeoffs encountered when using a variety of system architectures to achieve higher throughput, decreased component count or minimization of memory size. Control Bus A uni-directional set of signals that indicate the type of activity in current process. Type of activities: 1. 2. 3. 4. 5. 8080 Microcomputer system design lends itself to a simple, modular approach.
The following pages will cover the detailed design of the CPU Module with the 8080. The three Busses (Data, Address and Control) will be developed and the interconnection to Memory and I/O will be shown. the design and to achieve operational characteristics that are as close as possible to those of the 8224 and 8228.
OSCILLATOR ~ 20MHz 330 330 ~""""--01 >-......- - - - - - - - - - - -.......- - - - - - - -.... OSC 74S04 CLOCK GENERATOR 7486 DB OB 74163 DC OC . . . . . . . - - . . . - - - - - - - ' 7486 GND--+-~ 1 0 - - + - - - - - - - - -. . 4>2 (TTL) AUXILIARY FUNCTIONS r-----IIIIII---- SYNC 74HOO '----........--410 74S74 WAVEFORMS ----u 4>1 ---f 1~~~ 4>2 --' 50ns~ 4>1A SYNC t+- ---I u ~50ns \ --.
3. Auxiliary Timing Signals and Functions Bi-Directional Bus Driver and System Control Logic The Clock Generator can also be used to provide other signals that the designer can use to simplify large system timing or the interface to dynamic memories. The system Memory and I/O devices communicate with the CPU over the bi-directional Data Bus. The system Control Bus is used to gate data on and off the Data Bus within the proper timing sequences as dictated by the operation of the 8080 CPU.
The input level specification impl ies that any semiconductor memory or I/O device connected to the 8080 Data Bus must be able to provide a minimum of 3.3 volts in its high state. Most semiconductor memories and standard TTL I/O devices have an output capability of between 2.0 and 2.8 volts, obviously a direct connection onto the 8080 Data Bus would require pullup resistors, whose value should not affect the bus speed or stress the drive capability of the memory or I/O components. Status information.
INTERFACING THE 8080 CPU TO MEMORY AND I/O DEVICES This feature eliminates the need for extra equipment like tape readers and disks to load programs initially, an important aspect in small system design. The 8080 interfaces with standard semiconductor Memory components and I/O devices. In the previous text the proper control signals and buffering were developed which will produce a simple bus system similar to the basic system example shown at the beginning of this chapter.
The memories chosen for this example have an access time of 850 nS (max) to illustrate that slower, economical devices can be easily interfaced to the 8080 with little effect on performance. When the 8080 is operated from a clock generator with a tCY of 500 nS the required memory access time is Approx. 450-550 nS. See detailed timing specification Pg. 5-16. Using memory devices of this speed such as Intel@8308, 8102A, 8107A, etc.
I/O INTERFACE General Theory MEMR } __ As in any computer based system, the 8080 CPU must be able to communicate with devices or structures that exist outside its normal memory array. Devices like keyboards, paper tape, floppy disks, printers, displays and other control structures are used to 'input information into the 8080 CPU and display or store the results of the computational activity.
10--------...--r>-----.---+---- MEMR MEMW } TO MEMORY DEVICES SYSTEM CONTROL (8228) I/OR} NOT USED _ IIOW I/O R (MMJTO I/O DEVICES I/OW (MM) The second example uses Memory Mapped I/O and linear select to show how thirteen devices (8255) can be addressed without the use of extra decoders. The format shown could be the second and third bytes of the LDA or STA instructions or any other instructions used to manipulate I/O using the Memory Mapped technique.
The three 8212s can be used to drive long lines or LED indicators due to their high drive capability. (15mA) O-DATA 1-COMMAND C/DCONTROL _____________________ 8251SELECT (ACTIVE LOW) ________________________ 8212 #1 SE LECT (ACTIVE HIGH) _ _ _ _ _ _ _ _ _ _ _ 8212 #2 SELECT (ACTIVE HIGH) _ _ _ _ _ _ _ _ _ _ _ _ _ 8212 #3 SELECT (ACTIVE HIGH) Figure 3-13. 8251 Format. The two (2) 8255s provide twenty four bits each of programmable I/O da~a and control so that keyboards, sensors, paper tape, etc.
A computer, no matter how sophisticated, can only do what it is "told" to do. One "tells" the computer what to do via a series of coded instructions referred to as a Program. The realm of the programmer is referred to as Software, in contrast to the Hardware that comprises the actual computer equipment. A computer's software refers to all of the programs that have been written for that computer.
The 8080 can directly address up to 65,536 bytes of memory, which may consist of both read-only memory (ROM) elements and random-access memory (RAM) elements (read/ write memory). address where the data is located (the high-order bits of the address are in the first register of the pair, the low-order bits in the second).
Auxiliary Carry: If the instruction caused a carry out of bit 3 and into bit 4 of the resulting value, the auxiliary carry is set; otherwise it is reset. This flag is affected by single precision additions, subtractions, increments, decrements, comparisons, and logical operations, but is principally used with additions and increments preceding a DAA (Decimal Adjust Accumulator) instruction.
6. The last four lines contain incidental information about the execution of the instruction. The number of machine cycles and states required to execute the instruction are listed first. If the instruction has two possible execution times, as in a Conditional Jump·, both times will be listed, separated by a slash. Next, any significant data addressing modes' (see Page 4-2) are listed. The last line lists any of the five Flags that are affected by the execution of the instruction.
SHLD addr (Store Hand L direct) ((byte 3) (byte 2)) ~ (L) ((byte 3)(byte 2) + 1) ~ (H) The content of register L is moved to the memory Jocation whose address is specified in byte 2 and byte 3. The content of register H is moved to the succeeding memory location. LOA addr (Load Accumulator direct) (A) ~ ((byte 3) (byte 2)) The content of the memory location, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register A.
Arithmetic Group: ADC r (Add Register with carry) (A) ~ (A) + (r) + (CY) The content of register r and the content of the carry bit are added to the content of the accumulator. The result is placed in the accumulator. This group of instructions performs arithmetic operations on data in registers and memory. Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Carry, and Auxiliary Carry flags accord ing to the standard rules.
SUB M (Subtract memory) SBI data (Subtract immediate with borrow) (A) ~ (A) - (byte 2) - (CY) The contents of the second byte of the instruction and the contents of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator. (A) ~ (A) - ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is subtracted from the content of the accumulator. The result is placed in the accumulator.
OCR M (Decrement memory) OAA ((H) (L)) . . - ((H) (L)) - 1 The content of the memory location whose address is contained in the Hand L registers is decremented by one. Note: All condition flags except CY are affected. Cycles: States: Addressing: Flags: (Decimal Adjust Accumulator) The eight-bit number in the accumulator is adjusted to form two four-bit Binary-Coded-Decimal digits by the following process: 3 1.
ORA r (OR Register) (A) ~ (A) V (r) The content of register r is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. ANI data (AND immediate) (A) ~ (A) /\ (byte 2) The content of the second byte of the instruction is logicaJly anded with the contents of the accumu lator . The result is placed in the accumulator. The CY and AC flags are cleared.
CMP M (A) (Compare memory) RRC ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is subtracted from the accumulator. The accumulator remains unchanged. The condition flags are set as a result of the subtraction. The Z flag is set to 1 if (A) = ((H) (L)). The CY flag is set to 1 if (A) < ((H) (L)). (Rotate right) (An) ~ (A n -,); (A7) ~ (AO) (CY) ~ (AO) The content of the accumu lator is rotated right one position.
CMC (Complement carry) (CY)~ (CY) The CY flag is complemented. No other flags are affected. a , 0 dress is specified in byte 3 and byte 2 of the current instruction. 1 I 1 I 0 I I 0 0 I 0 I 1 I 1 low-order addr , high-order addr Cycles: States: Flags: STC 1 CY (Set carry) (CY) ~ 1 The CY flag is set to 1. No other flags are affected.
RST n (Restart) ((SP) - 1) ~ (PCH) ((SP) - 2) ~ (PCl) (SP) ~ (SP) - 2 (PC) ~ 8* (NNN) The high-order eight bits of the next instruction address are moved to the memory location whose address is one less than the content of register SP. The low-order eight bits of the next instruction address are moved to the memory location whose address is two less than the content of register SP. The content of register SP is decremented by two.
FLAG WORD Stack, I/O, and Machine Control Group: This group of instructions performs I/O, manipulates the Stack, and alters internal control flags. D1 Do Unless otherwise specified, condition flags are not affected by any instructions in this group. PUSH rp (Push) ((SP) - 1) ~ (rh) ((SP) - 2) ~ (rl) (SP) ~ (SP) - 2 The content of the high-order register of register pair rp is moved to the memory location whose address is one less than the content of register SP.
XTHL (Exchange stack top with Hand L) (L) (H) EI ~((SP)) ~ ((SP) + 1) The content of the L register is exchanged with the content of the memory location whose address is specified by the content of register SP. The content of the H register is exchanged with the content of the memory location whose address is one more than the content of register SP. 1 I 0 I SPHL 1 I I Cycles: States: Flags: 01 5 I 1 18 reg.
INSTRUCTION SET Summary of Processor Instructions Mnemonic Description try 06 MOV r1 ,r2 MOVM,r MOVr,M HlT MVI r MVIM INR r OCR r INR M OCR M ADOr AOCr SUB r SBB r Move register to register Move register to memory Move memory to register Halt Move immediate register Move immediate memory Increment register Decrement register Increment memory Decrement memory Add register to A Add register to A with carry Subtract register from A Subtract register from A with borrow And register with A Exclusive Or regi
CPU Group 8224 Clock Generator 8228 System Controller . . . . . . . . . . . . . . . . . . . . . . . 8080A Central Processor 8080A-1 Central Processor (1.3#ls) ••..•.••.••.••.• 8080A-2 Central Processor (1.5#ls) •...•..•..•.••.. MBOBOA Central Processor (_55° to +125°C) 5-1 5-7 5-13 5- 20 5-24 5-29 ROMs 8702A Erasable PROM (256 x 8) 8708/8704 Erasable PROM (1 K x 8302 Mask ROM (256 x 8) 8308 Mask ROM (1 K x 8) . . . . . 8316A Mask ROM (2K x 8) . . . . 5-37 5-45 5-51 5-59 5-61 .. . ... .. . . . . . . . .
CPU Group 8224 8228 8080A 8080A-1 8080A-2 M8080-A
Schottky Bipolar 8224 CLOCK GENERATOR AND DRIVER FOR 8080A CPU • Oscillator Output for External System Timing • C.rystal Controlled for Stable System Operation • Reduces System Package Count • Single Chip Clock Generator/Driver for 8080A CPU • Power-Up Reset for CPU • Ready Synchronizing Flip-Flop • Advanced Status Strobe The 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected by the designer, to meet a variety of system speed requirements.
SCHOTTKY BIPOLAR 8224 FUNCTIONAL DESCRIPTION The waveforms generated by the decode gating follow a simple 2-5-2 digital pattern. See Figure 2. The clocks generated; phase 1 and phase 2, can best be thought of as consisting of "units" based on the oscillator frequency. Assume that one "unit" equals the period of the oscillator frequency.
SCHOTTKY BIPOLAR 8224 STSTB (Status Strobe) The READY input to the 8080A CPU has certain timing specifications such as "set-up and hold" thus, an external synchronizing flip-flop is required. The 8224 has this feature built-in. The ROYI N input presents the asynchronous "wait request" to the "0" type flip-flop. By clocking the flip-flop with <1>20, a synchronized READY signal at the correct input level, can be connected directly to the a080A.
SCHOTTKY BIPOLAR 8224 D.C. Characteristics TA = O°C to 70°C; Vee = +5.0V ±5%; Voo = +12V ±5%. Symbol Parameter Min. Limits Typ. Max. Units Test Conditions IF Input Current Loading -.25 rnA VF = .45V IR Input Leakage Current 10 J.lA VR = 5.25V Ve Input Forward Clamp Voltage 1.0 V 'e = -5mA VIL Input"Low" Voltage .8 V Vee = 5.0V VIH Input "High" Voltage 2.6 2.0 V Reset Input All Other Inputs VIH-VIL REDIN Input Hysteresis .
SCHOTTKY BIPOLAR 8224 A.C. Characteristics vcc = +5.0V ± 5%; Voo = +12.0V ± 5%; TA = O°C to 70°C Symbol Limits Typ. Min. Parameter tq,1 cP1 Pulse Width 2tcy - - 20ns t2 cP2 Pulse Width 5tcy _ 35ns t01 cP1 to cP2 Delay 0 t02 cP2 to cP1 Delay 2tcy --14ns t03 cP1 to cP2 Delay tR cP1 and cP2 Rise Time cP1 and cP2 Fall Time cP2 to cP2 (TTL) Delay tF to2 Max.
SCHOTTKY BIPOLAR 8224 WAVEFORMS ~-------------tey---------------.I 1'4------t2fTTL) SYNC (FROM 8080A) ~--------toss-------.....----- t..-----tORH------.t RDYIN OR RESIN READY OUT RESET OUT VOLTAGE MEASUREMENT POINTS: cP1, cP2 Logic "0" = 1.0V, Logic "1" = 8.0V. All other signals measured at 1.5V. EXAMPLE: A.C. Characteristics (For tCY = 488.28 ns) TA = O°C to 70°C; Voo = +qV Symbol ±5%; Voo = +12V Parameter ±5%. Limits Typ. Min. Max.
Schottky Bipolar 8228 SYSTEM CONTROLLER AND BUS DRIVER FOR 8080A CPU • User Selected Single Leve,1 Interrupt Vector (RST 7) • 28 Pin Dual In-Line Package • Reduces System Package Count • Sing.le Chip System Control for MCS:SO Systems • Built-in Bi-Directional Bus Driver for Data Bus Isolation • Allows the use of Multiple Byte Instructions (e.g. CAL:L) for Interrupt Acknowledge The 8228 is a single chip system controller and bus driver for MCS-80.
SCHOTTKY BIPOLAR 8228 FUNCTIONAL DESCRIPTION Gating Array General The Gating Array generates control signals (MEM R, MEM W, I/O R, I/O Wand INTA) by gating the outputs of the Status Latch with signals from the 8080 CPU (DBIN, WR, and HLDA). The 8228 is a single chip System Controller and Data Bus driver for the 8080 Microcomputer System. It generates all control signals required to directly interface MCS-80™ family RAM, ROM, and I/O components.
SCHOTTKY BIPOLAR 8228 _ 18 WRn-------....., DBINt-=-1.:....7----..-----, HDLA ~2;.;.1~_--. 8080A CPU 3 °O~10~~-I 011-9--l~-I °2~8--l~~ ..... 0 3 1-7--l~-I DATA BUS 0 4 1-3--l~-I °51-4--l~-I 0 6 .-5--l~~-I _----- 0 7 .-6--l~~-I .... INTA MEMR MEM W CONTROL (FROM 8224) STATUSSTROBE--...c1II CONTROL BUS I/O R BUSEN _ _....
SCHOTTKY BIPOLAR 8228 WAVEFORMS STATUS STROBE 8080 DATA BUS -----...".I'~~+--,.,.I"-------------------- DBIN HLDA --------+----+-----'1 INTA, lOR, MEMR DURING HLDA SYSTEM BUS DURING READ 8080 BUS DURING READ· - - - - - - - - - lOW OR MEMW 8080 BUS DURING WRITE SYSTEM BUS DURING WRITE - - - - - - - - <~ - we1= SYSTEM BUS E N A B L E . SYSTEM BUS OUTPUTS - - - - - - - - - - - - - .
SCHOTTKY BIPOLAR 8228 D.C. Characteristics TA = O°c to 70°C; Vee = 5V ±5%. Symbol Limits Min. Typ.[1] Max. Parameter Ve Input Clamp Voltage, All Inputs IF Input Load Current, STSTB .75 02&06 Test Conditions -1.0 V Vee=4.75V; le=-5mA 500 IlA Vee=5.25V 750 IlA VF=O.45V IlA Do, 01, 04, Os, & 07 250 All Other Inputs 250 Il A 100 IlA Vee=5.25V OBo-OB7 20 IlA VR =5.25V All Other Inputs 100 p.A 2.0 V VCC=5V 190 mA VCC=5.
SCHOTTKY BIPOLAR 8228 · · 2 GND. Ao 20 +5V A1 11 -5V A2 28 +12V A3 A4 25 Ao 26 A1 27 A2 29 -- A 3 30 A4 31 As AS 8080A CPU · A7 HOLD INT. ENABLE ......- A 10 14 • INT 16 A 12 A 13 INTE A 14 A 1S WR r,; 1 D 14 13 TANK ----. OSC ~ cfJ2 (TTL) ~ RDYIN ~ RESIN -..0 +12V ----. DBIN TAl HDLA 22 10 15 24 ~ 8224 CLOCK GENERATOR DRIVER 4 23 1 12 cP1 cfJ 2 WAIT O2 REArJY 03 04 RESET 9 Os 16 06 +5V ----. GND ---.
intel® Silicon Gate MOS 8080 A SINGLE CHIP a-BIT N-CHANNEL MICROPROCESSOR The 8080A is functionally and electrically compatible with the Intel® 8080. • 2 J.
·SILICON GATE MOS 8080'A . 8080A FUNCTIONAL PIN DEFINITION The following describes the function of all of the 8080A I/O pins. Several of the descriptions refer to internal timing periods. _. . A 15. A O (oU1put three-state) ADDRESS BUS;.the address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao is the least significant address. bit.
SILICON GATE MOS 8080 A ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SILICON GATE MOS 8080A A.C. CHARACTERISTICS = O°C to 70°C, VOO = +12V ± 5%, VCC = +5V ± 5%, Vas = -5V ± 5%, Vss = OV, Unless Otherwise Noted TA Symbol Parameter Min. Max. Unit 0.48 2.0 J1sec 50 nsec Test Condition tCy[3] Clock Period t r , tf ·Clock Rise and Fall Time 0 ~1 f/J1 Pulse Width 60 nsec tq,2 cf>2 Pu.lse Width 220 nsec t01 Delayep1 to ep2 0 nsec .
SILICON GATE MOS 8080A A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, Voo = +12V ± 5%, Vee = +5V ± 5%, Vss = -5V'± 5%, V55 = OV, Unless Otherwise Noted Symbol Min. Parameter Max.
SILICON GATE MOS 8080 A INSTRUCTION SET The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate addressing modes. increment and decrement memory, the six general registers and the accumulator is provided as well as extended increment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by the abil ity to rotate the accu mu lator I~ft or right through or arou nd the carry bit.
SILICON GATE MOS 8080.A INSTRUCTION SET Summary of Processor Instructions Mnemonic Description D7 D6 MOV r1 .r2 MOVM,r MOVr,M .
infel® Silicon Gate MOS 8080A-1 SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR • TTL Drive Capability • 1.3 J.
SILICON GATE MOS 8080A-1 ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under 'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is'not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SILICON GATE MOS 8080A-1 A. c. CHARACTERISTICS TA CA UTlON: When operating the 8080A·l at or near full speed, care must be taken to assure precise timing compatibility between 8080A·', 8224 and 8228. = O°C to 70°C, Voo = +12V ± 5%, VCC = +5V ± 5%, VSS = -5V ± 5%, VSS = OV, Unless Otherwise Noted Symbol Parameter Min. Max. Unit .32 2.0 J.
SILICON GATE MOS 8080A-1 A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, Vo o = +12V ± 5%, Vee = +5V ± 5%, Vss Symbol = -5V ± 5%, V ss = OV, Unless Otherwise Noted Min. Parameter Max.
infel® Silicon Gate MOS 8080 A-2 SINGLE CHIP a-BIT N-CHANNEL MICROPROCESSOR • 1.5 J.
SILICON GATE MOS 8080A-2 ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SILICON GATE MOS 8080A-2 A.C. CHARACTERISTICS TA = O°C to 70°C, Vee = +12V ± 5%, VCC Symbol = +5V ± 5%, Vss = -5V ± 5%, Vss Parameter = OV, Unless Otherwise Noted Min. Max. Unit .38 2.
SILICON GATE MOS 8080A-2 A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, VOD = +12V ± 5%, Vee = +5V ± 5%, V BB = -5V ± 5%, Vss = OV, Unless Otherwise Noted Symbol Min. Parameter Max.
intel®.
SILICON GATE MOS M8080A INSTRUCTION SET The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate addressing modes. increment and decrement memory, the six general registers and the accumulator is provided as well as extended increment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by the ability to rotate the accumulator left or right through or arou nd the carry bit.
SILICON GATE MOS M8080A INSTRUCTION SET Summary of Processor Instructions Mnemonic Description 07 06 MOV r1 ,r2 MOV M,r MOVr,M HlT MVIr MVIM INR r OCR r INR M OCR M ADO r ADC r SUB r SBB r Move register to register Move register to memory Move memory to register Halt Move immediate register Move immediate memory Increment register Decrement register Increment memory Decrement memory Add register to A Add register to A with carry Subtract register from A Subtract register from A with borrow And register
SILICON GATE MOS M8080A M8080A FUNCTIONAL PIN DEFINITION The following describes the function of all of the M8080A I/O pi ns. Several of the descriptions refer to internal tim ing periods. 1 2 3 4 A15-AO (output' three~state) ADDRESS BUS; the address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao is the least significant address bit.
SILICON GATE MOS M8080A ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias -55°C to +125°C Storage T emperatu re .. . . . . . . . . . . . . . _65° C to + 150° C All Input or Output Voltages With Respect to VBB -0.3V to +20V Vcc, Voo and Vss With Respect to VBB -0.3V to +20V Power Dissipation . . . . . . . . . . . .. 1.7W *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
SILICON GATE MOS M8080A A.C. CHARACTERISTICS (Continued) TA = -55°C to +125°C, VOO = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted. Symbol Min. Parameter Max.
SILICON GATE MOS M8080A A.C. CHARACTERISTICS TA = -55°C to +125°C, Voo = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted. Symbol Parameter Min. Max. Unit 0.48 2.
ROMs 8702A 8704 8708 8302 8308 8316A
Silicon Gate MOS 8702A 2048 BIT ERASABLE AND ELECTRICALLY REPROGRAMMABLE READ ONLY MEMORY • Access Time -1.3 ~sec Max.
SILICON GATE MOS 8702A PIN CONNECTIONS The external lead connections to the 8702A differ, depending on whether the device is being programmed (1) or used in read. mode. (See following table.) 12 15 14 13 16 22 23 (Vee) (Vee) (Vee) (Program) (CS)· (VBB ) (VGG Read Vee Vee Vee VGG Vee Vee Programming GND Program Pulse GND GND Vee Pulsed VGG (V, L4P ) GND GND MODE .
SILICON GATE MOS 8702A A.C. CHARACTERISTICS TA = 00 C to +70°C, Vcc = +5V ±5%, Voo = -9V ±5%, VGG MINIMUM TEST SYMBOL = -9V ±5% unless otherwise noted TYPICAL MAXIMUM UNIT 1 Freq. Repetition Rate tOH Previous read data val id 100 ns tAcc t ovGG Address to output delay 1.3 p.s 400 JlS ns Clocked VGG set up Chip select delay t es [2] MHz 1.0 teo Output delay from CS 900 ns too Output deselect 400 ns tOHC Data out hold in clocked VGG mode (Note 1) 5 JlS Note 1.
SILICON GATE MOS 8702A TYPICAL CHARACTERISTICS OUTPUT CURRENT VS. VDO SUPPLY VOLTAGE '00 CURRENT VS. TEMPERATURE 39 38 37 36 1 35 33 ~ 32 o _0 v oo = -9V r\ \ '\ f'\ I" ~ 31 29 I '" ~ z I Vaa:l -9V II ~ -- .P ~ ~ -~ ! _. I - -5 ~ .~ -6 -3 ~ 80 100 120 AMBIENT TEMPERATURE (OCI VOH '" O.OV => TA -3.
SILICON GATE MOS 8702A PROGRAMMING OPERATION D.C.
SILICON GATE MOS 8702A SWITCHING CHARACTERISTICS FOR PROGRAMMING OPERATION PROGRAM OPERATION Conditions of Test: Input pulse rise and fall times :s 1J1sec CS = OV PROGRAM WAVEFORMS ---.l tACH r-I I I tACW----.
SILICON GATE MOS 8702A PROGRAMMING INSTRUCTIONS FOR THE 8702A I. Operation of the 8702A in Program Mode II. Programming of the 8702A Using Intel ® Microcomputers Initially, all 2048 bits of the ROM are in the "0" state (output low). Information is introduced by se\ectively programming "1 "s (output high) in the proper bit locations. Intel provides low cost program development systems which may be used to program its electrically programmable ROMs.
· :,
Silicon Gate MOS 8708/8704 8192/4096 BIT ERASABLE AND ELECTRICALLY REPROGRAM MABLE READ ONLY MEMORY • 8708 1024x8 Organization • 8704 512x8 Organization • Fast Programming Typ. 100 sec.
SILICON GATE MOS 8708/8704 Absolute Maximum Ratings~· Temperature Under Bias Storage Temperature ,. -25°C to +85°C -~5°C to +125°C All Input or Ou'tput Voltages with Respect to VBB (except Program) . . . . . . . . . . . . . . . . . . . . . Program Input to VBB . . . . . . . . . . . . . . . . . . . . Supply Voltages Vcc and Vss with Respect to VBB. Vo o with Respect to VBB . . . . . . . . . . . . . . . . . Power Dissipation ... . .... .. . . . . . . . . . . . . . . . . . . . . .. .. .. .. ...
SILICON GATE MOS 8708/8704 A.C. Characteristics TA =O°C to 70°C, Vee = +SV ±S%, Vo o = +12V ±S%, Vee = -SV ±S%, Vss = OV, Unless Otherwise Noted. Symbol Min. Parameter tAce Address to Output Delay teo Chip Select to Output Delay tOF Chip De-Select to Output Float 0 tOH Address to Output Hold 0 Capacitance£1] Symbol Typ. Max. Unit 280 4S0 ns 120 ns 120 ns ns TA = 2SoC, f = 1MHz Parameter Typ. Max.
SILICON GATE MOS 8708/8704 PROGRAMMING OPERATION Description Initially, and after each erasure, all bits of the 8708/8704 are in the "1" state (Output High). Information is introduced by selectively programming "0" into the desired bit locations. The circuit is set up for programming operation by raising the CS/WE input (Pin 20) to +12V. The word address is selected in the same manner as in the read mode. Data to be programmed are presented, 8-bits in parallel, to the data output lines (01-08).
SILICON GATE MOS 8708/8704 Waveforms (Logic levels and timing reference levels same as in the Read Mode unless noted otherwise.) A) Program Mode CS/WE = +12V . . . - - - - - - - - - - - - - - - O N E PROGRAM LOOP ---------------.! I ~ ADDRESS 0 ADDRESS __ AD_D_R_ESS_1_....c ~_--·-·-·----.
SILICON GATE MOS 8708/8704 Typical Characteristics (Nominal supply voltages unless otherwise noted): RANGE OF SUPPLY CURRENTS VS. TEMPERATURE OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE 10 80 r-----...----or----...----..,---,~ .----..----,....---~--~--, ALL POSSIBLE OPERATING CONDITIONS: Vee = 5.25V Voo = 12.6V Vee = 4.75V 81----+----t----t--~1t--~---::l~ 6 Vaa 60 =O°C TA =25°C TA =70°C ~~---#----+_'_~-+-----i TA = -5.25V =i .§ ...2 Cf.) w a:: a:: 40 ;:) 0 > ..
Silicon Gate MOS 8302 2048 BIT MASK PROGRAMMABLE READ ONLY MEMORY • Static MOS - No Clocks Required • Simple Memory Expansion - Chip Select Input Lead • 24-Pin Dual-In-Line Hermetically Sealed Ceramic Package • Access Time-1 p'sec Max. • Fully Decoded, 256 x 8 Organization • Inputs and Outputs TTL Compatible • Three-State Output Capability OR-Tie The Intel@8302 is a fully decoded 256 word by 8 bit metal mask ROM. It is ideal for large volume production runs of microcomputer systems initial.
SILICON GATE MOS 8302 Absolute Maximum Ratings ~~ o Ambient Temperature Under Bias oOc to +70 C Storage Temperature -65°C to +125 0 C Soldering Temperature of Leads (10 sec) . . . . . . .. +300 oC Power Dissipation 2 Watts Input Voltages and Supply Voltages with respect to Vcc +O.5V to -20V *COMMENT Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage to the device.
SILICON GATE MOS 8302 A.C. Characteristics TA = (1J C to +70°C, Vee = +5V ±5%, Voo SYMBOL MINIMUM TYPICAL MAXIMUM UNIT 1 Repetition Rate tOH Previous read data val id tACC t ovGG t cs Address to output delay Clocked VGG set up Ch ip select delay tco Output delay from CS too t OHC Output deselect .700 MHz 100 ns 1 JJ.s 1 JJ.s ns 200 500 300 ns ns 5 Data out hold in clocked VGG mode (Note 1) JJ.s The output will remain valid for tOHC as long as clocked VGG is at Vce.
SILICON GATE MOS 8302 Typical Characteristics ACCESS TIME VS. LOAD CAPACITANCE 100 CURRENT VS. TEMPERATURE 39 38 37 36 35 i 34 zau 33 ~ II: II: 32 u 31 0 _0 30 \ 900 I \ vee = +5V ~ \ "I" '\ j 29 l' '- 700 - v GG = -9V \ 800 - v oo = -9V ~ INPUTS:: Vee ! I ~ I 4( t----+---+-1 TTL LOAD t-- CJ 300 V cc = +5V = -9V I---- en 200 VGG :: -9V 250C TA ::I 100 o I 40 20 t----+---+-- ~ e I-- o 20 10 30 40 50 60 80 70 .
Silicon Gate MOS 8308 8192 BIT STATIC MOS READ ONLY MEMORY Organization --1024 Words x 8 Bits • Fast Access - 450 ns • Directly Compatible with 8080 CPU at Maximl)m Processor Speed • Three State Output - OR-Ti~ Capability • Two Chip Select Inputs for Easy Memory Expansion • Standard Power Supplies +12V DC, ±5V DC • ·Fully Decoded • Directly TTL Compatible - All Inputs and Outputs The Intel® 8308 is an 8,192 bit static MOS mask prog~ammable Read Only Memory organized as 1024 words by ~-bi~s.
SILICON GATE MOS 8308 Absolute Maximum Ratings* Ambient Temperature Under Bias Storage Temperature Voltage On Any Pin With Respect To Vaa . . . . . . . . . . . . . . . . . Power Dissipation *COMMENT -25°C to +85°C -65°·C to-i-150°C Stresses above those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
SILICON GATE - MOS 8308 - A.C. Characteristics TA = oo.c to'+70~C, VCC = +5V ±5%; VO_D = +12V ±5%, VBB = -5V _±5%, VSS_= OV, Unless Otherwise Specif.i~d. Limits[2] Symbol Parameter Min. Typ. Max. Unit tACC Address to Output Delay Time 200- 450 ns tC01 Chip Select 1 to Output Dela.y~ime 85 160 ns teo 2 Chip Select 2 to O~tput Delay Time 125 220 Chip Deselect to Output Data float Ti~_e_ tOF conditions~of Test for A.C. Characteristics. VOH = 3.7V @ IOH = -1mA, CL = 100pF.
SILICON GATE MOS 8308 Typical Characteristics (Nominal supply voltages unless .otherwise noted.) A OUTPUT CAPACITANCE VS. A OUTPUT DELAY 100 VS. TE""PERATURE (NORMALIZED) 1.4 1.2 +40 r-----~--_r__--~---, _ +20 t----+-----+----~<------f u W 1.1 1.0 (I) ..5- ~ .9 ~ ~ .J ~ ~ .8 0 t---:---+-------:::._--""'"'"f-- t- "- ~ .7 ::J ~ t- ::J ~ o <1 -20 ~--+_--_+__----+---__t ~ .6 ::::;~ -40 10 20 30 40 50 60 70 80 90 L . . -_ _...I..-_ _...Io....-_ _.......I.
MCS™ CUSTOM ROM ORDER FORM 8308 ROM CUSTOMER P.O. NUMBER _ . _ OATE _ For Intel use only S# _ STO PPpp--------_ zz, _ 00 APp _ _ OATE . _ All custom 8308 ROM orders must be submitted on this form. Programming information should be sent in the form of computer punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel.
MCS™ CUSTOM ROM ORPER _FOR.M_ 8308 a. Title Card '1 NO. OF OUTPUTS 4 or 8 TITLE CARD DESIGNATION CUSTOMER'S DIVISION OR CUSTOMER'S COMPANY NAME I ' ~"/~ G.:"-'·i-i·iNl('·~ I II II I III LOCATION INTEL CUSTOMER:S ~ i ,-:~AI?~ ::.,.o#1'i:: CORP I I III ~ PIN h?14:' \.
intel® Silicon Gate MOS ROM 8316A 16,384 BIT STATIC MOS READ ONLY MEMORY Organization-2048 Words x 8 Bits Access Time-SSO ns max -- • Single + 5 Volts Power Supply Voltage • Directly TTL Compatible - All Inputs and Outputs • Low Power Dissipation of 31.4 /LW/Bit Maximum • Three Programmable Chip Select Inputs for Easy Memory Expansion .
SI~ICON GATE MOS ROM 8316A ABSOLUTE MAXIMUM RATINGS· Ambient Temperature Under Bias O°C to 70°C -65°C to +150°C Storage Temperature Voltage On Any Pin With Respect To Ground. . . . . . . . . . . . . . . . . . . . .. -0.5V to +7V Power Dissipation ~ . . 1.0 Watt *COMMENT: Stresses above those Iisted under"Absolute Maximum Ratings" may cause permanent damage to the device.
SILICON GATE MOS ROM 831.6A WAVEFORMS ADDRESS tOF PROGRAMMABLE CHIP SELECTS OU~TVALID 5-63 1111.
S.ILICO.N GATE MOS ROM 8316A TYPICAL D.C. CHARACTERISTICS ACCESS TIME VS. AMBIENT TEMPERATURE V,N LIMITS VS. TEMPERATURE 900 . - - - - - - , . . - - - , - - - - - - . - - - - - - - . 800 1.8 r----,r----r--.,r---r---.,r---r--_ r----;----t----:::::;~--t---__I TYPICAL 1.6 t - - - - 1 t - - - - - t - - - - 1 t - - - t - - - I - - - - f - - - - - - f 600 ....-~--+----t-----+---~ en t-l ~ 1.4 t - - - t - - - - - - t - - t - - - t - - - t - - - t - - - - f z -> 400 r-----:=--...
MCS™ CUSTOM ROM ORDER FORM 8316A ROM CUSTOMER,-----------------P.O. NUMBER ----.;. _ OATE _ For Intel use only S# ----:. STO _ pppp-------- zz, _ 00 APp _ _ OATE _ All custom 8316A ROM orders must be submitted on this form. Programming information should be sent in the form of computer punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel.
a. Title Card 4 or 8 DESIGNATION 1 1I NO. OF OUTPUTS TITLE CARD CUSTOMER'S INTEL PIN DIVISION OR LOCATION CUSTOMER'S PIN ,----....1..-------,,1 r--L-, ~ CUSTOMER'S I COM~ANY NAME I ' DECIMAL NUMBER INDICATING THE TRUTH TABLE NUMBER r--;,~·'I·~l.~I:.~·LL[!":':_~.~·r"!:-,""·~.;~'~l~r.·)~·~CO~~R~P--:.--!;:'~,"~:i':!":,ri~~~l;L""':'t4":":"ll.~. "':'C~:\L""':!I~.~....:-~l2~J~4:;.\-.l-...:.:.(h~~·.
RAMs 8101-2 8111-2 8102-2 8102A-4 81078-4 5101 8210 8222
Silicon Gate MOS 8101-2 1024 BIT (256 x 4) STATIC MOS RAM WITH SEPARATE 1/0 • 256 x 4 Organization to Meet Needs for Small System Memories • Access Time - 850 nsec Max.
SILICON GATE MOS 8101-2 Absolute Maximum Ratings* *COMMENT: Stresses above those listed under ''Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias. . . . ..
SILICON GATE MOS 8101-2 A.C. Characteristics READ CYCLE TA = o°c to 70°C, Vee ±5~/~, unless otherwise specified. = 5V =I~ tRey Read Cycle tA Access Time ----- Chip Enable To Output too Output Disable To Output tOF [1] Data Output to High Z State - - _ . _ - _ .. _---._-----. -'----- -- Max. Test Conditions Unit ~--_._--- ns .- --.-- r _ _ _ _ ._.__u. ___________ teo I Previous Data Read Valid tOH Typ. Min. Parameter Symbol after change of Address ---_.
Silicon Gate MOS 8111-2 1024 BIT (256 x 4) STATIC MOS RAM WITH COMMON I/O AND OUTPUT DISABLE • • • • • Organization 256 Words by 4 Bits Access Time - 850 nsec Max.
SILICON GATE MOS 8111-2 Absolute Maximum Ratings* *COMMENT: Stresses above those listed under ''Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias. . . . ..
SILICON GATE MOS 8111-2 A.C. Characteristics READ CYCLE TA = o°c to 70°C, Vee = 5V ±5%, unless otherwise specified. Symbol Parameter tRCY tA tco too tOF [1] Read Cycle Access Time Chip Enable To Output Output Disable To Output Data Output to High Z State tOH Previous Data Read Valid after change of Add ress Typ. Min. Max.
Silicon Gate MOS 8102-2 1024 BIT FULLY DECODED STATIC MOS RANDOM ACCESS MEMORY • Simple Memory Expansion Enable Input • Access Time - 850ns Max.
SILICON GATE MOS 8102-2 ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any oth~r condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SILICON GATE MOS 8102-2 A.C. CHARACTERISTICS TA = ooe to 70 oe, Vee = 5V ±5% unless otherwise specified LIMITS --·---r----mT---_.~~_~ ..._... l}YP._... _~?<~. _._ PARAMETER SYMBOL UNIT ..L READ CYCLE ~~~~~~~---~--------~-_ tA .. -._- "--r .-_._.- --"---'- 85o-·-···T - - tR-e------r-R--EA~D-C-Y--C-L-E--·--------_ . - - - - - - - - _-----~--~-- -_._----~.
SILICON GATE MOS 8102·2 TYPICAL D.C. CHARACTERISTICS INPUT CURRENT VS. INPUT VOLTAGE +5 EFFECTIVE INPUT CHARACTERISTIC Vee~ 5.0V OUTPUT SINK CURRENT VS. bUTPUT VOLTAGE Vee I 5.0V g +2.5 r TYPICAL -5 -7.5 -1 ~~~b~.J ( VIH MIN. VIL MAX. +1 +2 +3 +5 +4 +6 VIN (VOLTS) RELATIONSHIP BETWEEN OUTPUT SINK CURRENT, NUMBER OF OR-TIES, AND OUTPUT VOLTAGE +5 4.3 vcclg AMBIENT TEMPERATURE oac -+--+-~_---+-_-I 4.75~ 3.9 25°C 70°C TYPICAL 3.5 ct ! ct .g -10 t-----.
Silicon Gate MOS 8102A-4 1024 BIT FULLY DECODED STATIC MOS RANDOM ACCESS MEMORY • Simple Memory Expansion Enable Input • Access Time -450 ns Max.
SILICON GATE MOS 8102A-4 ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SILICON GATE MOS 8102A-4 A. C. Characteristics TA = O°C to 70°C, Vee = 5V ±5% unless otherwise specified Limits Parameter Symbol TypJ1 ] Min. Max.
SILICON GATE MOS 8102A-4 Typical D. C. and A. C. Characteristics POWER SUPPLY CURRENT VS. SUPPLY VOLTAGE POWER SUPPLY CURRENT VS. AMBIENT TEMPERATURE 45 35 I I 40 30 VeeMAX.- ct ............ 30 25 r---___ -.............. TYPICAL ~ ! - ........ /r / 10 o 10 20 30 40 50 60 5 70 I 1 T (OC) A Vee (VOLTS) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE 30 -30 -25 -20 ct ! ~PICAL / 20 15 20 15 V .
Silicon Gate MOS 81078·4 FULLY DECODED RANDOM ACCESS 4096 BIT DYNAMIC MEMORY * Access Time·· 270 ns max. * Read, Write Cycle Times--470 ns max. * Refresh Period -- 2 ms • Low Cost Per Bit • Low Standby Power • Easy System Interface • Only One High Voltage Input Signal- Chip Enable • TTL Compatible -- All Address, Data, Write Enable, Chip Select Inputs • Read-Modify-Write Cycle Time _.
SILICON GATE MOS 81078·4 Absolute Maximum Ratings* ooc to 70°C Temperature Under Bias Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +150 0 C All I nput or Output Voltages with Respect to the most Negative Supply Voltage, Vee . . . . . . . . . . . . . . . . .. +25V to -O.3V Supply Voltages Vee, Vcc, and Vss with Respect to Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SILICON GATE MOS 81078·4 Read and Refresh Cycle [1) (Numbers in parentheses are for minimum cycle timing in ns) ~-------------- t Cy (470) ----------------------~ ADDRESS AND~ ADDRESS CAN CHANGE 0 \'IL 1 4 - - - - - - - - - - - tce (300) tAC(O)-.......-~ V,HC ----------~ ----+-----+-I..-oI!""!!-----------------------.. . CE \'JH - -...--~-+------------------------_t-;-.....,r_----.,...-- t cO (2S0) OoUT ..... VoL - - IMP~6~NCE V_A_L_ID_-_-_-:.::=~~~:~~~:~ 1-_....iI... -II.
SILICON GATE MOS 81078·4 A. C. Characteristics TA = oOc to 0 70 C, Voo = 12V ± 5%, VCC = 5V ± 10%, Va a READ, WRITE, AND READ MODIFY/WRITE CYCLE vss Symbol Parameter Min. Max. Unit 2 ms tREF Time Between Refresh tAC Address to CE Set Up Time 0 ns tAH Address Hold Time 100 ns tcc CE Off Time 130 tT CE Transition Time 10 tCF CE Off to Output High Impedance-State 0 = = -5V ± 5%, OV, unless otherwise noted.
SILICON GATE MOS 81078·4 Typical Characteristics Fig. 1. 100 AV VS. TEMPERATURE Fig. 2. TYPICAL 100 AVERAGE VS. CYCLE TIME 2.0 . - - - - - - - . - - - - - - - . . . - - - - - - , 1.751--------4------+-----; 39 1-----4---+-.....-....::IIlr-+-----I1-- > ~ 1.51----------+----- -+-----_1 TA ! 0 w > 1.25
SILICON GATE MOS 81078·4 Read Modify Write Cycle£1] Symbol t RWC Parameter Min. Read Modify Write( RMW) Max. 590 Unit ns Conditions tT = 20ns Cycle Time t CRW CE Width During RMW 420 3000 ns WE to CE on 0 ns WE to CE off 150 ns twp WE Pulse Width 50 ns tow DIN to WE Set Up 0 ns t DIN Hold Time 0 ns WC t w OH tco CE to Output Delay 250 ns t Access Time 270 ns ACC C load Ref = 50pF, Load = One TTL Gate, = 2.
SILICON GATE MOS 81078·4 Typical Current Transients Ys. Time ~ CE 100 200 300 400 500 0 100 200 300 400 500 I I I I I I I I I I I WRITE CYCLE \ READ CYCLE \ J 30 20 Ice (rnA) 10 0 A J V V 2.0 1.5 NORMALIZED 100 --f-....AP---....~~----IDo2 1.0 TYPICAL 0.5 a 20 Iss (rnA) 10 0 -10 Applications Refresh The 81078-4 is refreshed by either a read cycle, write cycle, or read-modify write cycle. Only the selected row of niemory array is refreshed.
SILICON GATE MOS 81078·4 Typical System Below is an example of a 16K x 8 bit memory circuit. Device decoding is done with the CE input. All devices are unselected during refresh with CS input. The 8210, 8205 and 8212 are standard Intel products. REFRESH 0----+0- 8228 CS {MEMW 8080 1~~ MEMR------------- Do .-------t'\/~-----.....I 07 I/.~-----------------~ -----~A~-----........
intel Silicon Gate CMOS 5101, 5101-3, 5101L, 5101L·3 e 1024 BIT (256 x 4) STATIC CMOS RAM *Ultra Low Standby Current: 15 nA/Bit for the 5101 • Directly TTL Compatible - All Inputs and Outputs • Three-State Output • Fast Access Time - 650 ns • Single +5 V Power Supply • CE 2 Controls Unconditional Standby Mode The Intel® 5101 and 5101-3 are ultra-low power 1024 bit (256 words x 4-bits) static RAMs fabricated with an advanced ionimplanted silicon gate CMOS technology.
SILICON GATE CMOS 5101,5101-3, 5101L, 5101L-3 Absolute Maximum Ratings * *COMMENT: Stresses above those listed under 'Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias. .
SILICON GATE CMOS 5101,5101-3, 5101L, 5101L-3 A.C. Characteristics for 5101, 5101· 3, 5101 L, 5101 L- 3 READ CYCLE T A = o°c to 70°C, Vcc Symbol = 5V ±5%, unless otherwise specified. Parameter Min. Typ. Max.
SILICON GATE CMOS 5101,5101-3, 5101L, 5101L-3 Waveforms WRITE CYCLE READ CYCLE ..-- _ 1 . . - - - - - - - t we ------~ ADDRESS ADDRESS 14----- CE2 CE2 00 00 ~I----- t CW2 (COMMON I/O) (3] t ew1 - - -... ------.t (COMMON I/O) (4) DATA DATA OUT IN DATA IN STABLE 1..---- tDw---~ --. tAW 104----t wP ----.I RIW NOTES: 1. 2. 3. 4. Typical values are for TA = 25° C and nominal supply voltage. This parameter is periodically sampled and is not 100% tested.
Schottky Bipolar 8210 TTL-TO-MOS LEVEL SHIFTER AND HIGH VOLTAGE CLOCK DRIVER • • • • • Operates from Standard Bipolar and MOS Power Supplies Four Low Voltage Drivers One High Voltage Driver TTL and OTl Compatible Inputs Outputs Compatible with 8107A MOS Memories • Maximum MOS Device Protection Output Clamp Diodes The Intel®821 0 is a Bipolar-to-MOS level shifter and high voltage driver which accepts TTL and DTL inputs.
SCHOTTKY BIPOLAR 8210 A.C. Characteristics Symbol TA = O°C to 70°C, VCC = 5.0V ± 5%, VDD = 12V ± 5% Parameter Min. Typ. Max. Unit tLd+ Delay Plus Rise Time for Low Voltage Drivers 5 13 20 ns tLd- Delay Plus Fall Time for Low Voltage Drivers 5 13 20 ns tHd+ Delay Plus Rise Time for High Voltage Driver 10 30 40 ns tHd- Delay Plus Fall Time for High Voltage Driver 10 30 40 ns A.C. CONDITIONS OF TEST *This parameter is periodically sampled and is not 100% tested.
SCHOTTKY BIPOLAR 8210 Absolute Maximum Ratings* Temperature Under Bias Storage Temperature Supply Voltage, Vee Supply Voltage, Voo All Input Voltages -1.0 to +5.5V Outputs for Low Voltage Drivers . . . . . . .. -0.5 to +7V -1.0 to +13V Outputs for Clock Driver Power Dissipation at 25°C 2W o°c to 70°C -65°C to +150°C -0.5 to +7V -0.5 to +13V *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This.
SCHOTTKY BIPOLAR 8210 Typical System Below is an example of a 16K x 8 bit memory circuit. Device decoding is done with the CE input. All devices are unselected during refresh with CS i~put. The 8210, 8205 and 8212 are standard Intel products. REFRESH 0-----+--1 cs 8228 {MEMW MEMR - - - - - 4__- - - - - ~ 8080 f~~ Do 0 7 . - - - - - - - i " J " I - - - - - -........ I/'...-----------------~ -------t/',J-------J'\.
Schottky Bipolar 8222 DYNAMIC MEMORY REFRESH CONTROLLER • Adjustable Refresh Request Oscillator • Internal Address Multiplexer • Ideal for 8107A, 81078 4K RAM Refresh • Up to 6 Ro . (64x 64,t}' '\ff The 8222 is a refresh controller for dynamic RAMs requiring row ref.JJj"\:;; W inR,~"addresses (or 4K bits for 64 x 64 organization). The device contains an accurate refresh timer (w~~)t::,~rL, ," '" n be,,-set by an external resistor and ca,:~\~'r',;":::--:, 0,<,:,,,:-,:<':). ,.
I/O 8212 8255 8251
Schottky Bipolar 8212 EIGHT-BIT INPUT/OUTPUT PORT • 3.65V Output High Voltage for Direct Interface to 8080 CPU or 8008 CPU • Asynchronous Register Clear • Replaces Buffers, Latches and Multiplexers in Microcomputer Systems • Reduces System Package Count • Fully Parallel 8-Bit Data Register and Buffer • Service Request Flip-Flop for Interrupt Generation • Low Input Load Current .25 mA Max. • Three State Outputs • Outputs Sink 1.
SCHOTTKY BIPOLAR 8212 Functional Description Data Latch The 8 flip-flops that make up the data latch are of a "0" type design. The output (Q) of the flip-flop will follow th~ data input (0) while the clock input (C) is high. Latching will occur when the clock (C) returns low. The data latch is cleared by an asynchronous reset input (CLR). (Note: Clock (C) Overides Reset (CLR).) Output Buffer The outputs of the data latch (Q) are connected to 3-state, non-inverting output buffers.
SCHOTTKY BIPOLAR 8212 Applications Of The 8212 -- For Microcomputer Systems I II III IV V VI Basic Schematic Symbol Gated Buffer Bi-Directional Bus Driver Interrupting Input Port Interrupt Instruction Port Output Port VII VIII IX 8080 Status Latch 8008 System 8080 System: 8 Input Ports 8 Output Ports 8 Level Priority Interrupt I.
SCHOTTKY BIPOLAR 8212 III. Bi-Directional Bus Driver BI-DIRECTIONAL BUS DRIVER A pair of 8212's wired (back-to-back) can be used as a symmetrical drive, bi-directional bus driver. The devices are controlled by the data bus input control which is connected to D81 on the first 8212 and to D82 on the second. One device is active, and acting as a straight through buffer the other is in 3-state mode. This is a very useful circuit in small system design.
SCHOTTKY BIPOLAR 8212 VI. Output Port (With Hand-Shaking) OUTPUT PORT (WITH HAND-SHAKING) The 8212 can be used to transmit data from the data bus to a system output. The output strobe could be a hand-shaking signal such as "reception of data" from the device that the system is outputting to. It in turn, can interrupt the system signifying the reception of data. The selection of the port comes from the device selection logic.
SCHOTTKY BIPOLAR 8212 VIII. 8008 System This shows the 8212 used in an 8008 microcomputer system. They are used to multiplex the data from three different sources onto the 8008 input data bus. The three sources of data are: memory data, input data, and the interrupt instruction. The 8212 is also used as the uni-directional bus driver to provide a proper drive to the address latches (both low order and high order are also 8212's) and to provide adequate drive to the output data bus.
SCHOTTKY BIPOLAR 8212 . IX. 8080 System This drawing shows the 8212 used in the I/O section of an 8080 microcomputer system. The system consists of 8 input ports, 8 output ports, 8 level priority systems, and a bidirectional bus driver. (The data bus within the system is darkened for emphasis). Basically, the operation would be as follows: The 8 ports, for example, could be connected to 8 keyboards, each keyboard having its own priority level.
SCHOTTKY BIPOLAR 8212 (See Note 1) AO - ' A 1 --+8080 ADDRESS .:... BUS A 2 --+- 8205 ST;~;T:¢ ST:212 t :7: :~ l l ltn ~ ::=:- ~ ~ E1 ~ --0 E2 ::Vee- ..E_3_ _.. ~ ;:N~~- I/O DEVICE SELECTOR :IIII[ INP - -......----t-t-t-t-t-+--+-t------------+-6 8212 _~L~ee? => ~:~~T STROBE 2 ---. STB INPUT ~ PORT 2 L-Y STATUS BITS - 8212 8212 ~ OUTPUT PORT 2 W ~ CLR _ INT OUT ----t------r-t-t-t-t----ir+-t-----------+--+----1~:::::f_4 r- D:J:~!I.
SCHOTTKY BIPOLAR 8212 Absolute Maximum Ratings· Temperature Under Bias Plastic .. -65°C to + 75°C Storage Temperature -65°C to +160°C All Output or Supply Voltages - 0.5 to + 7 Volts ,All Input Voltages -1.0 to 5.5 Volts Output Currents *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
SCHOTTKY BIPOLAR 8212 Typical Characteristics INPUT CURRENT YS. INPUT YOLTAGE o r Vee Vee (;" ....z TA =o°c""'" '/ w -150 « E = 25°C V : / TA =75°C V / TA I- zw I- I:::J ~ 60 a: a: :::J u u a. =+5.0V 801-----1----1----+--------4 I « -100 ..=: ~ 100 ....----.,...----.,...----~--____. ~~~ =+5.0V -50 :::J OUTPUT CURRENT VS. OUTPUT "LOW" YOLTAGE :;) ....a. :;) -200 40 0 20 -250 -300 -3 -2 o -1 +1 +2 O'---~~'-----'-----.L..------' o +3 .
SCHOTTKY BIPOLAR 8212 Timing Diagram 1.5Vy----------y.5V DATA _____ -J. I;==t pw 1.5vl STB or oSl • oS2 ~twE=J ~I_ tH :.j'---- ' -1._5V _ -/'10-:------- OUTPUT 1.5Vj oSl. OS2 ________l_tE_~ r ~E~~~W_) _ X OUTPUT \1.5V __ ~-t-D-~---- ~----,~t- I~tpw~I 1.5V\. eLR .5fV 11.5V ~~~~~~~~~~~~1r----- ><"-:._5V DO _____ J r1.5V . _ _ _ _ _ _ _--+-_--_--_-_tS _E_T_--__'-_" STB or _ 1.SV X- - - ----------- -- 'i1.
SCHOTTKY BIPOLAR 8212 A.C. Characteristics TA = O°C to + 75°C Symbol Vee = +5V ± 5% Limits Parameter Typ. Min. Unit t pw Pulse Width t pd Data To Output Delay 30 ns t we Write Enable To Output Delay 40 ns t set Data Setu·p Time 15 ns th Data Hold Time 20 ns tr Reset To Output Delay 40 ns ts Set To Output Delay 30 ns te Output Enable/Disable Time 45 ns tc Clear To Output Delay 55 ns CAPACITANCE * Symbol F 30 = 1 MHz VsrAs = 2.5V Vee Test Conditions Max.
Silicon Gate MOS 8255 PROGRAMMABLE PERIPHERAL INTERFACE • Direct Bit Set/Reset Capability Easing Control Application Interface • 40 Pin Dual In-Line Package • Reduces System Package Count • 24 Programmable I/O Pins • Completely TTL Compatible • Fully Comp.atible with MCS™-8 and MCSTM'_80 Microprocessor Families The 8255 is a general purpose programmable I/O device designed for use with both the 8008 and 8080 microprocessors.
SILICON GATE MOS 8255 8255 BASIC FUNCTIONAL DESCRIPTION (RD) General Read: A II10w" on this input pin enables the 8255 to send the Data or Status information to the 8080 CPU on the Data Bus. In essence, it allows the 8080 CPU to II read from" the 8255. The 8255 is a Programmable Peripheral Interface (PPI) device designed for use in 8080 Microcomputer Systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the 8080 system bus.
SILICON GATE MOS 8255 (RESET) Ports A, B, and C Reset: A "high" on this input clears all internal registers including the Control Register and all ports (A, B, C) are set to the input mode. The 8255 contains three 8-bit ports (A, S, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own speci al featu res or "personality" to further enhance the power and flexibil ity of the 8255.
SILICON GATE MOS 8255 8255 DETAILED OPERATIONAL DESCRIPTION CONTROL WORD Mode Selection There are three basic modes of operation that can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bi-Directional Bus ~ When the RESET input goes "high" all ports will be set to the Input mode (Le., all 24 lines will be in the high impedance state). After the RESET is removed the 8255 can remain in the Input mode with no additional initialization required.
SILICON GATE MOS 8255 When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports.
SILICON GATE MOS 8255 MODE 0 PORT DEFINITION CHART A B GROUPA GROUPB PORTC PORTC 04 03 01 DO PORTA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 OUTPUT OUTPUT OUTPUT OUTPUT 1 1 0 0 1 OUTPUT INPUT 7 INPUT INPUT 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 INPUT OUTPUT 9 OUTPUT INPUT 1 0 INPUT OUTPUT 10 INPUT OUTPUT 1 0 0 1 1 INPUT OUTPUT 11 INPUT INPUT 1 1 0 INPUT INPUT 12 OUTPUT OUTPUT 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 # PORT B OUTPUT OUTPUT 0 1 O
SILICON GATE MOS 8255 CONTROL WORD #8 CONTROL WORD #4 07 A 06 Os 04 03 ,02 A B , ,4 . . ,4 18 I c{ 07 ,8 A -, c{ -, • 06 05 04 03 O2 04 ,4 ,,4 ,8 I c{ pc'-PC4 0 7 -00 PC3 -PCO B P~-PBO 07 B 06 06 04 O2 0, ,8 PA7 ·pAo ,4 -, ,4 -, ,8 I PC7 ·PC4 PC3 -PCO P~.PBO DO A 14 c{ ,,4 -,' 8 B ,,8 14 ,1 4 ,8 -, CONTROL WORD #11 03 07 A 8 06 05 PA7 ·pAo A 8255 0 7-00 03 -, CONTROL WORD #7 04 ,8 I 8255 c{ 05 .
SILICON GATE MOS 8255 CONTROL WORD #12 07 06 05 04 CONTROL WORD #14 03 O2 07 01 A 06 05 04 03 O2 ,8 . 8255 c{ · B ,4 . / ,,4 06 05 04 c{ • ,8 B ~ I CONTROL WORD #13 07 DO A F 8255 • 0, . . ,8 I ,4 I ,4 . ,8 I CONTROL WORD #15 03 O2 0, 07 DO A 06 05 04 03 O2 0, ,8 DO ,8 A 7 8255 8255 c{ , 4 c{ I ,4 7 B ,4 1 ,4 7 ,8 B I ,,8 P~.
SILICON GATE MOS 8255 Input Control Signal Definition MODE 1 (PORT A) STB (Strobe (nput) A "low" on this input loads data into the input latch. CONTROL WORD IBF (Input Buffer Full F/F) STB A A "high" on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgement ISF is set by the falling edge of the STB input and is reset by the rising edge of the RD input.
SILICON GATE MOS 8255 Output Control Signal Definition OBF (Output Buffer Full F/F) MODE 1 (PORT A) The OBF output will go ~'Iow" to indicate that the CPU has written data out to the specified port. The OBF F/F will be set by the rising edge of the WR input and reset by the failing edge of the ACK input signal. CONTROL WORD r- - -, I INTE I I __ A .JI ACK (Acknowledge Input) A "Iow" on this input informs the 8255 that the data from Port A or Port B has been accepted.
SILICON GATE MOS 8255 Combinations of Mode 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. PA7 -PAo PA 7 -PAO 8 PC4 STBA PCs IBFA 8 PC 7 OBFA PC6 - + - - ACKA CONTROL WORD PC3 PC 3 INTRA 2 PC6 • 7 ..-.;-.-..
SILICON GATE MOS 8255 CONTROL WORD OBF A pC 200 ACKA 1 = INPUT 0= OUTPUT r--l PORTB 1 = INPUT 0= OUTPUT IN;E L __ I J PC4 . STBA PCs GROUP B MODE 0= MODE 0 1 = MODE 1 AD Mode 2 Control Word PC200 Mode 2 \'----" INTR 1 IBF DATA BUS (BETWEEN I/O CHIP AND I/O DEVICE) - - - - - - IBFA WR - DATA I/O DEVICE -+- Mode 2 (Bi-directional) Timing 5-124 I/O CHIP DATA I/O CHIP -+ I/O DEVICE .
SILICON GATE MOS 8255 MODE 2 AND MODE 0 (OUTPUT) MODE 2 AND MODE 0 (INPUT) PC3 INTRA PC3 PA7 -PAO ~ PC 6 CONTROL WORD PA7 -PAo OBFA . P~ ACKA CONTROL WORD PC4 STBA PC5 IBFA . ACKA PC4 . STBA I/O PC2.() AD IBFA PC5 PC2.() 1 = INPUT 0= OUTPUT 3 PC2.() OBFA PC6 0 7 0 6 0 5 0 4 0 3 O2 0, DO 0 7 0 6 05 04 03 O2 0, DO PC 2.() 1 = INPUT O=OUTPUT INTRA . 3 I I I/O " RO 8 PB 7 -PBO P~-PBO WR WR MODE 2 AND MODE 1 (OUTPUT) MODE 2 AND MODE 1 (INPUT) PC3 PC3 A ~ A.
SILICON GATE MOS 8255 MODE DEFINITION SUMMARY TABLE PAO PA1 PA2 PA3 PA4 PAS PAe PA7 IN IN IN IN IN IN IN IN MODE 0 OUT OUT OUT OUT OUT OUT OUT OUT OUT PBO P81 PB2 PB3 PB4 PB5 PBe PB7 IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT PCO PC, PC2 PC3 PC4 PCS PC6 PC7 IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT INTRB IBFB STBB INTRA STBA IBFA I/O I/O INTRB OBFB ACKB INTRA I/O I/O ACKA OBFA IN IN IN IN IN IN IN IN IN MODE 1
SILICON GATE MOS 8255 INTERRUPT REQUE STi APPLICATIONS OF THE 8255 PC 3 The 8255 is a very powerful tool for interfacing peripheral equipment to the 8080 microcomputer system. It represents the optimum use of available pins and is flexible enough to interface almost any I/O device without the need for additional external logic. - MODE 1 _ (INPUT) Each peripheral device in a Microcomputer system usually has a "service routine" associated with it.
SILICON GATE MOS 8255 INTERRUPT REQUE STi IP~ PAl I LSB r-- PC3 PA2 JPA PA3 PBO Do PB, 0, PB 2 O2 03 PB3 4 MODE 0 (OUTPUT) PAS ; PA PB4 PBs f-----------.. 12-BIT D-A CONVERTER (DAC) 6 PA7 PC4 PCS ---. ANALOG OUTPUT ,PC O BIT 06 PC4 PCS ACK (IN) PC7 _Pe 6 PC2 SAMPLE EN PC 3 STB PBO LSB DATA STB DATA READY ACK (OUT) 8255 OUTPUT EN PC2 TRACK "0" SENSOR PCo SYNC READY PC, INDEX PAO ENGAGE HEAD I SET/RESETl DS 07 STB DATA PC, ,...
SILICON GATE MOS 8255 I SYSTEM BUS (0, A, AND C) r--- ~---- I- - - - - , ,-- ~v ~V "",,-/7 "v'7 8080 CPU MEMORY ROM AND RAM 8255 8255 MODE 2 ..t. A t- - - - - , 1-- --.
SILICON GATE MOS 8255 D.C. CHARACTERISTICS TA = o°c to 70°C; Vee = +5V ±5%; vss = OV Typ. Symbol Parameter Vil Input Low Voltage V IH Input High Voltage Val Output Low Voltage VOH Output High Voltage IOH[1] Darlington Drive Current 2.0 rnA Ice Power Supply Current 40 rnA Min. Max. Unit .8 V Test Conditions V 2.0 .4 2.4 V IOl = 1.6mA V IOH = -50JlA (-1 OOJlA for D.B. Port) VOH=1.5V, REXT=390n NOTE: 1. Available on 8 pins only. A.C.
SILICON GATE MOS 8255 .. ~ t RP ~ ~ 7 I[ ~tHR-----" .--t'R---' K >: INPUT ~tRA--" tAR :~ ~~ A1,AO t RC ~tCR----' \~ JV :0- ~ ----- -- -- ---- .. t RD .. too Mode 0 (Basic Input) ~ .. twp { ,-- f-- 7 \ ~twD--' ~tDW~ )( tAW A1,AO twA )( .. cs K .. t cw JK .. twc \\ OUTPUT .. ~ J )( . twB Mode 0 (Basic Output) 5-131 -------.
SILICON GATE MOS 8255 IBF ~tRI INTR INPUT FROM PERIPHERAL _ I . . . - - - - - tps - - - - - .
SILICON GATE MOS 8255 .
Silicon Gate MOS 8251 PROGRAMMABLE COMMUNICATION INTERFACE .. Synchronous and Asynchronous Operation • Synchronous: 5-8 Bit Characters Internal or External Character Synchronization Automatic Sy.nc Insertion • Asynchronous: 5-8 Bit Characters Clock Rate -1,16 or 64 Times Baud Rate Break Character Generation 1, 1 1h, or 2 Stop Bits False Start Bit Detection • Baud Rate - DC to 56 k Baud ( Sync Mode) DC t09.
SILICON GATE MOS 8251 8251 BASIC FUNCTIONAL DESCRIPTION General C/D (Control/Data) The 8251 is a Universal Synchronous!Asynchronous Receiver/Transmitter designed specifically for the 8080 Microcomputer System. like other I!O devices in the 8080 Microcomputer System its functional configuration is programmed by the systems software for maximum flexibility. The 8251 can support virtually any serial data technique currently in use (including IBM "bi-sync").
SILICON GATE MOS 8251 Modem Control TxE (Transmitter Empty) The 8251 has a set of control inputs and outputs that can be used to simplify the interface to almost any Modem. The modem control signals are general purpose in nature and can be used for functions other than Modem control, if necessary. When the 8251 has no characters to transm it, the T x E output will go "high". It resets automatically upon receiving a character from the CPU.
SILICON GATE MOS 8251 Receiver Buffer The Receiver accepts serial data, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an "assembled" character to the CPU. Serial data is input to the RxD pin. When used as an input, (external SYNC detect mode), a positive going signal will cause the 8251 to start assembling data characters on the falling edge of the next RxC. Once in SYNC, the "high" input signal can be removed.
SILICON GATE MOS 8251 DETAILED OPERATION DESCRIPTION General The complete functional definition of the 8251 is programmed by the systems software. A set of control words must be sent out by the CPU to initialize the 8251 to support the desired communications format. These control words will program the: BAUD RATE, CHARACTER LENGTH, NUMBER OF STOP BITS, SYNCHRONOUS or ASYNCHRONOUS OPERATION, EVEN/ODD PARITY etc.
SILICON GATE MOS 8251 Mode Instruction Definition The 8251 can be used for either Asynchronous or Synchronous data communication. To understand how the Mode Instruction defines the functional operation of the 8251 the designer can best view the device as two separate components sharing the same package. One Asynchronous the other Synchronous. The format definition can be changed lion the fly" but for explanation purposes the two formats will be isolated.
SILICON GATE MOS 8251 Synchronous Mode (Transmission) The TxD output is continuously high until the CPU sends its first character to the 8251 which usually is a SYNC character. When the CTS line goes low, the first character is serially transmitted out. All characters are shifted out on the falling edge of TxC. Data is shifted out at the same rate as the TxC. CHARACTER LENGTH Once transmission has started, the data stream at TxD output must continue at the TxC rate.
SILICON GATE MOS 8251 COMMAND INSTRUCTION DEFINITION STATUS READ DEFINITION Once the functional definition of the 8251 has been programmed by the Mode Instruction and the Sync Characters are loaded (if in· Sync Mode) then the device is ready to be used for data communication. The Command Instruction controls the actual operation of the selected format. Functions such as: Enable Transmit/Receive, Error Reset and Modem Controls are provided by the Command Instruction.
SILICON GATE MOS 8251 APPLICATIONS OF THE 8251 ADDRESS BUS ADDRESS BUS CONTROL BUS CONTROL BUS DATA BUS DATA BUS r----' I EIA TO TTL :. CONVERT I IL ____ (OPT) J 8251 BAUD RATE GENERATOR TxC QJ) :: ASYNC MODEM CRT TERMINAL PHONE LINE INTER· FACE 8251 Asynchronous Serial Interface to CRT Terminal, DC-9600 Baud TELEPHONE LINE Asynchronous Interface to Telephone Lines L.- ADDRESS BUS .....
SILICON GATE MOS 8251 D.C. Characteristics: Symbol Parameter Min. Typ. Max. Unit V,L Input Low Voltage Vss-·5 0.8 V VIH Input High Voltage 2.0 Vee V VOL Output Low Voltage 0.45 V VOH Output High Voltage IOL Data Bus Leakage 50 IJ.A ILl Input Load Current 10 IlA Icc Power Supply Current 2.2 V 45 80 Typ. Max. Unit Test Conditions = 1.6mA IOH = -1001lA ( DB o-7) IOH = -1001lA (Others) IOl VOUT = 4.5V @5.
SILICON GATE MOS 8251 A.C. Characteristics: TA = o°c to 70°C; VCC = 5.0V ±5%; Vss = OV Parameter Symbol Min. Typ. Max. Unit tCY Clock Period .420 1.
SILICON GATE MOS 8251 READ AND WRITE TIMING ..,1'----------------""1"---------"1'-- CID,CS. D7 -DO -----..--'I~ ~-- t DS -------1~ . .- - *WRITE ------J---..:.-/'..--- twR ""-'-----...,t.......--- 1 ·WRITE AND READ PULSES HAVE NO TIMING LIMITATION WITH RESPECT TO ClK. TRANSMITTER CLOCK AND DATA J;:- I TxC(1xBAUDI 16 TxC P E R I O D S - - - - - - - : : ; C TxC (16x BAUD) TxD _ 4IlI --~~f ___ x--- __ RECEIVER CLOCK AND DATA RXD=..:..
Peripherals 8205 8214 8216/8226
Schottky Bipolar 8205 HIGH SPEED 1 OUT OF 8 BINARY DECODER • Low Input Load Current - .25 mA max., 1/6 Standard TTL Input Load • Minimum Line Reflection - Low Voltage Diode Input Clamp • 110 Port or Memory Selector • Simple Expansion - Enable Inputs • High Speed Schottky Bipolar Technology - 18ns Max. Delay • Outputs Sink 10 mA min.
SCHOTTKY BIPOLAR 8205 FUNCTIONAL DESCRIPTION Decoder The 8205 contains a one out of eight binary decoder. It accepts a three bit binary code and by gating this input, creates an exclusive output that represents the value of the input code. ~ I"" . lI"" . For example, if a binary code of 101 was present on the AO, A1 and A2 address input lines, and the device was enabled, an active low signal would appear on the 05 output line.
SCHOTTKY BIPOLAR 8205 APPLICATIONS OF THE 8205 ray of 8205s can be used to create a simple interface to a 24K memory system. The 8205 can be used in a wide variety of applications in microcomputer systems. I/O ports can be decoded from the address bus, chip select signals can be generated to select memory devices and the type of machine state such as in 8008 systems can be derived from a simple decoding of the state lines (SO, S1, S2) of the 8008 CPU.
SCHOTTKY BIPOLAR 8205 Logic Element Example Probably the most overlooked application of the 8205 is that of a general purpose logic element. Using the lion-chip" enabl ing gate, the 8205 can be configu red to gate its decoded outputs with system timing signals and generate strobes that can be directly connected to latches, flip-flops and one-shots that are used throughout the system. and T2 decoded strobes can connect directly to devices like 8212s for latching the address information.
SCHOTTKY BIPOLAR 8205 ABSOLUTE MAXIMUM RATINGS· Temperatu re Under Bias: *COMMENT -65°C to +125° C -65°C to +75°C Ceram ic Plastic Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
SCHOTTKY BIPOLAR 8205 8205 SWITCHING CHARACTERISTICS CONDITIONS OF TEST: Input pulse amplitudes: TEST LOAD: 390n 2.5V Input rise and fall times: 5 nsec between 1V and 2V Measurements are made at 1.5V 2K All Transistors 2N2369 or Equivalent. TEST WAVEFORMS ADDRESS OR ENABLE INPUT PULSE ---..1'~1 _ _ _ _ ___t+_-_'.... t++ 1'---___ =b~:.:~-I.-,..-------- I-: I eL = 30 pF , , , , OUTPUT = aoc to +75°C, Vee = 5.0V ±5% unless otherwise specified. A.C. CHARACTERISTICS TA PARAMETER SYMBOL MAX.
Schottky Bipolar 8214 PRIORITY INTERRUPT CONTROL UNIT • Eight Priority Levels • Current Status Register • Priority Comparator • Fully Expandable • High Performance (50ns) • 24-Pin Dual In-Line Package The 8214 is an eight level priority interrupt control unit designed to simplify interrupt driven microcomputer systems.
SCHOTTKY BIPOLAR 8214 INTERRUPTS IN MICROCOMPUTER SYSTEMS Microcomputer system design requires that I/O devices such as keyboards, displays, sensors and other components receive servicing in an efficient method so that large amounts of the total systems tasks can be assumed by the microcomputer with little or no effect on throughput. CPU·DRIVEN MULTIPLEXOR CPU The most common method of servicing such devices is the Polled approach.
SCHOTTKY BIPOLAR 8214 FUNCTIONAL DESCRIPTION General 'he 8214 is a device specifically designed for use in real time, interrupt driven, microcomputer systems.
SCHOTTKY BIPOLAR 8214 Control Signals INT The 8214 also has several inputs that enable the designer to synchronize the interrupt issued to the microprocessor and to allow or disallow such an issuance. Also, signals are provided that perm it simple expansion to other 8214s so that more than eight levels can be controlled. The INT output of the 8214 is the signal that is issued to the microprocessor to initiate the interrupt sequence.
SCHOTTKY BIPOLAR 8214 APPLICATIONS OF THE 8214 8 Level Controller (8080) Basic Operation The most common of applications of the 8214 is that of an eight level priority structure for 8080 or 8008 microcomputer systems. When the initial interrupt request is presented to the 8214 it will issue an interrupt to the 8080 if the structure is enabled. The 8214 will encode the request into 3 bits (modulo 8) and output them to the 8212.
SCHOTTKY BIPOLAR 8214 DO 8080 BI-ol RECTIONAL BUS ~ ~ ~ ~ 0 ~5 T I T ~ ~2 (TIL) INTE I • IIII • I ,6 I I I • I cl ClK ETLG 1K~ ~ ~: INT I:> 5 III~ b 11 GND PFlg mJ - 2 8214 RESET PR 4 PA5 PR6 PR 7 14 CLR 8212 os, ~ PRIORITY ARRAY EN (FROM I/O PORT DECODER) INT p5 ,~~~ 17~R, 1B~R2 ~~ Ri "'::lI 7n::3R'4 21 ~ R6 ?~~ A J! 8214 9 10 2 ~ ~ ~ 4 22 5 06 07 I/O R GND INTE 3 2 ffl1 7 ClK ETlG 13 PR 3 INT p23 oS2 Mo GND 1~ 0, 0 20 ~ECS ~ Do 7 16 ~3 4 18
SCHOTTKY BIPOLAR 8214 APPLICATIONS OF THE 8214 RST7 Cascading the 8214 SAVE PROCESSOR STATUS When greater than eight levels of interrupts must be prioritized and serviced, the 8214 can be cascaded with other 8214s to support such an .architecture. On the previous page a simple circuit is shown that can control 16 levels of interrupt and is easily expandable to support up to 40 levels of interrupt by just cascading more 8214s.
SCHOTTKY BIPOLAR 8214 D.C. AND OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias O°C to 70°C -65°C to +150°C Storage Temperature All Output and Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to +7V All Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.0V to +5.5V Output Currents . . . . . . . . . . . . . . . . . . . . . .
SCHOTTKY BIPOLAR 8214 A.C. CHARACTERISTICS AND WAVEFORMS TA = o°c to +70°C, vcc = +5V ±5% Parameter Symbol Min. Limits Typ.[1] Max.
SCHOTTKY BIPOLAR 8214 WAVEFORMS ENLG -----------------"'j( -------- -J.\ _ NOTES: (1) Typical values are for T A = 25°C ,Vee = 5.0V. (2) Required for proper operation if ISE is enabled during next clock pulse. (3) These times are not required for proper operation but for desired change in interrupt flip-flop. (4) Required for new request or status to be properly loaded. TEST CONDITIONS: TEST LOAD CI RCUIT Vee ) Input pulse amplitude: 2.5 volts.
Schottky Bipolar 8216/8226 4 BIT PARALLEL BIDIRECTIONAL BUS DRIVER • 3.65V Output High Voltage for Direct Interface to 8080 CPU • Data Bus Buffer Driver for 8080 CPU • Low Input Load Current - .25 mA Maximum • High Output Drive Capability for Driving System Data Bus • Three State Outputs • Reduces System Package Count The 8216/8226 is a 4-bit bi-directional bus driver/receiver. All inputs are low power TTL compatible. For driving MOS, the DO outputs provide a high 3.
SCHOTTKY BIPOLAR 8216/8226 FUNCTIONAL DESCRIPTION Microprocessors like the 8080 are MOS devices and are generally capable of driving a single TTL load. The same is true for MOS memory devices. While this type of drive is sufficient in small systems with few components, quite often it is necessary to buffer the microprocessor and memories when adding components or expanding to a multi-board system. 01 0 0 - - - - -.... "---1---.. ------oOBO OOoo------t-----c: 1-------1-_ 01, 0-------+---1 __' "--4--.
SCHOTTKY BIPOLAR 8216/8226 APPLICATIONS OF 8216/8226 . 8080 Data Bus Buffer The 8080 CPU Data Bus is capable of driving a single TTL load and is more than adequate for small, single board systems. When expand ing such a system to more than one board to increase I/O or Memory size, it is necessary to provide a buffer. The 8216/8226 is a device that is exactly fitted to this application.
SCHOTTKY BIPOLAR 8216/8226 D.C. AND OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ' O°C to 70°C Storage Temperature -6SoC to +150°C All Output and Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -O.5V to +7V All Input Voltages -1.0V to +5.5V Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SCHOTTKY BIPOLAR 8216/8226 WAVEFORMS -'X'-:,_5V INPUTS _ l--t FD OUTPUT ENABLE .5V ---+---V OH f VOL .5V A.C. CHARACTERISTICS TA = O°C to +70°C, Vcc = +5V ±5% Parameter Symbol Limits Typ,£1] Min. Max.
Coming Soon 8253 8257 8259
Silicon Gate MOS 8253 PROGRAMMABLE INTERVAL TIMER • 3 Independent 16-Bit Counters • Count Binary or BCD • Single +5V SUPR • 24 Pin Dual-in-li • DC to 3 MHz • Programmable Counter Modes The 8253 is a programmable counter/timer chip designed for use as an 8080 (or with a single +5V supply and is packaged in a 24-pin plastic DIP. It uses nMOS technology It is organized as three independent 16-bit counters, each with a count rat software programmable by the 8080. z. ~Jmodes'of v operation are "'.
SILICON GATE MOS 8253 8253 PRELIMINARY FUNCTIONAL DESCRIPTION In Microcomputer-based systems the most common interface is to a mechanical device such as a printer head or stepper motor. All such devices have inherent delays that must be accounted for if accurate and reliable performance is to be achieved. The systems software allows for such delays by programmed timing loops. This type of programming requires significant ov~rhead and maintenance of multiple loops gets extremely complicated.
Silicon Gate MOS 8257 PROGRAMMABLE DMA CONTROLLER • Four Channel DMA Controller • Priority DMA Request Logic • Channel Inhibit Logic • Terminal and Modulo 256/128 Outputs • Auto Load Mode • Single TTL Clock «(/)21 TTL) • Single +5V SUR~~ • Expandable • 40 Pin Du ~~:W~l~\:~~ '.'., cl}mputer systems.
SILICON GATE MOS 8257 8257 PRELIMINARY FUNCTIONAL DESCRIPTION The transfer of data between a mass storage device such as a floppy disk or mag cassette and system RAM memory is often limited by the speed of the microprocessor. Removing the processor during such a transfer and letting an auxiliary device manage the transfer in a more efficient manner would greatly improve the speed and make mass storage devices more attractive, even to the small system designer.
Silicon Gate MOS 8259 PROGRAMMABLE INTERRUPT CONTROLLER • Individual Request Mask Capability • Single + 5V Sup (No Clocks) • 28 Pin Dua ckage • Eight Level Priority Controller • Expandable to 64 Levels • Programmable Interrupt Modes (Algorithms) The 8259 handles up to eight vectored priority interrupts for the 8080A CPU. I interrupts, without additional circuitry. It will be, packaged in a 28-pin plasf single +5V supply. Circuitry is static, requiring no clock input.
SILICON GATE MOS 8259 8259 PRELIMINARY FUNCTIONAL DESCRIPTION In microcomputer systems, the rate at which a peripheral device or devices can be serviced determines the total amount of system tasks that can be assigned to the control of the microprocessor. The higher the throughput the more jobs the microcomputer can do and the more cost effective it becomes.
Intel Product Number CPU GROUP ROMs RAMs I/O PERIPHERAL - - - - - Standard Package Type 8224 C 0 P 16 8228 C 0 P 28 8080A C 40 8702A C 24 8708/4 C 24 8302 C P 24 8308 C P 24 8316A C P 24 8101-2 C P 22 8111-2 C P 18 8102-2 C P 16 8102A-4 C P 16 81078-4 C P 22 5101 C P 22 P 18 8210 0 8222 D 8212 0 8255 C 8251 C 8205 C 8214 C 8216/26 COMING SOON - Number Of Pins 22 P Comments Including 8080A-1, 8080A-2 and M8080A New Pro
PACKAGING INFORMATION Dimensions in inches and (millimeters). 16-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) 16-LEAD CerDIP DUAL IN-LINE PACKAGE (D) ~:[O:::JJ .735~ I I .830 121,0821 ~~ .070 (1,778) ~!2.ill1_ .023 10,5841 :Q!Q~- I---l-~ ~ .06511.651 .11012,7941 TYP. 16-LEAD PLASTIC DUAL IN-LINE PACKAGE (P) 1a-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) -- -- .855121,7171 ~ lli!.ml If----_ ALTERNATE PIN ;:1 IDENT. (IF NO NOTCH AT END OF PKG.I .-r--t==:I..lI::t.~....:::::::Io.I:=--e::s...
PACKAGING INFORMATION Dimensions in inches and (millimeters). 22-LEAD PLASTIC DUAL IN-LINE PACKAGE (P) PIN 1 ~ I ·34o~ I .360 19.144) .126 13.175) 1;r==i="-.=:::::p;;;;;r==:p;;;;r=;~==p:;r=::::p;:;;;;r=:::;;:::;;r==Fr===r;;;;;:;==;:;:or="'~ . I 1.090 ~) 1.110128.194) .02010,508) MIN. - - - - - -L --r- \.--.J..'~~~l = j ~ -j h j ~ Il .03~~p~'3) .025 10,635) RjF. ---l- ::r~ :t .160 14,0641 -.L --==l .~ I I -i~.•,~~::~, •.'.1 .15013,81) ~ -L O' ... .
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INSTRUCTION SET Summary of Processor Instructions Mnemonic Description 07 06 Instruction Code 11 J Os 04 03 02 0, Do Clock(2) Cycles MOV r1 • r2 MOVM.r MOVr.
~ INSTRUCTION SET Summary of Processor Instructions By Alphabetical Order Mnemonic Desaiptioll ACI Add immediate to A with tarry Add memory to A with tarry Add register to A with carry Add memory to A Add register to A Add immediate to A And memory with A And register with A And immediate with A Call ullCondi1ional Call on carry Call on minus Compliment A Compliment carry Compare memory with A Compare register with A Call on no carry Call on no lero Call on positive Call on parity even Compare immediate
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