8XC196NP, 80C196NU Microcontroller User’s Manual
8XC196NP, 80C196NU Microcontroller User’s Manual August 2004 Order Number 272479-003
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CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3 1.3 RELATED DOCUMENTS .............................................................................................. 1-5 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-8 1.4 1.4.
8XC196NP, 80C196NU USER’S MANUAL CHAPTER 3 ADVANCED MATH FEATURES 3.1 ENHANCED MULTIPLICATION INSTRUCTIONS ........................................................ 3-1 3.2 OPERATING MODES.................................................................................................... 3-2 3.2.1 Saturation Mode ........................................................................................................3-2 3.2.2 Fractional Mode ...................................................................
CONTENTS 4.5.1 Using Registers .......................................................................................................4-12 4.5.2 Addressing 32-bit Operands ...................................................................................4-12 4.5.3 Addressing 64-bit Operands ...................................................................................4-12 4.5.4 Linking Subroutines ................................................................................................4-13 4.
8XC196NP, 80C196NU USER’S MANUAL CHAPTER 6 STANDARD AND PTS INTERRUPTS 6.1 OVERVIEW OF INTERRUPTS...................................................................................... 6-1 6.2 INTERRUPT SIGNALS AND REGISTERS ................................................................... 6-3 6.3 INTERRUPT SOURCES AND PRIORITIES.................................................................. 6-4 6.3.1 Special Interrupts ...................................................................................
CONTENTS 7.3.1.4 Open-drain Output Mode ...................................................................................7-14 7.3.1.5 Input Mode .........................................................................................................7-16 7.3.2 Configuring EPORT Pins ........................................................................................7-17 7.3.2.1 Configuring EPORT Pins for Extended-address Functions ................................7-17 7.3.2.
8XC196NP, 80C196NU USER’S MANUAL 10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS ....................................... 10-2 10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 10-5 10.3.1 Cascade Mode (Timer 2 Only) ................................................................................10-6 10.3.2 Quadrature Clocking Mode .....................................................................................10-6 10.4 EPA CHANNEL FUNCTIONAL OVERVIEW ..
CONTENTS 12.3 IDLE MODE ................................................................................................................. 12-5 12.4 STANDBY MODE (80C196NU ONLY) ........................................................................ 12-6 12.4.1 Enabling and Disabling Standby Mode ...................................................................12-6 12.4.2 Entering Standby Mode ..........................................................................................12-6 12.4.
8XC196NP, 80C196NU USER’S MANUAL APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS B.1 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. B-1 B.2 SIGNAL DESCRIPTIONS............................................................................................. B-6 B.3 DEFAULT CONDITIONS ............................................................................................
CONTENTS FIGURES Figure 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 7-1 7-2 7-3 8-1 8-2 8-3 8-4 Page 8XC196NP and 80C196NU Block Diagram .................................................................2-2 Block Diagram of the Core ...........................................................................................2-3 Clock Circuitry (8XC196NP) .........................................
8XC196NP, 80C196NU USER’S MANUAL FIGURES Figure 8-5 8-6 8-7 8-8 9-1 9-2 9-3 9-4 9-5 9-6 9-7 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 13-4 13-5 13-6 xii Page Serial Port Frames in Mode 2 and 3.............................................................................8-7 Serial Port Control (SP_CON) Register........................................................................
CONTENTS FIGURES Figure 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 B-1 B-2 B-3 B-4 Page Chip Configuration 1 (CCR1) Register .....................................................................13-16 Multiplexing and Bus Width Options.........................................................................13-19 Bus Activity for Four Types of Buses........................................................................
8XC196NP, 80C196NU USER’S MANUAL TABLES Table 1-1 1-2 1-3 1-4 1-5 2-1 2-2 2-3 3-1 3-2 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 xiv Page Handbooks and Product Information ............................................................................1-6 Application Notes, Application Briefs, and Article Reprints ..........................................
CONTENTS TABLES Table 7-9 7-10 7-11 7-12 7-13 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 11-1 11-2 12-1 12-2 12-3 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 A-1 A-1 A-2 A-3 Page EPORT Pins ...............................................................................................................7-11 EPORT Control and Status Registers ........................................................................
8XC196NP, 80C196NU USER’S MANUAL TABLES Table A-4 A-5 A-6 A-7 A-8 A-9 B-1 B-2 B-3 B-4 B-5 C-1 C-2 C-3 C-4 C-5 C-6 C-7 C-8 C-9 C-10 C-11 C-12 C-13 C-14 C-15 C-16 C-17 C-18 C-19 xvi Page PSW Flag Setting Symbols ......................................................................................... A-5 Operand Variables ...................................................................................................... A-6 Instruction Set ................................................................
1 Guide to This Manual
CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196NP and 80C196NU embedded microcontrollers. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you complete your design. 1.1 MANUAL CONTENTS This manual contains several chapters and appendixes, a glossary, and an index.
8XC196NP, 80C196NU USER’S MANUAL Chapter 8 — Serial I/O (SIO) Port — describes the asynchronous/synchronous serial I/O (SIO) port and explains how to program it. Chapter 9 —Pulse-width Modulator — provides a functional overview of the pulse width modulator (PWM) modules, describes how to program them, and provides sample circuitry for converting the PWM outputs to analog signals.
GUIDE TO THIS MANUAL 1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used throughout this manual. The Glossary defines other terms with special meanings. # The pound symbol (#) has either of two meanings, depending on the context. When used with a signal name, the symbol means that the signal is active low. When used in an instruction, the symbol prefixes an immediate value in immediate addressing mode.
8XC196NP, 80C196NU USER’S MANUAL italics Italics identify variables and introduce new terminology. The context in which italics are used distinguishes between the two possible meanings. Variables in registers and signal names are commonly represented by x and y, where x represents the first variable and y represents the second variable. For example, in register Px_MODE.
GUIDE TO THIS MANUAL t Lowercase “t” represents the internal operating period. See “Internal Timing” on page 2-7 for details. units of measure The following abbreviations are used to represent units of measure: A DCV Kbytes kHz kΩ mA Mbytes MHz ms mW ns pF W V µA µF µs µW X 1.
8XC196NP, 80C196NU USER’S MANUAL Table 1-1. Handbooks and Product Information Title and Description Order Number Intel Embedded Quick Reference Guide Solutions for Embedded Applications Guide Data on Demand fact sheet Data on Demand annual subscription (6 issues; Windows* version) Complete set of Intel handbooks on CD-ROM. Handbook Set — handbooks and product overview Complete set of Intel’s product line handbooks.
GUIDE TO THIS MANUAL Table 1-2.
8XC196NP, 80C196NU USER’S MANUAL Table 1-5.
GUIDE TO THIS MANUAL Page Intentionally Left Blank 1-9
8XC196NP, 80C196NU USER’S MANUAL Page Intentionally Left Blank 1-10
GUIDE TO THIS MANUAL 1.4.4 World Wide Web We offer a variety of information through the World Wide Web (URL:http://www.intel.com/). Select “Embedded Design Products” from the Intel home page. 1.5 TECHNICAL SUPPORT In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S.
2 Architectural Overview
CHAPTER 2 ARCHITECTURAL OVERVIEW The 16-bit 8XC196NP and 80C196NU CHMOS microcontrollers are designed to handle highspeed calculations and fast input/output (I/O) operations. They share a common architecture and instruction set with other members of the MCS® 96 microcontroller family. In addition to their 16-bit address/data buses, both microcontrollers have extended addressing ports consisting of 4 external address pins, for a total of 20 address pins.
8XC196NP, 80C196NU USER’S MANUAL 2.2 DEVICE FEATURES Table 2-1 lists the features of the 8XC196NP and 80C196NU. Table 2-1. Features of the 8XC196NP and 80C196NU Device Pins ROM (Note 1) Register RAM (Note 2) I/O Pins (Note 3) EPA Pins SIO Ports PWM Channels Chipselect Pins External Interrupt Pins 8XC196NP 100 4K 1024 64 4 1 3 6 4 80C196NU 100 0 1024 64 4 1 3 6 4 NOTES: 1. Nonvolatile memory is optional for the 8XC196NP, but is not available for the 80C196NU.
ARCHITECTURAL OVERVIEW Memory Controller CPU Register File Register RAM RALU Prefetch Queue Microcode Engine Slave PC ALU Address Register Master PC Data Register PSW CPU SFRs Registers Bus Controller A2797-01 Figure 2-2. Block Diagram of the Core 2.3.
8XC196NP, 80C196NU USER’S MANUAL 2.3.3 Register Arithmetic-logic Unit (RALU) The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master program counter (PC), the processor status word (PSW), and several registers. The registers in the RALU are the instruction register, a constants register, a bit-select register, a loop counter, and three temporary registers (the upper-word, lower-word, and second-operand registers).
ARCHITECTURAL OVERVIEW 2.3.3.2 Instruction Format MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operand instruction format. This format allows a single instruction to specify two source registers and a separate destination register. For example, the following instruction multiplies two 16-bit variables and stores the 32-bit result in a third variable.
8XC196NP, 80C196NU USER’S MANUAL The extended program counter (EPC) is an extension of the slave PC. The EPC generates the upper eight address bits for extended code fetches and outputs them on the extended addressing port (EPORT). Because only four EPORT pins are implemented, only the lower four address bits are available. (See Chapter 5, “Memory Partitions,” for additional information.
ARCHITECTURAL OVERVIEW 2.4 INTERNAL TIMING The clock circuitry of the 8XC196NP (Figure 2-3) is identical to that of earlier MCS 96 microcontrollers. It receives an input clock signal on XTAL1 provided by an external crystal or clock and divides the frequency by two. The clock generators accept the divided input frequency from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2. These signals are active when high.
8XC196NP, 80C196NU USER’S MANUAL Disable PLL (Powerdown) FXTAL1 Phase Comparator FXTAL1 XTAL1 Phaselocked Oscillator Disable Oscillator (Powerdown) 4FXTAL1 2FXTAL1 XTAL2 Disable Clock Input (Powerdown) f PLLEN1 Filter Phase-locked Loop Clock Multiplier Divide-by-two Circuit f 2 Disable Clocks (Standby, Powerdown) PLLEN2 Peripheral Clocks (PH1, PH2) Clock Generators CLKOUT CPU Clocks (PH1, PH2) Disable Clocks (Idle, Standby, Powerdown) A3063-02 Figure 2-4.
ARCHITECTURAL OVERVIEW XTAL1 t t 1 State Time 1 State Time PH1 PH2 CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0805-01 Figure 2-5. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. Table 2-2. State Times at Various Frequencies f (Frequency Input to the Divide-by-two Circuit) State Time 12.
8XC196NP, 80C196NU USER’S MANUAL Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times FXTAL1 (Frequency on XTAL1) PLLEN2:1 Multiplier f (Input Frequency to the Divide-by-two Circuit) t (Clock Period) State Time 50 MHz † 00 1 50 MHz 20 ns 40 ns 00 1 25 MHz 40 ns 80 ns 10 2 50 MHz 20 ns 40 ns 00 1 12.5 MHz 80 ns 160 ns 10 2 25 MHz 40 ns 80 ns 11 4 50 MHz 20 ns 40 ns 25 MHz 12.5 MHz † Assumes an external clock.
ARCHITECTURAL OVERVIEW 2.5 INTERNAL PERIPHERALS The internal peripheral modules provide special functions for a variety of applications. This section provides a brief description of the peripherals; subsequent chapters describe them in detail. 2.5.1 I/O Ports The 8XC196NP and 80C196NU have five I/O ports, ports 1–4 and the EPORT. Individual port pins are multiplexed to serve as standard I/O or to carry special-function signals associated with an on-chip peripheral or an off-chip component.
8XC196NP, 80C196NU USER’S MANUAL Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or externally. Each timer/counter is called a timer if it is clocked internally and a counter if it is clocked externally. See Chapter 10, “Event Processor Array (EPA),” for additional information on the EPA and timer/counters. 2.5.
ARCHITECTURAL OVERVIEW 2.6.2 Testing the Printed Circuit Board The on-circuit emulation (ONCE) mode electrically isolates the 8XC196 device from the system. By invoking ONCE mode, you can test the printed circuit board while the device is soldered onto the board. 2.7 DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS This section summarizes differences to consider when converting your design requirements from the 80C196NP to the 80C196NU.
8XC196NP, 80C196NU USER’S MANUAL • The 80C196NU’s PWM has an additional prescaler option (divide-by-4), controlled by the PWM control register (CON_REG0). • When operating with a demultiplexed bus, the 80C196NU can add an automatic delay in the first cycle following a chip-select change or in a write cycle that follows a read. This mode, called deferred mode, extends the following timing specifications by two clock periods (2t): TAVDV, TAVWL, TAVRL, TRLDV, TRHDZ, TRHRL, TLHLH , TRHLH, TSLDV, and TWHLH.
3 Advanced Math Features
CHAPTER 3 ADVANCED MATH FEATURES The 80C196NU is the first member of the MCS® 96 microcontroller family to incorporate enhanced 16-bit multiplication instructions for performing multiply-accumulate operations and a dedicated, 32-bit accumulator register for storing the results of these operations. The accumulator and the enhanced instructions combine to decrease the amount of time required to perform multiply-accumulate operations.
8XC196NP, 80C196NU USER’S MANUAL Table 3-1.
ADVANCED MATH FEATURES 3.2.2 Fractional Mode A signed fractional contains an imaginary decimal point between the sign bit (the MSB) and the adjacent bit. These examples illustrate the representation of 32-bit signed fractional numbers: 0.111 1111 1111 1111 1111 1111 1111 1111 2147483647 = --------------------------------- = 1 2147483648 0.000 0000 0000 0000 0000 0000 0000 0000 = 0 –1 1.111 1111 1111 1111 1111 1111 1111 1111 = --------------------------------- = –0 2147483648 1.
8XC196NP, 80C196NU USER’S MANUAL 3.3 ACCUMULATOR REGISTER (ACC_0x) The 32-bit accumulator register (Figure 3-1) resides at locations 0C–0FH. Read from or write to the accumulator register as two words at locations 0CH and 0EH. Address: Reset State: ACC_0x x = 0, 2 (80C196NU) 0EH, 0CH 00H The 32-bit accumulator register (ACC_0x) resides at locations 0C–0FH. You can read from or write to the accumulator register as two words at locations 0CH and 0EH.
ADVANCED MATH FEATURES 3.4 ACCUMULATOR CONTROL AND STATUS REGISTER (ACC_STAT) The ACC_STAT register controls the operating mode and reflects the status of the accumulator. The mode bits (FME and SME) are effective only for signed multiplication. Table 3-2 describes the 80C196NU’s operation with each of the four possible configurations of these bits.
8XC196NP, 80C196NU USER’S MANUAL Table 3-2. Effect of SME and FME Bit Combinations SME FME 0 0 Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend (the number to be added to the contents of the accumulator) are equal, but the sign bit of the result is the opposite. 0 1 Shifts the addend (the number to be added to the contents of the accumulator) left by one bit before adding it to the accumulator.
4 Programming Considerations
CHAPTER 4 PROGRAMMING CONSIDERATIONS This section provides an overview of the instruction set of the MCS® 96 microcontrollers and offers guidelines for program development. For detailed information about specific instructions, see Appendix A. OVERVIEW OF THE INSTRUCTION SET 4.1 The instruction set supports a variety of operand types likely to be useful in control applications (see Table 4-1). NOTE The operand-type variables are shown in all capitals to avoid confusion.
8XC196NP, 80C196NU USER’S MANUAL Table 4-2 lists the equivalent operand-type names for both C programming and assembly language. Table 4-2. Equivalent Operand Types for Assembly and C Programming Languages Operand Types Assembly Language Equivalent C Programming Language Equivalent BYTE BYTE unsigned char SHORT-INTEGER BYTE char WORD WORD unsigned int INTEGER WORD int DOUBLE-WORD LONG unsigned long LONG-INTEGER LONG long QUAD-WORD — — 4.1.
PROGRAMMING CONSIDERATIONS 4.1.4 WORD Operands A WORD is an unsigned, 16-bit variable that can take on values from 0 through 65,535 (216–1). Arithmetic and relational operators can be applied to WORD operands, but the result must be interpreted in modulo 65536 arithmetic. Logical operations on WORDs are applied bitwise. Bits within WORDs are labeled from 0 to 15; bit 0 is the least-significant bit. WORDs must be aligned at even byte boundaries in the address space.
8XC196NP, 80C196NU USER’S MANUAL 4.1.7 LONG-INTEGER Operands A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648 (– 231) through +2,147,483,647 (+231–1). The architecture directly supports LONG-INTEGER operands only as the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations.
PROGRAMMING CONSIDERATIONS 4.1.11 Floating Point Operations The hardware does not directly support operations on REAL (floating point) variables. Those operations are supported by floating point libraries from third-party tool vendors. (See the Development Tools Handbook.) The performance of these operations is significantly improved by the NORML instruction and by the sticky bit (ST) flag in the processor status word (PSW).
8XC196NP, 80C196NU USER’S MANUAL EST Extended store word. Stores the value of the source (leftmost) word operand into the destination (rightmost) operand. This instruction allows you to move data from the lower register file to anywhere in the address space. It operates in extended indirect and extended indexed modes. ESTB Extended store byte. Stores the value of the source (leftmost) byte operand into the destination (rightmost) operand.
PROGRAMMING CONSIDERATIONS Table 4-3. Definition of Temporary Registers Temporary Register Description AX word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte BX word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte CX word-aligned 16-bit register; CH is the high byte of CX and CL is the low byte 4.2.
8XC196NP, 80C196NU USER’S MANUAL LD AX,[BX] ADDB AL,BL,[CX] POP [AX] 4.2.3.1 ; ; ; ; AX ← MEM_WORD(BX) AL ← BL + MEM_BYTE(CX) MEM_WORD(AX) ← MEM_WORD(SP) SP ← SP + 2 Extended Indirect Addressing Extended load and store instructions can use indirect addressing. The only difference is that the register containing the indirect address must be a word-aligned 24-bit register to allow access to the entire 1-Mbyte address space.
PROGRAMMING CONSIDERATIONS 4.2.3.4 Indirect Addressing with the Stack Pointer You can also use indirect addressing to access the top of the stack by using the stack pointer as the WORD register in an indirect reference. The following instruction uses indirect addressing with the stack pointer: PUSH [SP] 4.2.4 ; duplicate top of stack ; SP ← SP +2 Indexed Addressing Indexed addressing calculates an address by adding an offset to a base address.
8XC196NP, 80C196NU USER’S MANUAL ST AX,TABLE[BX] ADDB AL,BL,LOOKUP[CX] ; MEM_WORD(TABLE+BX) ← AX ; AL ← BL + MEM_BYTE(LOOKUP+CX) The instruction LD AX, TABLE[BX] loads AX with the contents of the memory location that resides at address TABLE+BX. That is, the instruction adds the contents of BX (the offset) to the constant TABLE (the base address), then loads AX with the contents of the resulting address.
PROGRAMMING CONSIDERATIONS 4.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS The assembly language simplifies the choice of addressing modes. Use these features wherever possible. 4.3.1 Direct Addressing The assembly language chooses between direct and zero-indexed addressing depending on the memory location of the operand. Simply refer to the operand by its symbolic name. If the operand is in the lower register file, the assembly language chooses a direct reference.
8XC196NP, 80C196NU USER’S MANUAL 4.5.1 Using Registers The 256-byte lower register file contains the CPU special-function registers and the stack pointer. The remainder of the lower register file and all of the upper register file is available for your use. Peripheral special-function registers (SFRs) and memory-mapped SFRs reside in higher memory. The peripheral SFRs can be windowed into the lower register file for direct access.
PROGRAMMING CONSIDERATIONS 4.5.4 Linking Subroutines Parameters are passed to subroutines via the stack. Parameters are pushed into the stack from the rightmost parameter to the left. The 8-bit parameters are pushed into the stack with the high-order byte undefined. The 32-bit parameters are pushed onto the stack as two 16-bit values; the mostsignificant half of the parameter is pushed into the stack first.
8XC196NP, 80C196NU USER’S MANUAL 4.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES The device has several features to assist in recovering from hardware and software errors. The unimplemented opcode interrupt provides protection from executing unimplemented opcodes. The hardware reset instruction (RST) can cause a reset if the program counter goes out of bounds.
5 Memory Partitions
CHAPTER 5 MEMORY PARTITIONS This chapter describes the organization of the address space, its major partitions, and the 1-Mbyte and 64-Kbyte operating modes. 1-Mbyte refers to the address space defined by the 20 external address lines. In 1-Mbyte mode, code can execute from almost anywhere in the 1-Mbyte space. In 64-Kbyte mode, code can execute only from the 64-Kbyte area FF0000–FFFFFFH. The 64Kbyte mode provides compatibility with software written for previous 16-bit MCS® 96 microcontrollers.
8XC196NP, 80C196NU USER’S MANUAL Because the four most-significant bits (MSBs) of the internal address can take any values without changing the external address, these four bits effectively produce 16 copies of the 1-Mbyte address space, for a total of 16 Mbytes in 256 pages, 00H–FFH (Figure 5-1). For example, page 01H has 15 duplicates: 11H, 21H, ..., F1H. The shaded areas in Figure 5-1 represent the overlaid areas.
MEMORY PARTITIONS Page FFH Page 00H 00FFFFH FFFFFFH External Memory External Memory 003000H 002FFFH FF3000H FF2FFFH Program Memory 80C196NP/NU: External 83C196NP: ROM 80C196NP/NU: External Memory 83C196NP: External Memory if CCB1.2 = 0 A Copy of Page FFH if CCB1.
8XC196NP, 80C196NU USER’S MANUAL Table 5-1. 8XC196NP and 80C196NU Memory Map Hex Address Description Addressing Modes FFFFFF FF3000 External device (memory or I/O) connected to address/data bus Indirect, indexed, extended FF2FFF FF2080 Program memory (Note 1) After a device reset, the first instruction fetch is from FF2080H (or F2080H in external memory).
MEMORY PARTITIONS 5.2.1 External Memory Several partitions in pages 00H and FFH and all of pages 01H–0EH are assigned to external memory (see Table 5-1). Data can be stored in any part of this memory. Instructions can be stored in any part of this memory in 1-Mbyte mode, but can be stored only in page FFH in 64-Kbyte mode. “Memory Configuration Examples” on page 5-27 contains examples of memory configurations in the two modes.
8XC196NP, 80C196NU USER’S MANUAL 5.2.2.2 Special-purpose Memory Special-purpose memory resides in locations FF2000–FF207FH. It contains several reserved memory locations, the chip configuration bytes (CCBs), and vectors for both peripheral transaction server (PTS) and standard interrupts. Note that the special-purpose memory partition of the 80C196NU differs slightly from that of the 8XC196NP. Table 5-3 describes the special-purpose memory; bold type highlights the differences. Table 5-3.
MEMORY PARTITIONS 5.2.2.3 Reserved Memory Locations Several memory locations are reserved for testing or for use in future products. Do not read or write these locations except to initialize them to the values shown in Table 5-3. The function or contents of these locations may change in future revisions; software that uses reserved locations may not function properly. 5.2.2.4 Interrupt and PTS Vectors The peripheral transaction server (PTS) vectors contain the addresses of the PTS control blocks.
8XC196NP, 80C196NU USER’S MANUAL Table 5-5.
MEMORY PARTITIONS Table 5-5.
8XC196NP, 80C196NU USER’S MANUAL Page 00H Address 03FFH General-purpose Register RAM Address 03FFH 0100H 00FFH 0000H 0100H 00FFH General-purpose Register RAM Upper Register File Stack Pointer Lower Register File CPU SFRs 001AH 0019H 0018H 0017H 0000H A0301-02 Figure 5-3. Register File Memory Map Table 5-6 on page 5-11 lists the register file memory addresses. The RALU accesses the lower register file directly, without the use of the memory controller.
MEMORY PARTITIONS Table 5-6. Register File Memory Addresses Address Range Description Addressing Modes 03FFH 0100H General-purpose register RAM; upper register file Indirect, indexed, windowed direct 00FFH 001AH General-purpose register RAM; lower register file Direct, indirect, indexed 0019H 0018H Stack pointer (SP); lower register file Direct, indirect, indexed 0017H 0000H CPU special-function registers (SFRs); lower register file Direct, indirect, indexed 5.2.4.
8XC196NP, 80C196NU USER’S MANUAL Subroutines may be nested. That is, each subroutine may call other subroutines. The CPU PUSHes the contents of the program counter onto the stack each time it executes a subroutine call. The stack grows downward as entries are added. The only limit to the nesting depth is the amount of available memory. As the CPU returns from each nested subroutine, it POPs the address off the top of the stack, and the next return address moves to the top of the stack.
MEMORY PARTITIONS 5.3 WINDOWING Windowing expands the amount of memory that is accessible with direct addressing. Direct addressing can access the lower register file with short, fast-executing instructions. With windowing, direct addressing can also access the upper register file and peripheral SFRs. Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into the lower register file. The 8XC196NP has a single window selection register, while the 80C196NU has two.
8XC196NP, 80C196NU USER’S MANUAL 5.3.1 Selecting a Window The window selection register (Figure 5-5) has two functions. The HLDEN bit (WSR.7) enables and disables the bus-hold protocol (see Chapter 13, “Interfacing with External Memory”); it is unrelated to windowing. The remaining bits select a window to be mapped into the top of the lower register file. Window selection register 1 (Figure 5-6) selects a second window to be mapped into the middle of the 80C196NU’s lower register file.
MEMORY PARTITIONS Address: Reset State: WSR1 (80C196NU) 0015H 00H Window selection 1 (WSR1) register selects a 32- or 64-byte segment of the upper register file or peripheral SFRs to be windowed into the middle of the lower register file, below any window selected by the WSR. 7 — 80C196NU Bit Number 0 W6 W5 W4 Bit Mnemonic W3 W2 W1 W0 Function 7 — Reserved; always write as zero. 6:0 W6:0 Window Selection These bits specify the window size and window number.
8XC196NP, 80C196NU USER’S MANUAL Table 5-9.
MEMORY PARTITIONS Table 5-10.
8XC196NP, 80C196NU USER’S MANUAL Table 5-11. Windowed Base Addresses Window Size WSR Windowed Base Address (Base Address in Lower Register File) WSR1 Windowed Base Address (Base Address in Lower Register File) 80C196NU Only 32-byte 00E0H 0060H 64-byte 00C0H 0040H 128-byte 0080H — Appendix C includes a table of the windowable SFRs with the window selection register values and direct addresses for each window size.
MEMORY PARTITIONS 5.3.2.4 Unsupported Locations Windowing Example (8XC196NP Only) Assume that you wish to access location 1FE7H (the EP_PIN register, a memory-mapped SFR) with direct addressing through a 128-byte window. This location is in the range of addresses (1FE0–1FFFH) that cannot be windowed. Although you could set up the window by writing 1FH to the WSR, reading this location through the window would return FFH (all ones) and writing to it would not change the contents.
8XC196NP, 80C196NU USER’S MANUAL public function2 extrn ?WSR wsr sp equ equ 14h:byte 18h:word oseg var1: var2: var3: dsw dsw dsw 1 1 1 cseg function2: push wsr ldb wsr, #?WSR ;Prolog code for wsr ;Prolog code for wsr add var1, var2, var3 ; ; ; ldb wsr, [sp] add sp, #2 ret ;Epilog code for wsr ;Epilog code for wsr end ****************************** The following is an example of a linker invocation to link and locate the modules and to determine the proper windowing. RL196 MOD1.OBJ, MOD2.
MEMORY PARTITIONS This listing shows the disassembled code: 2080H 2082H 2085H 2089H 208CH 2090H 2091H 2093H 2096H 209AH 209DH 20A1H ;C814 ;B14814 ;44E4E2E0 ;B21814 ;65020018 ;F0 ;C814 ;B14814 ;44EAE8E6 ;B21814 ;65020018 ;F0 | | | | | | | | | | | | PUSH LDB ADD LDB ADD RET PUSH LDB ADD LDB ADD RET WSR WSR,#48H E0H,E2H,E4H WSR,[SP] SP,#02H WSR WSR,#48H E6H,E8H,EAH WSR,[SP] SP,#02H The C compiler can also take advantage of this feature if the “windows” switch is enabled.
8XC196NP, 80C196NU USER’S MANUAL 5.4 REMAPPING INTERNAL ROM (83C196NP ONLY) The 83C196NP’s 4 Kbytes of ROM are located in FF2000–FF2FFFH. By using the REMAP bit (CCB1.2) and the EA# input, you can also access these locations in external memory (page 0FH or page 00H). The REMAP bit is loaded from CCB1 upon leaving reset and cannot be changed until the next reset. Tie EA# low to access external memory or tie it high to access the on-chip ROM.
MEMORY PARTITIONS 5.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES This section describes how the device fetches instructions and accesses data in the 1-Mbyte and 64-Kbyte modes. When the device leaves reset, the MODE64 bit (CCB1.1) selects the 1-Mbyte or 64-Kbyte mode. The mode cannot be changed until the next reset. NOTE The 8XC196NP and 80C196NU have two major differences concerning code and data fetches. The 8XC196NP’s prefetch queue is four bytes, while the 80C196NU’s is eight bytes.
8XC196NP, 80C196NU USER’S MANUAL For nonextended instructions, the EP_REG register provides the page number. Data and constants in this page are called near data and near constants. NOTE The 8XC196NP allows you to change the value of EP_REG to control which memory page a nonextended instruction accesses. However, software tools require that EP_REG be equal to 00H. The 80C196NU forces all nonextended data accesses to page 00H. You cannot use EP_REG to change pages.
MEMORY PARTITIONS 5.5.3 Code Fetches in the 1-Mbyte Mode CCR1.1 (the MODE64 bit) controls whether the device operates in 1-Mbyte or 64-Kbyte mode. CCR1 is loaded with the contents of CCB1 at reset. When MODE64 is clear, the device operates in 1-Mbyte mode. In this mode, code can execute from any page in the 1-Mbyte address space. An extended jump, branch, or call instruction across pages changes the EPC value to the destination page. For example, assume that code is executing from page FFH.
8XC196NP, 80C196NU USER’S MANUAL Code fetches are from external memory or internal memory, depending on the device, the memory location, and the value of the EA# input. 80C196NU: Code executes from page 0FH in external memory. (The 80C196NU has no EA# input.) 80C196NP: For devices without internal nonvolatile memory, EA# must be tied low, and code executes only from page 0FH in external memory. 83C196NP: Code in all locations except FF2000–FF2FFFH executes from external memory.
MEMORY PARTITIONS Data accesses to 002000–002FFFH depend on the REMAP bit and the EA# input: • If remapping is disabled (CCB1.2 = 0), accesses are external. • If remapping is enabled (CCB1.2 = 1), accesses depend on EA#: — If EA# is low, accesses are external (REMAP is ignored). — If EA# is high, accesses are to the internal ROM. 5.6 MEMORY CONFIGURATION EXAMPLES This section provides examples of memory configurations for both 64-Kbyte and 1-Mbyte mode.
8XC196NP, 80C196NU USER’S MANUAL 83C196NP only: Locations FF2000–FF2FFFH, which store code and special-purpose memory, are implemented by internal ROM. Data accesses to locations FF2000–FF2FFFH are directed to the flash memory if EA# is low and to internal ROM if EA# is high. Locations FF2000–FF2FFFH can be remapped to page 00H by setting the REMAP bit (CCB1.2). An access to the remapped area, 002000–002FFFH, is directed to ROM if EA# is high and to external memory if EA# is low.
MEMORY PARTITIONS 5.6.2 Example 2: A 64-Kbyte System with Additional Data Storage Figure 5-10 shows another system designed for operation in the 64-Kbyte mode. Code executes from page FFH only. This system is the same as the example in “Example 1: Using the 64-Kbyte Mode” on page 5-27, but with additional RAM. The 64-Kbyte RAM stores near data in page 00H. The 128-Kbyte RAM stores far data in pages 01H and 02H. Table 5-13 lists the memory addresses. (For memory map details, see Table 5-1 on page 5-4.
8XC196NP, 80C196NU USER’S MANUAL Table 5-13.
MEMORY PARTITIONS 5.6.3 Example 3: Using 1-Mbyte Mode Figure 5-11 shows a system designed for operation in the 1-Mbyte mode. In this mode, code can execute from any page in the 1-Mbyte memory space. The system uses both 8-bit and 16-bit buses and uses the write-strobe mode. (See Chapter 13, “Interfacing with External Memory.”) The 32K×8 RAM stores near data in the upper half of page 00H. The 32K×16 RAM stores far data in page 01H.
8XC196NP, 80C196NU USER’S MANUAL Table 5-14.
6 Standard and PTS Interrupts
CHAPTER 6 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It discusses the three special interrupts and the four PTS modes, two of which are used with the EPA to produce pulse-width modulated (PWM) outputs. It also explains interrupt programming and control. 6.
8XC196NP, 80C196NU USER’S MANUAL Interrupt Pending or PTSSRV Bit Set NMI Pending ? Yes No No INT_MASK.x = 1? Return Yes PTS Enabled? No Yes PTSSEL.x Bit = 1? Priority Encoder Highest Priority Interrupt Priority Encoder Yes Highest Priority PTS Interrupt Reset INT_PEND.x Bit Execute 1 PTS Cycle (Microcoded) Decrement PTSCOUNT No Return No Yes Return No Interrupts Enabled ? Yes PTSCOUNT = 0? Yes Clear PTSSEL.x Bit Set PTSSRV.x Bit PTSSRV.x = 1? Reset PTSSRV.
STANDARD AND PTS INTERRUPTS Figure 6-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” represents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both the INT_PEND and INT_PEND1 registers. 6.2 INTERRUPT SIGNALS AND REGISTERS Table 6-1 describes the external interrupt signals and Table 6-2 describes the control and status registers for both the interrupt controller and PTS. Table 6-1. Interrupt Signals Port Pin P2.2 P2.4 P3.6 P3.
8XC196NP, 80C196NU USER’S MANUAL Table 6-2. Interrupt and PTS Control and Status Registers (Continued) Mnemonic Address Description INT_PEND 0009H Interrupt Pending Registers INT_PEND1 0012H The bits in this register are set by hardware to indicate that an interrupt is pending. PSW No direct access Processor Status Word This register contains one bit that globally enables or disables servicing of all maskable interrupts and another that enables or disables the PTS.
STANDARD AND PTS INTERRUPTS Table 6-3.
8XC196NP, 80C196NU USER’S MANUAL 6.3.1.3 NMI The external NMI pin generates a nonmaskable interrupt for implementation of critical interrupt routines. NMI has the highest priority of all the prioritized interrupts. It is passed directly from the transition detector to the priority encoder, and it vectors indirectly through location FF203EH. The NMI pin is sampled during phase 2 (CLKOUT high) and is latched internally.
STANDARD AND PTS INTERRUPTS rupt if PTSSEL.5 is set. The interrupt vectors through FF204AH, but the corresponding end-ofPTS interrupt vectors through FF200AH, the standard SIO transmit interrupt vector. When the end-of-PTS interrupt vectors to the interrupt service routine, hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine should reinitialize the PTSCB, if required, and set the appropriate PTSSEL bit to re-enable PTS interrupt service. 6.
8XC196NP, 80C196NU USER’S MANUAL 6.4.2 Calculating Latency The maximum latency occurs when the interrupt request occurs too late for acknowledgment following the current instruction. The following worst-case calculation assumes that the current instruction is not a protected instruction. To calculate latency, add the following terms: • Time for the current instruction to finish execution (4 state times).
STANDARD AND PTS INTERRUPTS 1-Mbyte Mode 4 3 2 1 39 15 3 12 64-Kbyte Mode 4 3 2 1 39 11 2 12 Call is Forced If Stack External Execution Ending Instruction "NORML" End "NORML" 6 6 "PUSHA" If Stack External Interrupt Routine Interrupt Interrupt Pending Bit Response Time Set Cleared 1-Mbyte Mode 61 State Times 64-Kbyte Mode 56 State Times A0261-02 Figure 6-2. Standard Interrupt Response Time 6.4.2.
8XC196NP, 80C196NU USER’S MANUAL Table 6-4.
STANDARD AND PTS INTERRUPTS Address: Reset State: PTSSEL 0004H 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
8XC196NP, 80C196NU USER’S MANUAL Address: Reset State: INT_MASK 0008H 00H The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the stack and POPF or POPA restores it.
STANDARD AND PTS INTERRUPTS Address: Reset State: INT_MASK1 0013H 00H The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
8XC196NP, 80C196NU USER’S MANUAL SERIAL_RI_ISR: PUSHA LDB INT_MASK1, #01000000B EI ; ; ; ; Save PSW, INT_MASK, INT_MASK1, & WSR (this disables all interrupts) Enable EXTINT3 only Enable interrupt servicing ; Service the RI interrupt POPA ; Restore PSW, INT_MASK, INT_MASK1, & ; WSR registers RET CSEG AT 0FF200CH DCW LSW SERIAL_RI_ISR ; fill in interrupt table ; LSW is a compiler directive that means ; least-significant word of vector address END Note that location FF200CH in the interrupt vector tab
STANDARD AND PTS INTERRUPTS 6. At the end of the service routine, the POPA instruction restores the original contents of the PSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to these registers during the interrupt service routine are overwritten. Because interrupt calls cannot occur immediately following a POPA instruction, the last instruction (RET) will execute before another interrupt call can occur.
8XC196NP, 80C196NU USER’S MANUAL Address: Reset State: INT_PEND 0009H 00H When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. 7 0 EPA0 RI TI EXTINT1 Bit Number 7:3 1:0 EXTINT0 — OVRTM2 Function Any set bit indicates that the corresponding interrupt is pending.
STANDARD AND PTS INTERRUPTS Address: Reset State: INT_PEND1 0012H 00H When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. 7 0 NMI EXTINT3 EXTINT2 Bit Number 7:0 OVR2_3 OVR0_1 EPA3 EPA2 EPA1 Function Any set bit indicates that the corresponding interrupt is pending.
8XC196NP, 80C196NU USER’S MANUAL The address of the first (lowest) PTSCB byte is stored in the PTS vector table in special-purpose memory (see “Special-purpose Memory” on page 5-6). Figure 6-9 shows the PTSCB for each PTS mode. Unused PTSCB bytes can be used as extra RAM. NOTE The PTSCB must be located in the internal register file. The location of the first byte of the PTSCB must be aligned on a quad-word boundary (an address evenly divisible by 8).
STANDARD AND PTS INTERRUPTS Address: Reset State: PTSSRV 0006H 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
8XC196NP, 80C196NU USER’S MANUAL Address: PTSPCB + 1 PTSCON The PTS control (PTSCON) register selects the PTS mode and sets up control functions for that mode. 7 0 M2 Bit Number 7:5 M1 † M0 Bit Mnemonic M2:0 † † † † Function PTS Mode These bits select the PTS mode: M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 block transfer reserved PWM toggle or remap reserved single transfer reserved reserved reserved † The function of this bit depends upon which mode is selected.
STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).
8XC196NP, 80C196NU USER’S MANUAL PTS Single Transfer Mode Control Block (Continued) Register PTSCON Location PTSCB + 1 Function PTS Control Bits M2:0 PTS Mode M2 1 BW M1 0 M0 0 single transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer SU† Update PTSSRC 0 = reload original PTS source address after each byte or word transfer 1 = retain current PTS source address after each byte or word transfer DU† Update PTSDST 0 = reload original PTS destination address after each byte or word
STANDARD AND PTS INTERRUPTS Table 6-5. Single Transfer Mode PTSCB Unused Unused PTSDST (HI) = 60H PTSDST (LO) = 00H PTSSRC (HI) = 00H PTSSRC (LO) = 20H PTSCON = 85H (Mode = 100, BW = 0, SI/SU = 0, DI/DU = 1) PTSCOUNT = 09H 6.6.4 Block Transfer Mode In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from one memory location to another. See AP-445, 8XC196KR Peripherals: A User’s Point of View, for application examples with code.
8XC196NP, 80C196NU USER’S MANUAL PTS Block Transfer Mode Control Block In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).
STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block (Continued) Register PTSCON Location PTSCB + 1 Function PTS Control Bits M2:0 PTS Mode These bits select the PTS mode: M2 0 BW M1 0 M0 0 block transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer SU Update PTSSRC 0 = reload original PTS source address after each block transfer is complete 1 = retain current PTS source address after each block transfer is complete DU Update PTSDST 0 = reload original PTS destinatio
8XC196NP, 80C196NU USER’S MANUAL 6.6.5 PWM Modes The PWM toggle and PWM remap modes are designed for use with the event processor array (EPA) to generate pulse-width modulated (PWM) output signals. These modes can also be used with an interrupt signal from any other source. The PWM toggle mode uses a single EPA channel to generate a PWM signal. The PWM remap mode uses two EPA channels, but it can generate signals with duty cycles closer to 0% or 100% than are possible with the PWM toggle mode.
STANDARD AND PTS INTERRUPTS Output Value 1 on off on off 0 0 T1 On-time = T1 T2 T2 + T1 time Off-time = T2 - T1 A0263-02 Figure 6-14. A Generic PWM Waveform The PWM modes do not use a PTSCOUNT register to specify the number of consecutive PTS cycles. To stop producing the PWM output, first clear the PTSSEL.x bit to disable PTS service for the interrupt and then use the interrupt service routine to reconfigure the EPA channel. 6.6.5.
8XC196NP, 80C196NU USER’S MANUAL Table 6-8. PWM Toggle Mode PTSCB PTSCONST2 (HI) = T2 – T1 (HI) PTSCONST2 (LO) = T2 – T1 (LO) PTSCONST1 (HI) = T1 (HI) PTSCONST1 (LO) = T1 (LO) PTSPTR1 (HI) = 1FH PTSPTR1 (LO) = 82H PTSCON = 43H (Mode = 010, TMOD = 1, TBIT = 1) Unused 5. Configure P1.0 to serve as the EPA0 output. — Clear P1_DIR.0 (selects output). — Set P1_MODE.0 (selects the EPA0 special-function signal). — Set P1_REG.0 (initializes the output to “1”). 6. Set up EPA0.
STANDARD AND PTS INTERRUPTS PTS PWM Toggle Mode Control Block In PWM toggle mode, the PTS uses a single EPA channel to generate a pulse-width modulated (PWM) output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the PWM off-time (PTSCONST2), the address pointer (PTSPTR1), and a control register (PTSCON).
8XC196NP, 80C196NU USER’S MANUAL PTS PWM Toggle Mode Control Block (Continued) Register PTSCON Location PTSCB + 1 Function PTS Control Bits M2:0 PTS Mode These bits specify the PTS mode: M2 0 TMOD M1 1 M0 0 PWM Toggle Mode Select 1 = PWM toggle mode TBIT Toggle Bit Initial Value Defines the initial value of TBIT.
STANDARD AND PTS INTERRUPTS Start EPA No Timer Match ? Yes Toggle Output PTS PTS Cycle =1 =0 TBIT EPA0_TIME = EPA0_TIME + (T2 - T1) EPA0_TIME = EPA0_TIME + T1 Toggle TBIT A2552-02 Figure 6-16. EPA and PTS Operations for the PWM Toggle Mode Example You can modify the duty cycle without interrupting the PWM operation.
8XC196NP, 80C196NU USER’S MANUAL When the next timer match occurs, the PTS cycle (Figure 6-16) increments EPA0_TIME by T1 (if TBIT is zero (output = 0)) or T2 – T1 (if TBIT is one (output = 1)). (Note that although the values of the EPA0 output and TBIT are the same in this example, these two values are unrelated. To establish the initial value of the output, set or clear P1_REG.x.) The PWM toggle mode has the advantage of using only one EPA channel.
STANDARD AND PTS INTERRUPTS Table 6-9. PWM Remap Mode PTSCB 4. PTSCB0 for EPA0 PTSCB1 for EPA1 Unused Unused Unused Unused PTSCONST1 (HI) = T2 (HI) PTSCONST1 (HI) = T2 (HI) PTSCONST1 (LO) = T2 (LO) PTSCONST1 (LO) = T2 (LO) PTSPTR1 (HI) = 1FH (EPA0_TIME, HI) PTSPTR1 (HI) = 1FH (EPA1_TIME, HI) PTSPTR1 (LO) = 82H (EPA0_TIME, LO) PTSPTR1 (LO) = 86H (EPA1_TIME, LO) PTSCON = 40H (Mode = 010, TMOD = 0) PTSCON = 40H (Mode = 010, TMOD = 0) Unused Unused Set up EPA0 and EPA1.
8XC196NP, 80C196NU USER’S MANUAL PTS PWM Remap Mode Control Block In PWM remap mode, the PTS uses two EPA channels to generate a pulse-width modulated (PWM) output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the address pointer (PTSPTR1), and a control register (PTSCON).
STANDARD AND PTS INTERRUPTS PTS PWM Remap Mode Control Block (Continued) Register PTSCON Location PTSCB + 1 Function PTS Control Bits M2:0 PTS Mode These bits specify the PTS mode: M2 0 M1 1 M0 0 PWM TMOD Remap Mode Select TBIT Toggle Bit Initial Value 0 = PWM remap mode Defines the initial value of TBIT. 1 = selects initial value as one 0 = selects initial value as zero NOTE: In PWM remap mode, the TBIT value is not used; PTSCONST1 is always added to the PTSPTR1 value.
8XC196NP, 80C196NU USER’S MANUAL Start EPA No Timer Match ? Yes If EPA0, set the output If EPA1, clear the output PTS Cycle PTS If EPA0: EPA0_TIME = EPA0_TIME + T2 If EPA1: EPA1_TIME = EPA1_TIME + T2 Toggle TBIT (TBIT is not used) A2553-01 Figure 6-18. EPA and PTS Operations for the PWM Remap Mode Example You can change the duty cycle by changing the time that the output is high and keeping the period constant.
7 I/O Ports
CHAPTER 7 I/O PORTS I/O ports provide a mechanism to transfer information between the device and the surrounding system circuitry. They can read system status, monitor system operation, output device status, configure system options, generate control signals, provide serial communication, and so on. Their usefulness in an application is limited only by the number of I/O pins available and the imagination of the engineer. 7.
8XC196NP, 80C196NU USER’S MANUAL Table 7-2. Bidirectional Port Pins Port Pin Special-function Signal(s) Special-function Signal Type Associated Peripheral P1.0 EPA0 I/O EPA P1.1 EPA1 I/O EPA P1.2 EPA2 I/O EPA P1.3 EPA3 I/O EPA P1.4 T1CLK I Timer 1 P1.5 T1DIR I Timer 1 P1.6 T2CLK I Timer 2 P1.7 T2DIR I Timer 2 P2.0 TXD O SIO P2.1 RXD I/O SIO P2.2 EXTINT0 I P2.3 BREQ# O Bus controller P2.4 EXTINT1 I Interrupts Interrupts P2.
I/O PORTS Table 7-3. Bidirectional Port Control and Status Registers Mnemonic Address Description Port x Direction P1_DIR P2_DIR P3_DIR P4_DIR 1FD2H 1FCBH 1FDAH 1FDBH P1_MODE P2_MODE P3_MODE P4_MODE 1FD0H 1FC9H 1FD8H 1FD9H P1_PIN P2_PIN P3_PIN P4_PIN 1FD6H 1FCFH 1FDEH 1FDFH Port x Input P1_REG P2_REG P3_REG P4_REG 1FD4H 1FCDH 1FDCH 1FDDH Port x Data Output Each bit of Px_DIR controls the direction of the corresponding pin.
8XC196NP, 80C196NU USER’S MANUAL In special-function mode (selected by setting Px_MODE.y), SFDIR and SFDATA are input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high impedance. Special-function output signals clear SFDIR; special-function input signals set SFDIR. Table 7-5 is a logic table for special-function operation of these ports.
I/O PORTS Internal Bus Vcc Px_REG 0 SFDATA Q1 1 I/O Pin Px_DIR 0 Q2 SFDIR 1 Vss Px_MODE Sample Latch 150Ω to 200Ω R1 Px_PIN Q D LE Read Port PH1 Clock Vcc Medium Pullup 300ns Delay Q3 RESET# Vcc RESET# Weak Pullup R Q Any Write to Px_MODE Q4 S A0238-04 Figure 7-1.
8XC196NP, 80C196NU USER’S MANUAL Table 7-4. Logic Table for Bidirectional Ports in I/O Mode Configuration Complementary Output Open-drain Output Input Px_MODE 0 0 0 0 Px_DIR 0 0 1 1 SFDIR X X X X SFDATA X X X X Px_REG 0 1 0, 1 (Note 2) 1 Q1 off on off off Q2 on off on, off (Note 2) off Px_PIN 0 1 X (Note 3) high-impedance (Note 4) NOTES: 1. X = Don’t care. 2. If Px_REG is cleared, Q2 is on; if Px_REG is set, Q2 is off. 3.
I/O PORTS 7.2.2 Bidirectional Port Pin Configurations Each bidirectional port pin can be individually configured to operate either as an I/O pin or as a pin for a special-function signal. In the special-function configuration, the signal is controlled by an on-chip peripheral or an off-chip component.
8XC196NP, 80C196NU USER’S MANUAL Table 7-6.
I/O PORTS Table 7-8. Port Pin States After Reset and After Example Code Execution Resulting Pin States† Action or Code Reset LDB Px_DIR, #00011111B Px.7 Px.6 Px.5 Px.4 Px.3 Px.2 Px.1 Px.0 wk1 wk1 wk1 wk1 wk1 wk1 wk1 wk1 1 1 1 wk1 wk1 wk1 wk1 wk1 LDB Px_MODE, #00000000B 1 1 1 HZ1 HZ1 HZ1 HZ1 HZ1 LDB Px_REG, #10010011B 1 0 0 HZ1 0 0 HZ1 HZ1 † wk1 = weakly pulled high, HZ1 = high impedance (actually a “1” with an external pull-up). 7.2.
8XC196NP, 80C196NU USER’S MANUAL P2.7/CLKOUT Following reset, P2.7 carries the strongly driven CLKOUT signal. It is not held high. When P2.7 is configured as CLKOUT, it is always a complementary output. P2.7 A value written to P2_REG.7 is held in a buffer until P2_MODE.7 is cleared, at which time the value is loaded into P2_REG.7. A value read from P2_REG.7 is the value currently in the register, not the value in the buffer. Therefore, any change to P2_REG.7 can be read only after P2_MODE.7 is cleared.
I/O PORTS 7.2.5 Design Considerations for External Interrupt Inputs To configure a port pin that serves as an external interrupt input, you must set the corresponding bits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). However, setting the Px_MODE bit causes the device to set the corresponding interrupt pending bit, indicating an interrupt request. To configure P2.2/EXTINT0, P2.4/EXTINT1, P3.6/EXTINT2, and P3.
8XC196NP, 80C196NU USER’S MANUAL Table 7-10. EPORT Control and Status Registers Mnemonic EP_DIR Address 1FE3H Description EPORT Direction In I/O mode, each bit of EP_DIR controls the direction of the corresponding pin. Clearing a bit configures a pin as a complementary output; setting a bit configures a pin as either an input or an opendrain output. (Open-drain outputs require external pull-ups).
I/O PORTS I/O MUX Internal Bus EP_REG VCC I/O (0) Address MUX Data Extended Code Address (from CPU) Extended Data Address (from CPU) CODE EPC 64K ADR (1) Force Page 00H Q1 DATA EDAR I/O Pin Combinational Logic 1M Data/Address Control (from Bus Controller) MODE64 Control (from CPU) Q2 Mode EP_MODE Direction EP_DIR VSS Sample Latch EP_PIN Q Buffer D LE Read Port PH1 Clock NOTE: Shaded area is unique to the 80C196NU. A3113-01 Figure 7-2. EPORT Block Diagram If EP_MODE.
8XC196NP, 80C196NU USER’S MANUAL The 8XC196NP allows you to change the value of EP_REG to control which memory page a nonextended instruction accesses. However, software tools require that EP_REG be equal to 00H. The 80C196NU forces all nonextended data accesses to page 00H. You cannot use EP_REG to change pages. You can read EP_PIN at any time to determine the value of a pin. When EP_PIN is read, the contents of the sample latch are output onto the internal bus.
I/O PORTS Internal Bus RESET# EP_REG Vcc 0 DATA Address Bit from Address MUX Q1 1 I/O Pin EP_MODE Q2 EP_DIR POWERDOWN# IDLE# HOLD# Vss Sample Latch EP_PIN Q 150Ω to 200Ω R1 Buffer D LE Read Port PH1 Clock Vcc Medium Pullup 300ns Delay Q3 RESET# Vcc Weak Pullup Q4 A0241-02 Figure 7-3.
8XC196NP, 80C196NU USER’S MANUAL 7.3.1.5 Input Mode Input mode is obtained by configuring the pin as an open-drain output (EP_DIR set and EP_MODE clear) and writing a one to EP_REG.x. In this configuration, Q1 and Q2 are both off, allowing an external device to drive the pin. To determine the value of the I/O pin, read EP_PIN.x. Table 7-11 is a logic table for I/O operation and Table 7-12 is a logic table for address mode operation of EPORT. Table 7-11.
I/O PORTS 7.3.2 Configuring EPORT Pins Each EPORT pin can be individually configured to operate either as an extended-address signal or as an I/O pin in one of these modes: • complementary output (output only) • high-impedance input or open-drain output (input, output, or bidirectional) 7.3.2.1 Configuring EPORT Pins for Extended-address Functions The EPORT pins default to their extended-address functions upon reset (see Table B-5 on page B-13).
8XC196NP, 80C196NU USER’S MANUAL 7.3.3 EPORT Considerations This section outlines considerations for using the EPORT pins. 7.3.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold During reset, the EPORT pins are forced to their extended-address functions and are weakly pulled high. During the CCB fetch, FFH is strongly driven onto the pins. This value remains strongly driven until either the pin is configured for I/O or a different extended address is accessed.
I/O PORTS 3. Any nonextended or direct instruction that accesses the register file or the windowable SFRs is always directed internally to these areas, regardless of the page from which code is executing. This effectively maps the register file and windowable SFRs into every page. Extended instructions can access the “mapped over” areas of each page, as shown in the following code example. EST 7.3.3.
8 Serial I/O (SIO) Port
CHAPTER 8 SERIAL I/O (SIO) PORT A serial input/output (SIO) port provides a means for the system to communicate with external devices. This device has a serial I/O (SIO) port that shares pins with port 2. This chapter describes the SIO port and explains how to configure it. Chapter 7, “I/O Ports,” explains how to configure the port pins for their special functions. Refer to Appendix B for details about the signals discussed in this chapter. 8.
8XC196NP, 80C196NU USER’S MANUAL An independent, 15-bit baud-rate generator controls the baud rate of the serial port. Either the internal peripheral clock or T1CLK can provide the clock signal. The baud-rate register (SP_BAUD) selects the clock source and the baud rate. 8.2 SERIAL I/O PORT SIGNALS AND REGISTERS Table 8-1 describes the SIO signals and Table 8-2 describes the control and status registers. Table 8-1. Serial Port Signals Port Pin P2.
SERIAL I/O (SIO) PORT Table 8-2. Serial Port Control and Status Registers (Continued) Mnemonic P1_PIN Address 1FD6H Description Port 1 Pin State If you are using T1CLK (P1.4) as the clock source for the baud-rate generator, you can read P1_PIN.4 to determine the current value of T1CLK. P1_REG 1FD4H Port 1 Output Data To use T1CLK as the clock source for the baud-rate generator, set P1_REG.4. P2_DIR 1FCBH Port 2 Direction This register selects the direction of each port 2 pin. Clear P2_DIR.
8XC196NP, 80C196NU USER’S MANUAL Table 8-2. Serial Port Control and Status Registers (Continued) Mnemonic SP_STATUS Address Description 1FB9H Serial Port Status This register contains the serial port status bits. It has status bits for receive overrun errors (OE), transmit buffer empty (TXE), framing errors (FE), transmit interrupt (TI), receive interrupt (RI), and received parity error (RPE) or received bit 8 (RB8).
SERIAL I/O (SIO) PORT In mode 0, RXD must be enabled for receptions and disabled for transmissions. (See “Programming the Control Register” on page 8-8.) When RXD is enabled, either a rising edge on the RXD input or clearing the receive interrupt (RI) flag in SP_STATUS starts a reception. When RXD is disabled, writing to SBUF_TX starts a transmission. Disabling RXD stops a reception in progress and inhibits further receptions.
8XC196NP, 80C196NU USER’S MANUAL When the serial port is configured for mode 1, 2, or 3, writing to SBUF_TX causes the serial port to start transmitting data. New data placed in SBUF_TX is transmitted only after the stop bit of the previous data has been sent. A falling edge on the RXD input causes the serial port to begin receiving data if RXD is enabled. Disabling RXD stops a reception in progress and inhibits further receptions. (See “Programming the Control Register” on page 8-8.) 8.3.2.
SERIAL I/O (SIO) PORT 8.3.2.2 Mode 2 Mode 2 is the asynchronous, ninth-bit recognition mode. This mode is commonly used with mode 3 for multiprocessor communications. Figure 8-5 shows the data frame used in this mode. It consists of a start bit (0), nine data bits (LSB first), and a stop bit (1). During transmissions, setting the TB8 bit in the SP_CON register before writing to SBUF_TX sets the ninth transmission bit.
8XC196NP, 80C196NU USER’S MANUAL 8.3.2.5 Multiprocessor Communications Modes 2 and 3 are provided for multiprocessor communications. In mode 2, the serial port sets the RI interrupt pending bit only when the ninth data bit is set. In mode 3, the serial port sets the RI interrupt pending bit regardless of the value of the ninth bit. The ninth bit is always set in address frames and always cleared in data frames.
SERIAL I/O (SIO) PORT Address: Reset State: SP_CON 1FBBH 00H The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. For the 80C196NU, it also enables or disables the divide-by-two prescaler.
8XC196NP, 80C196NU USER’S MANUAL Address: Reset State: SP_CON (Continued) 1FBBH 00H The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. For the 80C196NU, it also enables or disables the divide-by-two prescaler.
SERIAL I/O (SIO) PORT Address: Reset State: SP_BAUD 1FBCH 0000H The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate. The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum BAUD_VALUE is 0000H when using the internal clock source (f) and 0001H when using T1CLK.
8XC196NP, 80C196NU USER’S MANUAL CAUTION For mode 0 receptions, the BAUD_VALUE must be 0002H or greater. Otherwise, the resulting data in the receive shift register will be incorrect. The reason for this restriction is that the receive shift register is clocked from an internal signal rather than the signal on TXD. Although these two signals are normally synchronized, the internal signal generates one clock before the first pulse transmitted by TXD and this first clock signal is not synchronized with TXD.
SERIAL I/O (SIO) PORT Table 8-4. SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only) SP_BAUD Register Value† % Error Baud Rate 9600 Mode 0 Mode 1, 2, 3 Mode 0 Mode 1, 2, 3 8A2CH 8145H 0 0.15 †Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud-rate generator. 8.4.4 Enabling the Serial Port Interrupts The serial port has both a transmit interrupt (TI) and a receive interrupt (RI).
8XC196NP, 80C196NU USER’S MANUAL Address: Reset State: SP_STATUS 1FB9H 0BH The serial port status (SP_STATUS) register contains bits that indicate the status of the serial port. 7 0 RPE/RB8 Bit Number 7 RI TI FE Bit Mnemonic RPE/RB8 TXE OE — — Function Received Parity Error/Received Bit 8 RPE is set if parity is disabled (SP_CON.2 = 0) and the ninth data bit received is high. RB8 is set if parity is enabled (SP_CON.2 = 1) and a parity error occurred. Reading SP_STATUS clears this bit.
SERIAL I/O (SIO) PORT The receive interrupt (RI) flag indicates whether an incoming data byte has been received. The transmit interrupt (TI) flag indicates whether a data byte has finished transmitting. These flags also set the corresponding bits in the interrupt pending register. A reception or transmission sets the RI or TI flag in SP_STATUS and the corresponding interrupt pending bit.
9 Pulse-width Modulator
CHAPTER 9 PULSE-WIDTH MODULATOR The pulse-width modulator (PWM) module has three output pins, each of which can output a PWM signal with a fixed frequency and a variable duty cycle. These outputs can be used to drive motors that require an unfiltered PWM waveform for optimal efficiency, or they can be filtered to produce a smooth analog signal.
8XC196NP, 80C196NU USER’S MANUAL 8 Load Buffer PWMx_CONTROL 8 Bufferx 8 CON_REG0.0 (CLK0 Bit) Comparatorx CON_REG0.1 (CLK1 Bit) = RS Flip-flopx R Prescaler 8 Internal Clock Signal –2 –4 00 01 10 11 P4_MODE Q Up Counter S Port 4 Control PWMx Output Overflow P4.x/ PWMx Shared Circuitry A3158-01 Figure 9-2. PWM Block Diagram (80C196NU Only) 9.2 PWM SIGNALS AND REGISTERS Table 9-1 describes the PWM’s signals and Table 9-2 briefly describes the control and status registers. Table 9-1.
PULSE-WIDTH MODULATOR Table 9-2. PWM Control and Status Registers Mnemonic CON_REG0 Address 1FB6H Description PWM Control Register This register controls the clock prescaler. Bit 0 (CLK0) controls the output period of the PWM channels by enabling or disabling the divide-by-two clock prescaler (8XC196NP only). Bits 0 and 1 (CLK0, CLK1) control the output period of the PWM channels by enabling or disabling the divide-by-two or divide-by-four clock prescaler (80C196NU only).
8XC196NP, 80C196NU USER’S MANUAL For the 80C196NU, two bits control the PWM output frequency, CON_REG0.0 (CLK0) and CON_REG0.1 (CLK1). The two bits control the PWM output frequency by enabling or disabling the divide-by-two or divide-by-four clock prescaler. Each control register (PWMx_CONTROL; x = 0, 1, or 2) controls the duty cycle (the pulsewidth stated as a percentage of the period) of the corresponding PWM output.
PULSE-WIDTH MODULATOR Duty Cycle PWM Control Register Value 0% 00H 0 10% 19H 0 50% 80H 0 90% E6H 0 99.6% FFH 0 Output Waveform A0119-02 Figure 9-3. PWM Output Waveforms 9.4 PROGRAMMING THE FREQUENCY AND PERIOD The PWM module provides two selectable, fixed PWM output frequencies for a specified internal operating frequency (f). Table 9-3 shows the PWM output frequencies for common operating frequencies on the 8XC196NP. The value of CON_REG0.
8XC196NP, 80C196NU USER’S MANUAL For the 80C196NU, the PWM module provides three selectable, fixed PWM output frequencies for a specified internal operating frequency (f). Table 9-3 shows the PWM output frequencies for common operating frequencies. The value of bits 0 and 1 in the CON_REG0 register determines the output frequency by enabling or disabling the divide-by-two or divide-by-four clock prescaler.
PULSE-WIDTH MODULATOR Address: Reset State: CON_REG0 1FB6H FEH The control (CON_REG0) register controls the clock prescaler for the three pulse-width modulators (PWM0–PWM2). 7 0 — 8XC196NP — — — — — — CLK0† 7 — 80C196NU Bit Number 0 — — — Bit Mnemonic — — CLK1 CLK0 Function 7:1 (NP) 7:2 (NU) — Reserved; for compatibility with future devices, write zeros to these bits.
8XC196NP, 80C196NU USER’S MANUAL Clock Prescaler Disabled ÷2 Clock Prescaler Enabled PWM x _CON × 4 ----------------------------------------------f Pulsewidth (in µs) = PWM x _CON × 2 ----------------------------------------------f Duty Cycle (in %) = Puls ewidth --------------------------------- × 100 T PW M ÷4 Clock Prescaler† Enabled PWM x _CON × 8 ----------------------------------------------f where: PWMx_CON = 8-bit value to load into the PWMx_CONTROL register Pulsewidth = width of each
PULSE-WIDTH MODULATOR 9.5.1 Sample Calculations For example, assume that the operating frequency equals 25 MHz, the desired period of the PWM output waveform is either 20.48 µs (512 state times) if the divide-by-two prescaler is disabled or 40.96 µs (1,024 state times) if the prescaler is enabled. If PWMx_CONTROL equals 8AH (138 decimal), the pulsewidth is held high for 11.04 µs (and low for 9.44 µs) of the total 20.48 µs period, resulting in a duty cycle of approximately 54%.
8XC196NP, 80C196NU USER’S MANUAL 8XC196 Device PWM Buffer to Make Output Swing Rail to Rail Filter (Passive or Active) Power Amp (Optional) Analog Output (Optional) A2391-01 Figure 9-6. D/A Buffer Block Diagram Figure 9-7 shows a sample circuit used for low output currents (less than 100 µA). Consider temperature and power-supply drift when selecting components for the external D/A circuitry. With proper components, a highly accurate 8-bit D/A converter can be made using the PWM.
10 Event Processor Array (EPA)
CHAPTER 10 EVENT PROCESSOR ARRAY (EPA) Control applications often require high-speed event control. For example, the controller may need to periodically generate pulse-width modulated outputs or an interrupt. In another application, the controller may monitor an input signal to determine the status of an external device. The event processor array (EPA) was designed to reduce the CPU overhead associated with these types of event control.
8XC196NP, 80C196NU USER’S MANUAL Timer-Counter Unit TIMER1 TIMER2 EPA0 Capture/Compare Channel 0 EPA0 Interrupt EPA1 Capture/Compare Channel 1 EPA1 Interrupt EPA2 Capture/Compare Channel 2 EPA2 Interrupt EPA3 Capture/Compare Channel 3 EPA3 Interrupt A2352-02 Figure 10-1. EPA Block Diagram 10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS Table 10-1 describes the EPA and timer/counter input and output signals. Each signal is multiplexed with a port pin as shown in the first column.
EVENT PROCESSOR ARRAY (EPA) Table 10-2. EPA Control and Status Registers Mnemonic EPA_MASK Address 1F9CH Description EPA Mask Four bits (OVR0, OVR1, OVR2, and OVR3) in this 8-bit register enable and disable (mask) the individual capture overrun interrupt sources associated with capture/compare channels EPA3:0. EPA_PEND 1F9EH EPA Pending Four bits (OVR0, OVR1, OVR2, and OVR3) in this 8-bit register indicate an overrun status for the associated capture/compare channels, EPA3:0.
8XC196NP, 80C196NU USER’S MANUAL Table 10-2. EPA Control and Status Registers (Continued) Mnemonic P1_MODE Address 1FD0H Description Port 1 Mode Each bit of P1_MODE controls whether the corresponding pin functions as a standard I/O port pin or as a special-function signal. Setting a bit configures a pin as a special-function signal; clearing a bit configures a pin as a standard I/O port pin.
EVENT PROCESSOR ARRAY (EPA) 10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW The EPA has two 16-bit up/down timer/counters, timer 1 and timer 2, which can be clocked internally or externally. Each is called a timer if it is clocked internally and a counter if it is clocked externally. Figure 10-2 illustrates the timer/counter structure. T2CONTROL.2:0 † 3 Timer 2 T2CLK f/4 Prescaler Module Quadrature Count Clock Overflow Timer 1 Overflow OVRTM Interrupt T2DIR T2CONTROL.
8XC196NP, 80C196NU USER’S MANUAL The timer/counters can be used as time bases for input captures, output compares, and programmed interrupts (software timers). When a counter increments from FFFEH to FFFFH or decrements from 0001H to 0000H, the counter-overflow interrupt pending bit is set. This bit can optionally cause an interrupt.
EVENT PROCESSOR ARRAY (EPA) Increment 8XC196 Device Decrement PH2 X PH1 Y TxCLK Optical Reader TxDIR D Q D Q D Q X_internal D Q D Q D Q Y_internal A0268-02 Figure 10-3. Quadrature Mode Interface Table 10-3.
8XC196NP, 80C196NU USER’S MANUAL CLKOUT PH2 TxCLK TxDIR COUNT x x+1 x +2 x +3 x +4 x +5 x +6 x +5 x +4 x +3 x +2 x +1 A0269-02 Figure 10-4. Quadrature Mode Timing and Count 10.4 EPA CHANNEL FUNCTIONAL OVERVIEW The EPA has four programmable capture/compare channels that can perform the following tasks.
EVENT PROCESSOR ARRAY (EPA) Timer/Counter Unit External clocking (Tx CLK) with up to 6-bit prescaler Quadrature clocking through Tx CLK and Tx DIR Internal clocking with up to 6-bit prescaler TIMER1 Clock on TIMER1 overflow TIMER2 Capture Overrun EPA Capture/Compare Channel x OVRx Interrupt Capture Buffer EPAx_TIME EPA Pin Compare Bus TGL EPA Interrupt EPAx_CON Overwrite Mode Control †Remap Reset Timer Mode Selection † EPA1 and 3 only. If enabled for EPA1, EPA0 shares the EPA1 pin.
8XC196NP, 80C196NU USER’S MANUAL TIMERx Event Occurs at EPA Pin Capture Buffer EPA Interrupt Pending Bit Set EPAx_TIME Read-out Time Value A2458-02 Figure 10-6. EPA Simplified Input-capture Structure If a third event occurs before the CPU reads the event-time register, the overwrite bit (EPAx_CON.0) determines how the EPA will handle the event. If the bit is clear, the EPA ignores the third event. If the bit is set, the third event time overwrites the second event time in the capture buffer.
EVENT PROCESSOR ARRAY (EPA) Table 10-4. Action Taken when a Valid Edge Occurs Overwrite Bit (EPAx_CON.0) Status of Capture Buffer & EPAx_TIME 0 empty Edge is captured and event time is loaded into the capture buffer and EPAx_TIME register. 0 full New data is ignored — no capture, EPA interrupt, or transfer occurs; OVRx interrupt pending bit is set. 1 empty Edge is captured and event time is loaded into the capture buffer and EPAx_TIME register.
8XC196NP, 80C196NU USER’S MANUAL 10.4.1.2 Preventing EPA Overruns Any one of the following methods can be used to prevent or recover from an EPA overrun situation. • Clear EPAx_CON.0 When the overwrite bit (EPAx_CON.0) is zero, the EPA does not consider the captured edge until the EPAx_TIME register is read and the data in the capture buffer is transferred to EPAx_TIME.
EVENT PROCESSOR ARRAY (EPA) The maximum output frequency depends upon the total interrupt latency and the interrupt-service execution times used by your system. As additional EPA channels and the other functions of the microcontroller are used, the maximum PWM frequency decreases because the total interrupt latency and interrupt-service execution time increases.
8XC196NP, 80C196NU USER’S MANUAL The maximum output frequency depends upon the total interrupt latency and interrupt-service execution time. As additional EPA channels and the other functions of the microcontroller are used, the maximum PWM frequency decreases because the total interrupt latency and interrupt-service execution time increases.
EVENT PROCESSOR ARRAY (EPA) 10.4.2.4 Generating the Highest-speed PWM Output You can generate a highest-speed, pulse-width modulated output with a pair of EPA channels and a dedicated timer/counter. The first channel toggles the output when the timer value matches EPAx_TIME, and at some later time, the second channel toggles the output again and resets the timer/counter. This restarts the cycle. No interrupts are required, resulting in the highest possible speed.
8XC196NP, 80C196NU USER’S MANUAL Address: Reset State: T1CONTROL 1F90H 00H The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
EVENT PROCESSOR ARRAY (EPA) Address: Reset State: T2CONTROL 1F94H 00H The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
8XC196NP, 80C196NU USER’S MANUAL 10.5.3 Programming the Capture/Compare Channels The EPAx_CON register controls the function of its assigned capture/compare channel. The registers for EPA0 and EPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit (RM), which is used to enable and disable remapping for high-speed PWM generation (see “Generating a High-speed PWM Output” on page 10-14).
EVENT PROCESSOR ARRAY (EPA) Address: Reset State: EPAx_CON x = 0–3 Table 10-2 on page 10-3 00H The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
8XC196NP, 80C196NU USER’S MANUAL Address: Reset State: EPAx_CON (Continued) x = 0–3 Table 10-2 on page 10-3 00H The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
EVENT PROCESSOR ARRAY (EPA) Address: Reset State: EPAx_CON (Continued) x = 0–3 Table 10-2 on page 10-3 00H The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
8XC196NP, 80C196NU USER’S MANUAL 10.6 ENABLING THE EPA INTERRUPTS The EPA generates four individual event interrupts, EPA3:0, from the four capture/compare channels and two timer interrupts, OVRTM1 and OVRTM2, from timer 1 and timer 2. These interrupts are directly mapped into the two 8-bit interrupt pending registers (INT_PEND and INT_PEND1). The four separate capture overrun interrupts from EPA3:0 are multiplexed and mapped into two bits in INT_PEND1.
EVENT PROCESSOR ARRAY (EPA) Address: Reset State: EPA_PEND† 1F9EH AAH When hardware detects a pending EPA3:0 overrun interrupt (OVR3:0), it sets the corresponding bit in the EPA interrupt pending (EPA_PEND) register. OVR0 and OVR1 are multiplexed to share one bit (OVR0_1) in the INT_PEND1 register. Similarly, OVR2 and OVR3 are multiplexed to share another bit (OVR2_3) in the INT_PEND1 register. 7 0 — OVR3 — OVR2 Bit Number — OVR1 — Function 7, 5, 3, 1 Reserved. These bits are undefined.
8XC196NP, 80C196NU USER’S MANUAL 10.8 PROGRAMMING EXAMPLES FOR EPA CHANNELS The three programming examples provided in this section demonstrate the use of the EPA channel for a compare event, for a capture event, and for generation of a PWM signal. The programs demonstrate the detection of events by a polling scheme, by interrupts, and by the PTS. All three examples were created using ApBUILDER, an interactive application program available through Intel Literature Fulfillment.
EVENT PROCESSOR ARRAY (EPA) void poll_epa0() { if(checkbit(int_pend, EPA0_INT_BIT)) { /* Insert user code for event channel 0 here. */ /* Since this event is absolute and re-enabled, no polling is neccessary.*/ clrbit(int_pend, EPA0_INT_BIT); } } void main(void) { /* Initialize the timers before using the epa */ init_timer1(); init_epa0(); /* EPA events can be serviced by polling int_pend or epa_pend. */ while(1) { poll_epa0(); } } 10.8.
8XC196NP, 80C196NU USER’S MANUAL time_value = epa0_time; /* must read to prevent overrun */ } void init_timer1() { t1control = COUNT_ENABLE ¦ COUNT_UP ¦ CLOCK_INTERNAL ¦ DIVIDE_BY_1; } void main(void) { unsigned int time_value; /* Initialize the timers and interrupts before using the EPA */ init_timer1(); init_epa0(); enable(); /* Globally enable interrupts */ while(1); /* loop forever, wait for interrupts to occur */ } 10.8.
EVENT PROCESSOR ARRAY (EPA) void Init_PWM_toggle_PTS3(void) { disable(); /* disable all interrupts */ disable_pts(); /* disable the PTS interrupts */ PWM_toggle_CB_3.constant2 PWM_toggle_CB_3.constant1 PWM_toggle_CB_3.pts_ptr PWM_toggle_CB_3.ptscon = = = = 127; 127; (void *)&EPA0_TIME; 0x42; /* Sample code that could be used to generate a PWM with an EPA channel.
11 Minimum Hardware Considerations
CHAPTER 11 MINIMUM HARDWARE CONSIDERATIONS The 8XC196NP and 80C196NU have several basic requirements for operation within a system. This chapter describes options for providing the basic requirements and discusses other hardware considerations. 11.1 MINIMUM CONNECTIONS Table 11-1 lists the signals that are required for the device to function and Figure 11-1 shows the connections for a minimum configuration. Table 11-1.
8XC196NP, 80C196NU USER’S MANUAL Table 11-1. Minimum Required Signals (Continued) Signal Name XTAL1 Type I Description Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator, internal phase-locked loop circuitry (80C196NU), and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1.
MINIMUM HARDWARE CONSIDERATIONS (Note 1) 20 pF VCC 0.01 µF 20 pF XTAL2 VCC (Note 2) XTAL1 RESET# VCC + (NP Only) VSS 4.7 µF EA# NMI (Note 3) RPD VCC 8XC196 Device + .22 µF READY PLLEN1 (NU Only) BHE# RD# WR# ONCE Bus Control (Note 4) INST ALE PLLEN2 (NU Only) Notes: 1. See the datasheet for the oscillator frequency range (FOSC) and the crystal manufacturer's datasheet for recommended load capacitors. 2. The number of VCC and VSS pins varies with package type (see datasheet).
8XC196NP, 80C196NU USER’S MANUAL 11.2 APPLYING AND REMOVING POWER When power is first applied to the device, RESET# must remain continuously low for at least one state time after the power supply is within tolerance and the oscillator/clock has stabilized; otherwise, operation might be unpredictable. Similarly, when powering down a system, RESET# should be brought low before VCC is removed; otherwise, an inadvertent write to an external location might occur.
MINIMUM HARDWARE CONSIDERATIONS Multilayer printed circuit boards with separate VCC and ground planes also help to minimize noise. For more information on noise protection, refer to AP-125, Designing Microcontroller Systems for Noisy Environments and AP-711, EMI Design Techniques for Microcontrollers in Automotive Applications. 11.4 THE ON-CHIP OSCILLATOR CIRCUITRY The on-chip oscillator circuit (Figure 11-3) consists of a crystal-controlled, positive reactance oscillator.
8XC196NP, 80C196NU USER’S MANUAL Figure 11-4 shows the connections between the external crystal and the device. When designing an external oscillator circuit, consider the effects of parasitic board capacitance, extended operating temperatures, and crystal specifications. Consult the manufacturer’s datasheet for performance specifications and required capacitor values. With high-quality components, 20 pF load capacitors (CL) are usually adequate for frequencies above 1 MHz.
MINIMUM HARDWARE CONSIDERATIONS 11.5 USING AN EXTERNAL CLOCK SOURCE To use an external clock source, apply a clock signal to XTAL1 and let XTAL2 float (Figure 11-5). To ensure proper operation, the external clock source must meet the minimum high and low times (TXHXX and TXLXX) and the maximum rise and fall transition times (TXLXH and TXHXL) (Figure 11-6).
8XC196NP, 80C196NU USER’S MANUAL 11.6 RESETTING THE DEVICE Reset forces the device into a known state. As soon as RESET# is asserted, the I/O pins, the control pins, and the registers are driven to their reset states. (Table B-5 on page B-13 lists the reset states of the pins. See Table C-2 on page C-2 for the reset values of the SFRs.) The device remains in its reset state until RESET# is deasserted.
MINIMUM HARDWARE CONSIDERATIONS The following events will reset the device (see Figure 11-8): • an external device pulls the RESET# pin low • the CPU issues the reset (RST) instruction • the CPU issues an idle/powerdown (IDLPD) instruction with an illegal key operand The following paragraphs describe each of these reset methods in more detail.
8XC196NP, 80C196NU USER’S MANUAL The simplest way to reset the device is to insert a capacitor between the RESET# pin and V SS, as shown in Figure 11-9. The device has an internal pull-up resistor (RRST) shown in Figure 11-8. RESET# should remain asserted for at least one state time after VCC and XTAL1 have stabilized and met the operating conditions specified in the datasheet. A capacitor of 4.7 µF or greater should provide sufficient reset time, as long as VCC rises quickly. RESET# + 4.
MINIMUM HARDWARE CONSIDERATIONS 11.6.2 Issuing the Reset (RST) Instruction The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times. It also clears the processor status word (PSW), sets the extended and master program counters (EPC/PC) to FF2080H, and resets the special function registers (SFRs). See Table C-2 on page C-2 for the reset values of the SFRs. 11.6.
12 Special Operating Modes
CHAPTER 12 SPECIAL OPERATING MODES The 8XC196NP and 80C196NU provide the following power saving modes: idle, standby (80C196NU only), and powerdown. They also provide an on-circuit emulation (ONCE) mode that electrically isolates the device from the other system components. This chapter describes each mode and explains how to enter and exit each.
8XC196NP, 80C196NU USER’S MANUAL Table 12-1. Operating Mode Control Signals (Continued) Signal Name Port Pin — Type PLLEN2:1 (80C196NU only) I Description Phase Lock Loop 1 and 2 Enable These input pins are used to enable the on-chip clock multiplier feature and select either the doubled or quadrupled clock speed. CAUTION: If PLLEN1 is held low while PLLEN2 is held high, the device will enter into an unsupported test mode.
SPECIAL OPERATING MODES Table 12-2. Operating Mode Control and Status Registers (Continued) Mnemonic INT_MASK1 Address 0013H Description Interrupt Mask 1 Bits 5 and 6 of this register enable and disable (mask) the external interrupts, EXTINT2 and EXTINT3. INT_PEND 0009H Interrupt Pending Bits 3 and 4 of this register are set to indicate a pending external interrupt, EXTINT0 and EXTINT1.
8XC196NP, 80C196NU USER’S MANUAL Disable Clock Input (Powerdown) FXTAL1 XTAL1 Divide-by-two Circuit Disable Clocks (Powerdown) XTAL2 Peripheral Clocks (PH1, PH2) Disable Oscillator (Powerdown) Clock Generators CLKOUT CPU Clocks (PH1, PH2) Disable Clocks (Idle, Powerdown) A3161-01 Figure 12-1.
SPECIAL OPERATING MODES Disable PLL (Powerdown) FXTAL1 Phase Comparator FXTAL1 XTAL1 Phaselocked Oscillator Disable Oscillator (Powerdown) 4FXTAL1 2FXTAL1 XTAL2 Disable Clock Input (Powerdown) f PLLEN1 Filter Phase-locked Loop Clock Multiplier Divide-by-two Circuit f 2 Disable Clocks (Standby, Powerdown) PLLEN2 Peripheral Clocks (PH1, PH2) Clock Generators CLKOUT CPU Clocks (PH1, PH2) Disable Clocks (Idle, Standby, Powerdown) A3063-02 Figure 12-2.
8XC196NP, 80C196NU USER’S MANUAL The device enters idle mode after executing the IDLPD #1 instruction. Any enabled interrupt source, either internal or external, or a hardware reset can cause the device to exit idle mode. When an interrupt occurs, the CPU clocks restart and the CPU executes the corresponding interrupt service or PTS routine. When the routine is complete, the CPU fetches and then executes the instruction that follows the IDLPD #1 instruction.
SPECIAL OPERATING MODES 12.4.3 Exiting Standby Mode The device will exit standby mode when a transition on an external interrupt pin (EXTINT3:0) or a hardware reset occurs. The interrupts need not be enabled for them to bring the device out of standby, but the pin must be configured as a special-function input (see “Bidirectional Port Pin Configurations” on page 7-7). When an external interrupt brings the device out of standby mode, the corresponding pending bit is set in the interrupt pending register.
8XC196NP, 80C196NU USER’S MANUAL After completing these tasks, execute the IDLPD #2 instruction to enter powerdown mode. NOTE To prevent an accidental return to full power, hold the external interrupt pins (EXTINTx) low while the device is in powerdown mode. 12.5.3 Exiting Powerdown Mode The device will exit powerdown mode when either of the following events occurs: • a hardware reset is generated, or • a transition occurs on an external interrupt pin.
SPECIAL OPERATING MODES XTAL1 CLKOUT PH1 Internal Powerdown Signal EXTINTx RPD Timeout (Internal) A3159-01 Figure 12-3. Power-up and Powerdown Sequence When Using an External Interrupt When using an external interrupt signal to exit powerdown mode, we recommend that you connect the external component shown in Figure 12-4 to the RPD pin.
8XC196NP, 80C196NU USER’S MANUAL During normal operation (before entering powerdown mode), an internal pull-up holds the RPD pin at VCC. When an external interrupt signal is asserted, the internal oscillator circuitry is enabled and turns on a weak internal pull-down. The resistance of the internal pull-down should be approximately 10 kΩ. This weak pull-down causes the external capacitor (C1) to begin discharging at a typical rate of 200 µA.
SPECIAL OPERATING MODES 5V 5 4 EXTINTx 3V 3 RPD, Volts 2 200 µA C1 Discharge 1.2 V 1 .8 V Code Execution Resumes 2 4 6 8 10 12 14 16 18 20 22 Time, ms VCC = 5 V VCC = 3 V A2385-02 Figure 12-5. Typical Voltage on the RPD Pin While Exiting Powerdown When selecting the capacitor, determine the worst-case discharge time needed for the oscillator to stabilize, then use this formula to calculate an appropriate value for C1.
8XC196NP, 80C196NU USER’S MANUAL For example, assume that the oscillator needs at least 12.5 ms to discharge (TDIS = 12.5 ms), V t is 2.5 V, and the discharge current is 200 µA. The minimum C1 capacitor size is 1 µF. ( 0.0125 ) ( 0.0002 ) C 1 = -------------------------------------------------- = 1 µF 2.5 When using an external oscillator, the value of C1 can be very small, allowing rapid recovery from powerdown. For example, a 100 pF capacitor discharges in 1.25 µs. – 10 C1 × Vt ( 1.0 × 10 ) ( 2.
SPECIAL OPERATING MODES Table 12-3. 80C196NU Clock Modes PLLEN2 PLLEN1 Mode 0 0 Clock-multiplier circuitry disabled. 0 1 Reserved. CAUTION: This combination causes the device to enter an unsupported test mode. 1 0 Doubled; clock doubling circuitry enabled. Internal clock is twice the XTAL1 input. 1 1 Quadrupled; clock quadrupling circuitry enabled. Internal clock is four times the XTAL1 input.
13 Interfacing with External Memory
CHAPTER 13 INTERFACING WITH EXTERNAL MEMORY The device can interface with a variety of external memory devices. Six chip-selects can be individually programmed for bus width, the number of wait states, and a multiplexed or demultiplexed address/data bus. Other features of the external memory interface include ready control for inserting additional wait states, a bus-hold protocol that enables external devices to take control of the bus, and two write-control modes for writing words and bytes to memory.
8XC196NP, 80C196NU USER’S MANUAL 13.2 EXTERNAL MEMORY INTERFACE SIGNALS Table 13-2 describes the external memory interface signals. For some signals, the pin has an alternate function (shown in the Multiplexed With column). In some cases the alternate function is a port signal (e.g., P2.7). Chapter 7, “I/O Ports,” describes how to configure a pin for its I/O port function and for its special function. In other cases, the signal description includes instructions for selecting the alternate function.
INTERFACING WITH EXTERNAL MEMORY Table 13-2. External Memory Interface Signals (Continued) Name ALE Type O Description Address Latch Enable Multiplexed With — This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0 for a demultiplexed bus).
8XC196NP, 80C196NU USER’S MANUAL Table 13-2. External Memory Interface Signals (Continued) Name EA# Type I Description External Access Multiplexed With — This input determines whether memory accesses to special-purpose and program memory partitions (FF2000–FF2FFFH) are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant.
INTERFACING WITH EXTERNAL MEMORY Table 13-2. External Memory Interface Signals (Continued) Name WR# Type O Description Write† Multiplexed With WRL# This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. † The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. WRH# O Write High† P5.
8XC196NP, 80C196NU USER’S MANUAL Table 13-3.
INTERFACING WITH EXTERNAL MEMORY 13.3.1 Defining Chip-select Address Ranges This section describes the ADDRCOMx and ADDRMSKx registers and how to set them up for a desired address range. The ADDRCOMx register (Figure 13-2) and ADDRMSKx register (Figure 13-3) control the assertion of each chip-select output CSx#. The BASE19:8 bits in the ADDRCOMx register determine the base address of the address range. The MASK19:8 bits in the ADDRMSKx register determine the size of the address range.
8XC196NP, 80C196NU USER’S MANUAL Address: Table 13-5 Reset State: ADDRMSKx x = 0–5 The address mask (ADDRMSKx) register, together with the address compare register, defines the address range that is assigned to the chip-select x output, CSx#. The address mask register determines the size of the address range, which must be 2n bytes, where n = 8, 9, . . , 20. For a 2nbyte address range, calculate n1 = 20 – n, and set the n1 most-significant bits of MASK19:8 in the address mask register.
INTERFACING WITH EXTERNAL MEMORY Observe the following restrictions in choosing an address range for a chip-select output: • The addresses in the address range must be contiguous. • The size of the address range must be 2n bytes, where n = 8, 9, ..., 20. This corresponds to block sizes of 256 bytes, 512 bytes, ..., 1 Mbyte. • The base address of a 2n-byte address range must be on a 2n-byte boundary (that is, the base address must be evenly divisible by 2n).
8XC196NP, 80C196NU USER’S MANUAL Note that the 32-Kbyte address range could not have 4000H as base address, for example, because 4000H is not on a 32-Kbyte boundary. “Example of a Chip-select Setup” on page 13-12 shows another example of setting up the chipselect unit. 13.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing For each chip-select output address range, the bus control register BUSCONx (Figure 13-4) determines the wait states, the bus width, and the address/data multiplexing.
INTERFACING WITH EXTERNAL MEMORY Table 13-7. BUSCONx Addresses and Reset Values Register Address Reset Value BUSCON0 1F44H 03H BUSCON1 1F4CH 00H BUSCON2 1F54H 00H BUSCON3 1F5CH 00H BUSCON4 1F64H 00H BUSCON5 1F6CH 00H 13.3.3 Chip-select Unit Initial Conditions A chip reset produces the following initial conditions for the chip-select unit: • • • • ADDRMSKx = XFFFH. ADDRCOM0 = 0F20H. This asserts CS0# for the 256-byte address range F2000–F20FFH. ADDRCOM1–ADDRCOM5 = X000H.
8XC196NP, 80C196NU USER’S MANUAL Use the following sequence to initialize the chip-select registers after reset: 1. 2. Initialize chip-select output 0: 1.1. Clear ADDRMSK0. 1.2. Write to ADDRCOM0 to establish the desired base address. 1.3. Write to ADDRMSK0 to establish the desired address range. 1.4. Write the desired bus-parameter values to BUSCON0. While executing in the address range defined in step 1 for chip-select output 0, use the following sequence to initialize chip-select outputs 1–5.
INTERFACING WITH EXTERNAL MEMORY Flash 256K×16 8XC196 CE# CS0# CS2# A19:0 AD15:0 SRAM 8K×8 CE# A18:1 A12:0 A17:0 AD15:0 A12:0 AD7:0 D15:0 D7:0 0 WS 80000–FFFFFH 0 WS 7E000–7FFFFH OE# OE# WE# WE# RD# WR# A2:0 A2:0 AD7:0 D7:0 CE# CS1# 82510 UART 3 WS 01E00–01EFFH Rxd Txd A2433-03 Figure 13-5. Example System for Setting Up Chip-select Outputs Table 13-8.
8XC196NP, 80C196NU USER’S MANUAL Table 13-9. Results for the Chip-select Example Chip Select Address Range Size of Address Range Number of Bits to Set in ADDRMSKx 0 80000–FFFFFH 512 Kbytes = 219 bytes n1 = 20 – 19 = 1 0800H 0800H 1 01E00–01EFFH 256 bytes = 28 bytes n1 = 20 – 8 = 12 001EH 0FFFH 2 7E000–7FFFFH 8 Kbytes = 213 bytes n1 = 20 – 13 = 7 07E0H 0FE0H Contents of ADDRCOMx Contents of ADDRMSKx 13.
INTERFACING WITH EXTERNAL MEMORY no direct access† CCR0 The chip configuration 0 (CCR0) register enables or disables powerdown and standby (80C196NU only) modes and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1. 7 0 1 1 Bit Number WS1 WS0 DEMUX Bit Mnemonic BHE# BW16 PD Function 7:6 1 To guarantee device operation, write ones to these bits.
8XC196NP, 80C196NU USER’S MANUAL no direct access† CCR1 The chip configuration 1 (CCR1) register selects the 16-bit or 24-bit addressing mode and (for the 8XC196NP only) controls whether the internal ROM is mapped into two address ranges, FF2000– FF2FFFH and 002000–002FFFH, or into FF2000–FF2FFFH only. 7 8XC196NP 0 1 1 0 1 1 REMAP MODE64 — 1 1 DM 1 1 — MODE64 — 7 80C196NU Bit Number 0 Bit Mnemonic 7:6 1 5†† DM Function To guarantee device operation, write ones to these bits.
INTERFACING WITH EXTERNAL MEMORY Following reset, the chip automatically fetches the two chip configuration bytes. • 83C196NP only. The CCB fetches are from external memory if EA# = 0 and from internal ROM if EA# = 1. • 80C196NP and 80C196NU only. The CCB fetches are from external memory. (EA# should be tied low.) If the CCBs are stored in external ROM, chip-select output 0 (CS0#) should be connected to that device.
8XC196NP, 80C196NU USER’S MANUAL After RESET# is deasserted, the following pins are initialized: • The P2.7/CLKOUT pin operates as CLKOUT (as during reset). Be sure that the CLKOUT signal does not damage external hardware. • The P3.0/CS0# pin operates as CS0#, which is asserted for the CCB fetches. If you plan to use the P3.0 pin as an input, it must be reconfigured from its post-reset operation as an output. • • • • The BHE#/WRH# pin operates as BHE#. • • • • The INST pin is low (deasserted).
INTERFACING WITH EXTERNAL MEMORY Bus Control A19:16 (EPORT) Address Bits 16–19 Bus Control A19:16 (EPORT) Address Bits 16–19 Address Bits 0–15 Address Bits 0–15 A15:0 A15:0 16-bit Data Driven with the data currently on the internal bus.
8XC196NP, 80C196NU USER’S MANUAL A design can incorporate external devices that operate with different bus widths and multiplexing. The bus parameters used during a particular bus cycle are determined by the chip-select output that is assigned to the address being accessed. Figure 13-9 shows the address and data bus configurations for the four combinations of bus width and multiplexing. For detailed waveforms, see “16-bit Bus Timings” on page 13-22 and “System Bus AC Timing Specifications” on page 13-36.
INTERFACING WITH EXTERNAL MEMORY In multiplexed mode, with the full address on the bus for only half of the cycle, the external device has less time to receive it and to respond. As a result, for the same bus-cycle length (4t) a multiplexed system requires a faster external device (unless wait states are added to the bus cycle). Although the multiplexed mode has this disadvantage, it is useful for compatibility with devices designed for multiplexed operation.
8XC196NP, 80C196NU USER’S MANUAL CS1# CS0# CS# CS# A19:0 AD15:0 Flash 256K×16 Flash 256K×16 8XC196 A18:1 AD15:0 A18:1 A17:0 AD15:0 D15:0 OE# WE# A17:0 D15:0 OE# WE# RD# WR# A2438-03 Figure 13-10. 16-bit External Devices in Demultiplexed Mode 13.5.2 16-bit Bus Timings Figure 13-11 shows idealized 16-bit external-bus timings for the 8XC196NP. The signals are divided into two groups: signals for a demultiplexed bus (top) and signals for a multiplexed bus (bottom).
INTERFACING WITH EXTERNAL MEMORY Demultiplexed CLKOUT ALE Address A19:0 TRLDV RD# TRHDZ TAVDV Data AD15:0 TWLWH WR# TQVWH Data AD15:0 Multiplexed CLKOUT ALE Address A19:16 TRLDV RD# TAVDV AD15:0 Data TRHDZ Data Address TWLWH WR# TQVWH AD15:0 Data Address Data Address A2461-02 Figure 13-11.
8XC196NP, 80C196NU USER’S MANUAL 13.5.3 8-bit Bus Timings Figure 13-12 shows idealized 8-bit timings for the 8XC196NP. One cycle is required for an 8-bit read or write. A 16-bit access requires two cycles. The first cycle accesses the lower byte, and the second cycle accesses the upper byte. Except for requiring an extra cycle to write the bytes separately, the timings are the same as on the 16-bit bus, and the comparison between the multiplexed and demultiplexed cases is also the same.
INTERFACING WITH EXTERNAL MEMORY Demultiplexed CLKOUT ALE Address A19:0 AD15:8 Address High Address High Address RD# Data AD7:0 Data WR# Data AD7:0 Data Multiplexed CLKOUT ALE Address A19:16 Address RD# AD7:0 Data Low Address Data High Address AD15:8 Low Address Data High Address WR# AD7:0 AD15:8 Data Low Address High Address Data Low Address Data High Address A2471-02 Figure 13-12.
8XC196NP, 80C196NU USER’S MANUAL 13.5.4 Comparison of Multiplexed and Demultiplexed Buses This section compares the timings for multiplexed and demultiplexed buses. A 16-bit bus is used for the comparison. “8-bit Bus Timings” on page 13-24 compares the 8-bit and 16-bit buses. In a multiplexed system, where AD15:0 carry both address and data, bus activities are time-compressed in comparison with a demultiplexed system, where the address and data have separate lines (A19:0 and AD15:0).
INTERFACING WITH EXTERNAL MEMORY When selecting infinite wait states, be sure to add external hardware to count wait states and release READY within a specified period of time. Otherwise, a defective external device could tie up the address/data bus indefinitely. NOTE Ready control is valid only for external memory; you cannot add wait states when accessing internal ROM.
8XC196NP, 80C196NU USER’S MANUAL TCLYX (max) CLKOUT READY TAVYV TCLYX (min) TLHLH + 2t ALE TRLRH + 2t RD# TRLDV + 2t TAVDV + 2t AD15:0 (read) Address Out Data In TWLWH + 2t WR# TQVWH + 2t AD15:0 (write) Address Out Data Out BHE#, INST A19:16 CSx# T0013-02 Figure 13-13.
INTERFACING WITH EXTERNAL MEMORY TCLYX (max) CLKOUT TAVYV TCLYX (min) READY TLHLH + 2t ALE TRLRH + 2t RD# TRLDV + 2t TAVDV + 2t AD15:0 (read) Data TWLWH + 2t WR# TQVWH + 2t AD15:0 (write) Data Valid BHE#, INST A19:0 CSx# T0007-02 Figure 13-14.
8XC196NP, 80C196NU USER’S MANUAL TCHYX (max) CLKOUT TCHYX (min) TAVYV READY TLHLH + 2t ALE TRLRH + 2t RD# TRLDV + 2t TAVDV + 2t AD15:0 (read) Data Valid TWLWH + 2t WR# TQVWH + 2t AD15:0 (write) Data Valid BHE#, INST A19:16 CS x# T0014-02 Figure 13-15. READY Timing Diagram — Demultiplexed Mode (80C196NU) 13.7 BUS-HOLD PROTOCOL The 8XC196Nx supports a bus-hold protocol that allows external devices to gain control of the address/data bus.
INTERFACING WITH EXTERNAL MEMORY . CLKOUT THVCH THVCH Hold Latency HOLD# TCLHAL TCLHAH HLDA# TCLBRL TCLBRH BREQ# THALAZ THAHAX A19:0, AD15:0 THALBZ CSx#, BHE#, INST, RD#, WR# WRL#, WRH# THAHBV Weakly held inactive TCLLH ALE Start of strongly driven ALE A2460-03 Figure 13-16. HOLD#, HLDA# Timing Table 13-12.
8XC196NP, 80C196NU USER’S MANUAL If the 8XC196Nx has a pending external bus cycle while it is in hold (another device has control of the bus), it asserts BREQ# to request control of the bus. After the external device responds by releasing HOLD#, the 8XC196Nx exits hold and then deasserts BREQ# and HLDA#. 13.7.1 Enabling the Bus-hold Protocol To use the bus-hold protocol, you must configure P2.3/BREQ#, P2.5/HOLD#, and P2.6/HLDA# to operate as special-function signals.
INTERFACING WITH EXTERNAL MEMORY Table 13-13. Maximum Hold Latency Bus Cycle Type Maximum Hold Latency (state times) Internal execution or idle mode 1.5 16-bit external execution 2.5 + 1 per wait state 8-bit external execution 2.5 + 2 per wait state 13.7.4 Regaining Bus Control While HOLD# is asserted, the 8XC196Nx continues executing code until it needs to access the external bus. If executing from internal memory, it continues until it needs to perform an external memory cycle.
8XC196NP, 80C196NU USER’S MANUAL Standard Mode Write Strobe Mode ALE ALE WR# WRL# Active for low- or high-byte write. BHE# Active for low-byte write. WRH# Active for high-byte write. Active for high-byte write. A2472-02 Figure 13-17. Write-control Signal Waveforms Table 13-14 compares the values of the write-control signals for write operations in the standard mode and the write strobe mode.
INTERFACING WITH EXTERNAL MEMORY To write single bytes on a 16-bit bus requires separate low-byte and high-byte write signals (WRL# and WRH#). Figure 13-18 shows a sample circuit that combines WR#, BHE#, and address bit 0 (A0) to produce these signals. This additional logic is unnecessary, however. In the write strobe mode, WRL# and WRH# are available at the device’s external pins. BHE# WRH# WR# WRL# A0 A0104-01 Figure 13-18.
8XC196NP, 80C196NU USER’S MANUAL Figure 13-19 illustrates the use of the write strobe mode in a mixed 8-bit and 16-bit system with two flash memories and one SRAM. The WRL# signal, which is generated for all 8-bit writes (Table 13-14), is used to write bytes to the SRAM. Note that the RD# signal is sufficient for single-byte reads on a 16-bit bus. Both bytes are put onto the data bus and the memory controller discards the unwanted byte.
INTERFACING WITH EXTERNAL MEMORY TCLCL TCHCL CLKOUT TRLCL TCLLH TLLCH TLHLH ALE TLHLL TLLRL TAVLL TLLAX TRHLH TRLRH RD# TRHDZ TRLDV TRLAZ AD15:0 (read) Address Out Data TAVDV TWHLH TWLWH TLLWL WR# TWHQX TQVWH AD15:0 (write) Address Out Address Out Data Out TRHBX TWHBX BHE#, INST Valid TRHAX TWHAX AD15:8 Address Out TSLDV A19:16 CSx# Address Out TWHSH TRHSH A2367-05 Figure 13-20.
8XC196NP, 80C196NU USER’S MANUAL TCLCL TCHDV T TRLCL TCLLH TCHCL CLKOUT TRHLH TLLCH TLHLH TLHLL TLLRL ALE TRLRH TRHDZ TRLAZ RD# TRLDV TAVLL AD15:0 (read) TLLAX TAVDV Address Out Data In TCHWH TLLWL TWLWH TWHLH TWHQX WR# TQVWH AD15:0 (write) Address Out Data Out Address Out TWHBX, TRHBX BHE#, INST TWHAX,TRHAX AD15:8 TWHSH,TRHSH A19:16 CSx# T0011-02 Figure 13-21.
INTERFACING WITH EXTERNAL MEMORY TCLCL TCHCL CLKOUT TCLDV TLLCH TCLLH TLHLH ALE TLHLL TRLRH TRHLH TRLCH RD# TRHDZ TRLDV AD15:0 (read) Valid TAVDV TCHWH TWHLH TWLWH WR# TWLCH TQVWH AD15:0 (write) TWHQX Valid TRHBX TWHBX BHE#, INST Valid TRHAX A19:0 CSx# Address Out TWHAX Address A2368-05 Figure 13-22.
8XC196NP, 80C196NU USER’S MANUAL TCHCL T TCLCL TCLLH TLLCH TCHWH CLKOUT TLHLH TWHLH TRHLH TLHLL ALE TRHRL TRHDZ TRLCL TRHAX TRLRH TAVRL RD# TCHDV TRLDV TAVDV TSLDV AD15:0 (read) Valid TWHQX TWLCL TAVWL TWHAX TWLWH WR# AD15:0 (write) TQVWH Valid TWHBX,TRHBX BHE#, INST A19:0 CS x# T0012-02 Figure 13-23. Demultiplexed System Bus Timing (80C196NU) 13.9.1 Deferred Bus-cycle Mode (80C196NU Only) The 80C196NU offers a deferred bus cycle mode. This bus mode (enabled by CCR1.
INTERFACING WITH EXTERNAL MEMORY CLKOUT TWHLH + 2t TLHLH + 2t ALE TRHLH + 2t TAVRL + 2t RD# TAVDV + 2t AD15:0 (read) valid valid TAVWL + 2t WR# AD15:0 (write) valid BHE#, INST A19:16 CSx# T0010-02 Figure 13-24.
8XC196NP, 80C196NU USER’S MANUAL 13.9.2 Explanation of AC Symbols Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. For example, TLLRL is the time between signal L (ALE) condition L (Low) and signal R (RD#) condition L (Low). Table 13-15 defines the signal and condition codes. Table 13-15.
INTERFACING WITH EXTERNAL MEMORY Table 13-16. AC Timing Definitions (Continued) Symbol Definition The 8XC196Nx Meets These Specifications f Operating frequency Frequency of the signal input on the XTAL1 pin times the clock multiplier (x). For the 8XC196NP, x is always 1; for the 80C196NU, x is 1, 2, or 4, depending on the clock mode. The internal bus speed of the device is ½ f. t Operating period (1/f) TAVLL Address Setup to ALE Low All AC Timings are referenced to t.
8XC196NP, 80C196NU USER’S MANUAL Table 13-16. AC Timing Definitions (Continued) Symbol Definition The 8XC196Nx Meets These Specifications (Continued) TRHAX (Multiplexed Mode) AD15:8/CSx# Hold after RD# High Minimum time the high byte of the address in 8-bit mode will be valid after RD# inactive. (Demultiplexed Mode) A19:0/CSx# Hold after RD# High Minimum time the address will be valid after RD# inactive. TRHBX BHE#, INST Hold after RD# High Minimum time these signals will be valid after RD# inactive.
INTERFACING WITH EXTERNAL MEMORY Table 13-16. AC Timing Definitions (Continued) Symbol Definition The 8XC196Nx Meets These Specifications (Continued) TWHSH A19:0/CSx# Hold after WR# High TWLCH WR# Low to CLKOUT High Minimum time the address and chip-select output are held after WR# inactive. Minimum and maximum time between WR# being asserted and CLKOUT going high. TWLCL WR# Low to CLKOUT Low Minimum and maximum time between WR# being asserted and CLKOUT going low.
A Instruction Set Reference
APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS® 96 microcontrollers. It defines the processor status word (PSW) flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes, instruction lengths, and execution times. It includes the following tables. • Table A-1 on page A-2 is a map of the opcodes.
8XC196NP, 80C196NU USER’S MANUAL Table A-1.
INSTRUCTION SET REFERENCE Table A-1.
8XC196NP, 80C196NU USER’S MANUAL Table A-2. Processor Status Word (PSW) Flags Mnemonic C Description The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of the last bit shifted out of an operand. If a subtraction operation generates a borrow, the carry flag is cleared. C Value of Bits Shifted Off 0 < ½ LSB 1 ≥ ½ LSB Normally, the result is rounded up if the carry flag is set. The sticky bit flag allows a finer resolution in the rounding decision.
INSTRUCTION SET REFERENCE Table A-3 shows the effect of the PSW flags or a specified condition on conditional jump instructions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction on the PSW flags. Table A-3.
8XC196NP, 80C196NU USER’S MANUAL Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands. Table A-5. Operand Variables Variable Description aa A 2-bit field within an opcode that selects the basic addressing mode used. This field is present only in those opcodes that allow addressing mode options. The field is encoded as follows: baop A byte operand that is addressed by any addressing mode.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set Mnemonic ADD (2 operands) Operation Instruction Format ADD WORDS. Adds the source and destination word operands and stores the sum into the destination operand. (DEST) ← (DEST) + (SRC) DEST, SRC ADD wreg, waop (011001aa) (waop) (wreg) PSW Flag Settings ADD (3 operands) Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — ADD WORDS. Adds the two source word operands and stores the sum into the destination operand.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic ADDCB Operation Instruction Format ADD BYTES WITH CARRY. Adds the source and destination byte operands and the carry flag (0 or 1) and stores the sum into the destination operand. DEST, SRC ADDCB breg, baop (101101aa) (baop) (breg) (DEST) ← (DEST) + (SRC) + C PSW Flag Settings AND (2 operands) Z N C V VT ST ↓ ✓ ✓ ✓ ↑ — LOGICAL AND WORDS.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ANDB (3 operands) LOGICAL AND BYTES. ANDs the two source byte operands and stores the result into the destination operand. The result has ones in only the bit positions in which both operands had a “1” and zeros in all other bit positions.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic BMOVI Operation Instruction Format INTERRUPTIBLE BLOCK MOVE. Moves a block of word data from one location in memory to another. The instruction is identical to BMOV, except that BMOVI is interruptible. The source and destination addresses are calculated using the indirect with autoincrement addressing mode. A long register (PTRS) addresses the source and destination pointers, which are stored in adjacent word registers.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic CLR Operation Instruction Format CLEAR WORD. Clears the value of the operand. (DEST) ← 0 DEST CLR wreg (00000001) (wreg) PSW Flag Settings CLRB Z N C V VT ST 1 0 0 0 — — CLEAR BYTE. Clears the value of the operand. (DEST) ← 0 DEST CLRB breg (00010001) (breg) PSW Flag Settings CLRC Z N C V VT ST 1 0 0 0 — — CLEAR CARRY FLAG. Clears the carry flag.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic CMPB Operation Instruction Format COMPARE BYTES. Subtracts the source byte operand from the destination byte operand. The flags are altered, but the operands remain unaffected. If a borrow occurs, the carry flag is cleared; otherwise, it is set. DEST, SRC CMPB breg, baop (100110aa) (baop) (breg) (DEST) – (SRC) PSW Flag Settings CMPL Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — COMPARE LONG.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic DI Operation Instruction Format DISABLE INTERRUPTS. Disables interrupts. Interrupt calls cannot occur after this instruction. Interrupt Enable (PSW.1) ← 0 DI (11111010) PSW Flag Settings DIV Z N C V VT ST — — — — — — DIVIDE INTEGERS. Divides the contents of the destination long-integer operand by the contents of the source integer word operand, using signed arithmetic.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic DIVU Operation Instruction Format DIVIDE WORDS, UNSIGNED. Divides the contents of the destination double-word operand by the contents of the source word operand, using unsigned arithmetic. It stores the quotient into the low-order word (i.e., the word with the lower address) of the destination operand and the remainder into the high-order word. The following two statements are performed concurrently.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic DJNZW Operation Instruction Format DECREMENT AND JUMP IF NOT ZERO WORD. Decrements the value of the word operand by 1. If the result is 0, control passes to the next sequential instruction. If the result is not 0, the instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic EBMOVI Operation Instruction Format EXTENDED INTERRUPTABLE BLOCK MOVE. Moves a block of word data from one memory location to another. This instruction allows you to move blocks of up to 64K words between any two locations in the 16-Mbyte address space. This instruction is interruptable.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic ECALL Operation Instruction Format EXTENDED CALL. Pushes the contents of the program counter (the return address) onto the stack, then adds to the program counter the offset between the end of this instruction and the target label, effecting the call. The operand may be any address in the address space.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic ELD Operation Instruction Format DEST, SRC EXTENDED LOAD WORD. Loads the value of the source word operand into the destination operand. ELD This instruction allows you to move data from anywhere in the 16-Mbyte address space into the lower register file. ext. indexed: (11101001) (treg) (disp-low) (disp-high) (disp-ext) (wreg) wreg, [treg] ext. indirect: (11101000) (treg) (wreg) ext.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic EST Operation Instruction Format SRC, DEST EXTENDED STORE WORD. Stores the value of the source (leftmost) word operand into the destination (rightmost) operand. EST This instruction allows you to move data from the lower register file to anywhere in the 16Mbyte address space. ext. indexed: (00011101) (treg) (disp-low) (disp-high) (disp-ext) (wreg) wreg, [treg] ext. indirect: (00011100) (treg) (wreg) ext.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic EXTB Operation Instruction Format SIGN-EXTEND SHORT-INTEGER INTO INTEGER. Sign-extends the low-order byte of the operand throughout the high-order byte of the operand. if DEST.7 = 1 then (high byte DEST) else (high byte DEST) end_if EXTB wreg (00010110) (wreg) ← 0FFH ←0 PSW Flag Settings IDLPD Z N C V VT ST ✓ ✓ 0 0 — — IDLE/POWERDOWN.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic INC Operation Instruction Format INCREMENT WORD. Increments the value of the word operand by 1. (DEST) ← (DEST) + 1 INC wreg (00000111) (wreg) PSW Flag Settings INCB Z N C V VT ST ✓ ✓ ✓ ✓ ↑ 0 INCREMENT BYTE. Increments the value of the byte operand by 1. (DEST) ← (DEST) + 1 INCB breg (00010111) (breg) PSW Flag Settings JBC Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — JUMP IF BIT IS CLEAR. Tests the specified bit.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic JC Operation Instruction Format JUMP IF CARRY FLAG IS SET. Tests the carry flag. If the carry flag is clear, control passes to the next sequential instruction. If the carry flag is set, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in the range of –128 to +127.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic JGT Operation Instruction Format JUMP IF SIGNED GREATER THAN. Tests both the zero flag and the negative flag. If either flag is set, control passes to the next sequential instruction. If both flags are clear, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in the range of –128 to +127.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic JLT Operation Instruction Format JUMP IF SIGNED LESS THAN. Tests the negative flag. If the flag is clear, control passes to the next sequential instruction. If the negative flag is set, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in the range of –128 to +127.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic JNH Operation Instruction Format JUMP IF NOT HIGHER (UNSIGNED). Tests both the zero flag and the carry flag. If the carry flag is set and the zero flag is clear, control passes to the next sequential instruction. If either the carry flag is clear or the zero flag is set, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic JNVT Operation Instruction Format JUMP IF OVERFLOW-TRAP FLAG IS CLEAR. Tests the overflow-trap flag. If the flag is set, this instruction clears the flag and passes control to the next sequential instruction. If the overflow-trap flag is clear, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in range of –128 to +127.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic JVT Operation Instruction Format JUMP IF OVERFLOW-TRAP FLAG IS SET. Tests the overflow-trap flag. If the flag is clear, control passes to the next sequential instruction. If the overflow-trap flag is set, this instruction clears the flag and adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in range of –128 to +127.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic LDB Operation Instruction Format LOAD BYTE. Loads the value of the source byte operand into the destination operand. (DEST) ← (SRC) DEST, SRC LDB breg, baop (101100aa) (baop) (breg) PSW Flag Settings LDBSE Z N C V VT ST — — — — — — LOAD BYTE SIGN-EXTENDED. Signextends the value of the source shortinteger operand and loads it into the destination integer operand.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MUL (2 operands) MULTIPLY INTEGERS. Multiplies the source and destination integer operands, using signed arithmetic, and stores the 32-bit result into the destination long-integer operand. The sticky bit flag is undefined after the instruction is executed.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULB (3 operands) MULTIPLY SHORT-INTEGERS. Multiplies the two source short-integer operands, using signed arithmetic, and stores the 16-bit result into the destination integer operand. The sticky bit flag is undefined after the instruction is executed.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULUB (2 operands) MULTIPLY BYTES, UNSIGNED. Multiplies the source and destination operands, using unsigned arithmetic, and stores the word result into the destination operand. The sticky bit flag is undefined after the instruction is executed.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic NORML Operation Instruction Format NORMALIZE LONG-INTEGER. Normalizes the source (leftmost) long-integer operand. (That is, it shifts the operand to the left until its most significant bit is “1” or until it has performed 31 shifts). If the most significant bit is still “0” after 31 shifts, the instruction stops the process and sets the zero flag.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic OR Operation Instruction Format LOGICAL OR WORDS. ORs the source word operand with the destination word operand and replaces the original destination operand with the result. The result has a “1” in each bit position in which either the source or destination operand had a “1”.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic POPA Operation Instruction Format POP ALL. This instruction is used instead of POPF, to support the eight additional interrupts. It pops two words off the stack and places the first word into the INT_MASK1/WSR register pair and the second word into the PSW/INT_MASK register-pair. This instruction increments the SP by 4. Interrupt calls cannot occur immediately following this instruction.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic PUSHA Operation Instruction Format PUSH ALL. This instruction is used instead of PUSHF, to support the eight additional interrupts. It pushes two words — PSW/INT_MASK and INT_MASK1/WSR — onto the stack. PUSHA (11110100) This instruction clears the PSW, INT_MASK, and INT_MASK1 registers and decrements the SP by 4. Interrupt calls cannot occur immediately following this instruction.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic RST Operation Instruction Format RESET SYSTEM. Initializes the PSW to zero, the EPC/PC to FF2080H, and the pins and SFRs to their reset values. Executing this instruction causes the RESET# pin to be pulled low for 16 state times. RST (11111111) SFR ← Reset Status Pin ← Reset Status PSW ← 0 EPC/PC ← FF2080H PSW Flag Settings SCALL Z N C V VT ST 0 0 0 0 0 0 SHORT CALL.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic SHL Operation Instruction Format SHIFT WORD LEFT. Shifts the destination word operand to the left as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. The right bits of the result are filled with zeros.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic SHLL Operation Instruction Format SHIFT DOUBLE-WORD LEFT. Shifts the destination double-word operand to the left as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. The right bits of the result are filled with zeros.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic SHRA Operation Instruction Format ARITHMETIC RIGHT SHIFT WORD. Shifts the destination word operand to the right as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. If the original high order bit value was “0,” zeros are shifted in.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic SHRAL Operation Instruction Format ARITHMETIC RIGHT SHIFT DOUBLEWORD. Shifts the destination double-word operand to the right as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic SHRL Operation Instruction Format LOGICAL RIGHT SHIFT DOUBLE-WORD. Shifts the destination double-word operand to the right as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. The left bits of the result are filled with zeros.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic ST Operation Instruction Format STORE WORD. Stores the value of the source (leftmost) word operand into the destination (rightmost) operand. (DEST) ← (SRC) SRC, DEST ST wreg, waop (110000aa) (waop) (wreg) PSW Flag Settings STB Z N C V VT ST — — — — — — STORE BYTE. Stores the value of the source (leftmost) byte operand into the destination (rightmost) operand.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic SUBB (2 operands) Operation Instruction Format SUBTRACT BYTES. Subtracts the source byte operand from the destination byte operand, stores the result in the destination operand, and sets the carry flag as the complement of borrow. DEST, SRC SUBB breg, baop (011110aa) (baop) (breg) (DEST) ← (DEST) – (SRC) PSW Flag Settings SUBB (3 operands) Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — SUBTRACT BYTES.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic TIJMP Operation Instruction Format TABLE INDIRECT JUMP. Causes execution to continue at an address selected from a table of addresses. The first word register, TBASE, contains the 16-bit address of the beginning of the jump table. TBASE can be located in RAM up to FEH without windowing or above FFH with windowing. The jump table itself can be placed at any nonreserved memory location on a word boundary in page FFH.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic TRAP Operation Instruction Format SOFTWARE TRAP. This instruction causes an interrupt call that is vectored through location FF2010H. The operation of this instruction is not affected by the state of the interrupt enable flag (I) in the PSW. Interrupt calls cannot occur immediately following this instruction. TRAP (11110111) NOTE: 64-Kbyte mode: SP ← SP – 2 (SP) ← PC PC ← (2010H) This instruction is not supported by assemblers.
8XC196NP, 80C196NU USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic XOR Operation Instruction Format LOGICAL EXCLUSIVE-OR WORDS. XORs the source word operand with the destination word operand and stores the result in the destination operand. The result has ones in the bit positions in which either operand (but not both) had a “1” and zeros in all other bit positions.
INSTRUCTION SET REFERENCE Table A-7.
8XC196NP, 80C196NU USER’S MANUAL Table A-7.
INSTRUCTION SET REFERENCE Table A-7.
8XC196NP, 80C196NU USER’S MANUAL Table A-7.
INSTRUCTION SET REFERENCE Table A-7.
8XC196NP, 80C196NU USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic E6 EJMP E7 LJMP E8 ELD Indirect E9 ELD Indexed EA ELDB Indirect EB ELDB Indexed EC DPTS ED EPTS EE Reserved (Note 1) EF LCALL F0 RET F1 ECALL F2 PUSHF F3 POPF F4 PUSHA F5 POPA F6 IDLPD F7 TRAP F8 CLRC F9 SETC FA DI FB EI FC CLRVT FD NOP FE DIV/DIVB/MUL/MULB (Note 2) FF RST NOTES: 1.
INSTRUCTION SET REFERENCE Table A-8.
8XC196NP, 80C196NU USER’S MANUAL Table A-8.
INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Stack Direct Indirect (Note 1) Immediate Indexed (Notes 1, 2) Mnemonic Length Length Opcode Length S/L Opcode — 2 CE 3/4 CF — — — — — — — — — C9 2 CA 3/4 CB — — — — — — — — — — Length Opcode Opcode POP 2 CC — POPA 1 F5 — POPF 1 F3 — — PUSH 2 C8 3 PUSHA 1 F4 — PUSHF 1 F2 — NOTES: 1.
8XC196NP, 80C196NU USER’S MANUAL Table A-8.
INSTRUCTION SET REFERENCE Table A-8.
8XC196NP, 80C196NU USER’S MANUAL Table A-8.
INSTRUCTION SET REFERENCE Table A-8.
8XC196NP, 80C196NU USER’S MANUAL Table A-9 lists instructions alphabetically within groups, along with their execution times, expressed in state times. Table A-9. Instruction Execution Times (in State Times) Arithmetic (Group I) Indirect Mnemonic Direct Immed. Normal Reg. Mem. Indexed Autoinc. Reg. Mem. Short Reg. Long Mem. Reg. Mem.
INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Arithmetic (Group II) Indirect Mnemonic Direct Immed. Normal Indexed Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
8XC196NP, 80C196NU USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Stack (Register) Indirect Mnemonic Direct Immed. Normal Reg. Mem. Indexed Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem.
INSTRUCTION SET REFERENCE Table A-9.
8XC196NP, 80C196NU USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Jump Mnemonic Direct Immed. Extended-indirect Extended-indexed Normal Autoinc. EBR — — 9 — EJMP — — — — — 8 Indirect Mnemonic Direct Indexed Immed. Normal Autoinc.
INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Call (Memory) Extended-indirect Mnemonic ECALL 1-Mbyte mode Direct Immed. — — Direct Immed. Extended-indexed Normal Autoinc. — — 22 Indirect Mnemonic Indexed Normal Autoinc.
8XC196NP, 80C196NU USER’S MANUAL Table A-9.
INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Special Indirect Mnemonic Direct Indexed Immed. Normal Autoinc. Short Long CLRC 2 — — — — — CLRVT 2 — — — — — DI 2 — — — — — EI 2 — — — — — IDLPD Valid key Invalid key — — 12 28 — — — — — — — — NOP 2 — — — — — RST 4 — — — — — SETC 2 — — — — — SKIP 3 — — — — — PTS Indirect Mnemonic Indexed Direct Immed. Normal Autoinc.
B Signal Descriptions
APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196NP and 80C196NU. B.1 FUNCTIONAL GROUPINGS OF SIGNALS Table B-1 lists the signals for the 8XC196NP and 80C196NU, grouped by function. A diagram of each package that is currently available shows the pin location of each signal. NOTE As new packages are supported, they will be added to the datasheets first.
P3.7 / EXTINT3 P1.0 / EPA0 VCC P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1 P2.5 / HOLD# P2.6 / HLDA# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC SIGNAL DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x8XC196NP View of component as mounted on PC board 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS A18 / EPORT.2 A19 / EPORT.
P3.7 / EXTINT3 P1.0 / EPA0 VCC P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1 P2.5 / HOLD# P2.6 / HLDA# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC SIGNAL DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x8XC196NU View of component as mounted on PC board 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS A18 / EPORT.2 A19 / EPORT.
8XC196NP, 80C196NU USER’S MANUAL B.2 SIGNAL DESCRIPTIONS Table B-2 defines the columns used in Table B-3, which describes the signals. Table B-2. Description of Columns of Table B-3 Column Heading Description Name Lists the signals, arranged alphabetically. Many pins have two functions, so there are more entries in this column than there are pins. Every signal is listed in this column.
SIGNAL DESCRIPTIONS Table B-3. Signal Descriptions (Continued) Name ALE Type O Description Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0 for a demultiplexed bus). ALE differs from ADV# in that it does not remain active during the entire bus cycle.
8XC196NP, 80C196NU USER’S MANUAL Table B-3. Signal Descriptions (Continued) Name Type EA# (NP only) I Description External Access This input determines whether memory accesses to special-purpose and program memory partitions (FF2000–FF2FFFH) are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant.
SIGNAL DESCRIPTIONS Table B-3. Signal Descriptions (Continued) Name HOLD# Type I Description Bus Hold Request An external device uses this active-low input signal to request control of the bus. This pin functions as HOLD# only if the pin is configured for its special function (see “Bidirectional Port Pin Configurations” on page 7-7) and the bushold protocol is enabled. Setting bit 7 of the window selection register (WSR) enables the bus-hold protocol. HOLD# is multiplexed with P2.5.
8XC196NP, 80C196NU USER’S MANUAL Table B-3. Signal Descriptions (Continued) Name PLLEN2:1 (NU only) Type I Description Phase-locked Loop 1 and 2 Enable These input pins are used to enable the on-chip clock multiplier feature and select either the doubled or quadrupled clock speed as follows: PLLEN1 PLLEN2 0 0 0 1 1 0 1 1 Mode standard mode; clock multiplier circuitry disabled. Internal clock equals the XTAL1 input frequency. Reserved† doubled mode; clock multiplier circuitry enabled.
SIGNAL DESCRIPTIONS Table B-3. Signal Descriptions (Continued) Name RPD Type I Description Return from Powerdown Timing pin for the return-from-powerdown circuit. If your application uses powerdown mode, connect a capacitor† between RPD and VSS if either of the following conditions are true.
8XC196NP, 80C196NU USER’S MANUAL Table B-3. Signal Descriptions (Continued) Name VCC Type PWR Description Digital Supply Voltage Connect each VCC pin to the digital supply voltage. V SS GND Digital Circuit Ground Connect each VSS pin to ground through the lowest possible impedance path. WR# O Write† This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# is multiplexed with WRL#.
SIGNAL DESCRIPTIONS B.3 DEFAULT CONDITIONS Table B-5 lists the default functions of the I/O and control pins of the 8XC196NP and 80C196NU with their values during various operating conditions. Table B-4 defines the symbols used to represent the pin status. Refer to the DC Characteristics table in the datasheet for actual specifications for VOL, VIL, VOH, and VIH. Table B-4.
8XC196NP, 80C196NU USER’S MANUAL Table B-5. 8XC196NP and 80C196NU Pin Status (Continued) Port Pins Multiplexed With During RESET# Active Upon RESET# Inactive (Note 11) Idle Powerdown (NP/NU) and Standby (NU only) Hold Bus Idle P4.3 — WK1 WK1 (Note 1) (Note 1) (Note 1) — EPORT.
C Registers
APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-1 lists the modules and major components of the device with their related configuration and status registers. Table C-2 lists the registers, arranged alphabetically by mnemonic, along with their names, addresses, and reset values. Following the tables, individual descriptions of the registers are arranged alphabetically by mnemonic. . Table C-1.
8XC196NP, 80C196NU USER’S MANUAL Table C-2.
REGISTERS Table C-2.
8XC196NP, 80C196NU USER’S MANUAL Table C-2.
REGISTERS ACC_0x Address: Reset State: ACC_0x x = 0, 2 (80C196NU) Table C-3 The 32-bit accumulator register (ACC_0x) resides at locations 0C–0FH. You can read from or write to the accumulator register as two words at locations 0CH and 0EH.
8XC196NP, 80C196NU USER’S MANUAL ACC_STAT Address: Reset State: ACC_STAT (80C196NU) 0BH 00H The accumulator control and status (ACC_STAT) register enables and disables fractional and saturation modes and contains three status flags that indicate the status of the accumulator’s contents. 7 Bit Number 7 0 FME 80C196NU SME — Bit Mnemonic FME — — STOVF OVF STSAT Function Fractional Mode Enable Set this bit to enable fractional mode. (See Table C-4.
REGISTERS ACC_STAT Table C-4. Effect of SME and FME Bit Combinations SME FME Description 0 0 Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend (the number to be added to the contents of the accumulator) are equal, but the sign bit of the result is the opposite. 0 1 Shifts the addend (the number to be added to the contents of the accumulator) left by one bit before adding it to the accumulator.
8XC196NP, 80C196NU USER’S MANUAL ADDRCOMx Address: Reset State: ADDRCOMx x = 0–5 Table C-5 The address compare (ADDRCOMx) register specifies the base (lowest) address of the address range. The base address of a 2n-byte address range must be on a 2n-byte boundary.
REGISTERS ADDRMSKx Address: Reset State: ADDRMSKx x = 0–5 Table C-6 The address mask (ADDRMSKx) register, together with the address compare register, defines the address range that is assigned to the chip-select x output, CSx#. The address mask register determines the size of the address range, which must be 2n bytes, where n = 8, 9, . . , 20. For a 2nbyte address range, calculate n1 = 20 – n, and set the n1 most-significant bits of MASK19:8 in the address mask register.
8XC196NP, 80C196NU USER’S MANUAL BUSCONx Address: Reset State: BUSCONx x = 0–5 Table C-7 For the address range assigned to chip-select x, the bus control (BUSCONx) register specifies the number of wait states, the bus width, and the address/data multiplexing for all external bus cycles that access address range x.
REGISTERS CCR0 no direct access† CCR0 The chip configuration 0 (CCR0) register enables or disables powerdown and standby (80C196NU only) modes and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1. 7 0 1 1 Bit Number WS1 WS0 DEMUX Bit Mnemonic BHE# BW16 PD Function 7:6 1 To guarantee device operation, write ones to these bits.
8XC196NP, 80C196NU USER’S MANUAL CCR1 no direct access† CCR1 The chip configuration 1 (CCR1) register selects the 16-bit or 24-bit addressing mode and (for the 8XC196NP only) controls whether the internal ROM is mapped into two address ranges, FF2000– FF2FFFH and 002000–002FFFH, or into FF2000–FF2FFFH only. 7 0 1 8XC196NP 1 0 1 1 REMAP MODE64 — 7 1 80C196NU Bit Number 0 1 DM 1 Bit Mnemonic 1 — MODE64 — Function 7:6 1 To guarantee device operation, write ones to these bits.
REGISTERS CON_REG0 Address: Reset State: CON_REG0 1FB6H FEH The control (CON_REG0) register controls the clock prescaler for the three pulse-width modulators (PWM0–PWM2). 7 8XC196NP 0 — — — — — — — CLK0† — — — — — — CLK1 CLK0 7 80C196NU Bit Number 0 Bit Mnemonic Function 7:1 (NP) 7:2 (NU) — Reserved; for compatibility with future devices, write zeros to these bits.
8XC196NP, 80C196NU USER’S MANUAL EP_DIR Address: Reset State: EP_DIR 1FE3H FFH In I/O mode, each bit of the extended port I/O direction (EP_DIR) register controls the direction of the corresponding pin. Clearing a bit configures a pin as a complementary output; setting a bit configures a pin as either an input or an open-drain output. (Open-drain outputs require external pull-ups).
REGISTERS EP_MODE Address: Reset State: EP_MODE 1FE1H FFH Each bit of the extended port mode (EP_MODE) register controls whether the corresponding pin functions as a standard I/O port pin or as an extended-address signal. Setting a bit configures a pin as an extended-address signal; clearing a bit configures a pin as a standard I/O port pin. 7 0 — Bit Number — — — PIN3 Bit Mnemonic PIN2 PIN1 PIN0 Function 7:4 — Reserved; always write as zeros.
8XC196NP, 80C196NU USER’S MANUAL EP_PIN Address: Reset State: EP_PIN 1FE7H XXH Each bit of the extended port input (EP_PIN) register reflects the current state of the corresponding pin, regardless of the pin configuration. 7 0 — Bit Number — Bit Mnemonic — — PIN3 PIN2 Function 7:4 — Reserved; always write as zeros. 3:0 PIN3:0 Extended Address Port Pin x Input This bit contains the current state of EPORT.x.
REGISTERS EP_REG Address: Reset State: EP_REG 1FE5H X0H Each bit of the extended port data output (EP_REG) register contains data to be driven out by the corresponding pin. When a pin is configured as standard I/O (EP_MODE.x = 0), the result of a CPU write to EP_REG is immediately visible on the pin. During nonextended data accesses, EP_REG contains the value of the memory page that is to be accessed.
8XC196NP, 80C196NU USER’S MANUAL EPA_MASK Address: Reset State: EPA_MASK 1F9CH AAH The EPA interrupt mask (EPA_MASK) register enables or disables (masks) the multiplexed EPA3:0 overrun interrupts (OVR3:0). 7 0 — Bit Number OVR3 Bit Mnemonic — OVR2 — OVR1 — OVR0 Function 7, 5, 3, 1 — Reserved; for compatibility with future devices, write zeros to these bits. 6, 4, 2, 0 OVR3 OVR2 OVR1 OVR0 Setting this bit enables the corresponding source as a shared overrun interrupt source.
REGISTERS EPA_PEND Address: Reset State: EPA_PEND 1F9EH AAH When hardware detects a pending EPA3:0 overrun interrupt (OVR3:0), it sets the corresponding bit in the EPA interrupt pending (EPA_PEND) register. OVR0 and OVR1 are multiplexed to share one bit (OVR0_1) in the INT_PEND1 register. Similarly, OVR2 and OVR3 are multiplexed to share another bit (OVR2_3) in the INT_PEND1 register. 7 0 — OVR3 — OVR2 Bit Number 7, 5, 3, 1 6, 4, 2, 0 NOTE: — OVR1 — OVR0 Function Reserved.
8XC196NP, 80C196NU USER’S MANUAL EPAx_CON Address: Reset State: EPAx_CON x = 0–3 Table C-8 The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
REGISTERS EPAx_CON Address: Reset State: EPAx_CON (Continued) x = 0–3 Table C-8 The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
8XC196NP, 80C196NU USER’S MANUAL EPAx_CON Address: Reset State: EPAx_CON (Continued) x = 0–3 Table C-8 The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
REGISTERS EPAx_CON Table C-8.
8XC196NP, 80C196NU USER’S MANUAL EPAx_TIME Address: Reset State: EPAx_TIME x = 0–3 Table C-9 The EPA time (EPAx_TIME) registers are the event-time registers for the EPA channels. In capture mode, the value of the reference timer is captured in EPAx_TIME when an input transition occurs. Each event-time register is buffered, allowing the storage of two capture events at once. In compare mode, the EPA triggers a compare event when the reference timer matches the value in EPAx_TIME.
REGISTERS INT_MASK Address: Reset State: INT_MASK 0008H 00H The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the stack and POPF or POPA restores it.
8XC196NP, 80C196NU USER’S MANUAL INT_MASK1 Address: Reset State: INT_MASK1 0013H 00H The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
REGISTERS INT_PEND Address: Reset State: INT_PEND 0009H 00H When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. 7 0 EPA0 RI TI EXTINT1 Bit Number 7:3 1:0 EXTINT0 — OVRTM2 OVRTM1 Function Any set bit indicates that the corresponding interrupt is pending.
8XC196NP, 80C196NU USER’S MANUAL INT_PEND1 Address: Reset State: INT_PEND1 0012H 00H When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
REGISTERS ONES_REG Address: Reset State: ONES_REG 02H FFFFH The two-byte ones register (ONES_REG) is always equal to FFFFH. It is useful as a fixed source of all ones for comparison operations. 15 8 One (high byte) 7 0 One (low byte) Bit Number 15:0 Function One These bits are always equal to FFFFH.
8XC196NP, 80C196NU USER’S MANUAL Px_DIR Address: Table C-10 Reset State: Px_DIR x = 1–4 Each pin of port x can operate in any of the standard I/O modes of operation: complementary output, open-drain output, or high-impedance input. The port x I/O direction (Px_DIR) register determines the I/O direction for each port x pin. The register settings for an open-drain output or a high-impedance input are identical. An open-drain output configuration requires an external pull-up.
REGISTERS Px_MODE Address: Reset State: Px_MODE x = 1–4 Table C-11 Each bit of the port x mode (Px_MODE) register controls whether the corresponding pin functions as a standard I/O port pin or as a special-function signal.
8XC196NP, 80C196NU USER’S MANUAL Px_PIN Address: Reset State: Px_PIN x = 1–4 Table C-13 Each bit of the port x pin input (Px_PIN) register reflects the current state of the corresponding pin, regardless of the pin configuration. 7 x = 1–3 0 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 — — — — PIN3 PIN2 PIN1 PIN0 7 0 x=4 Bit Number 7:0 Bit Mnemonic PIN7:0 Function Port x Pin y Input Value This bit contains the current state of Px.y. Table C-13.
REGISTERS Px_REG Address: Reset State: Px_REG x = 1–4 Table C-14 For an input, set the corresponding port x data ouput (Px_REG) register bit. For an output, write the data to be driven out by each pin to the corresponding bit of Px_REG. When a pin is configured as standard I/O (Px_MODE.y = 0), the result of a CPU write to P x_REG is immediately visible on the pin. When a pin is configured as a special-function signal (Px_MODE.
8XC196NP, 80C196NU USER’S MANUAL PSW no direct access PSW The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
REGISTERS PSW no direct access PSW (Continued) The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
8XC196NP, 80C196NU USER’S MANUAL PTSSEL Address: Reset State: PTSSEL 0004H 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
REGISTERS PTSSRV Address: Reset State: PTSSRV 0006H 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
8XC196NP, 80C196NU USER’S MANUAL PWMx_CONTROL Address: Reset State: PWMx_CONTROL x = 0–2 Table C-15 The PWM control (PWMx_CONTROL) register determines the duty cycle of the PWM x channel. A zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in this register causes the PWM to have its maximum duty cycle (99.6% duty cycle). 7 0 PWM Duty Cycle Bit Number 7:0 Function PWM Duty Cycle This register controls the PWM duty cycle.
REGISTERS SBUF_RX Address: Reset State: SBUF_RX 1FB8H 00H The serial port receive buffer (SBUF_RX) register contains data received from the serial port. The serial port receiver is buffered and can begin receiving a second data byte before the first byte is read. Data is held in the receive shift register until the last data bit is received, then the data byte is loaded into SBUF_RX.
8XC196NP, 80C196NU USER’S MANUAL SBUF_TX Address: Reset State: SBUF_TX 1FBAH 00H The serial port transmit buffer (SBUF_TX) register contains data that is ready for transmission. In modes 1, 2, and 3, writing to SBUF_TX starts a transmission. In mode 0, writing to SBUF_TX starts a transmission only if the receiver is disabled (SP_CON.3=0). 7 0 Data to Transmit Bit Number 7:0 Function Data to Transmit This register contains a byte of data to be transmitted by the serial port.
REGISTERS SP Address: Reset State: SP 18H XXXXH The system’s stack pointer (SP) can point anywhere in an internal or external memory page; it must be word aligned and must always be initialized before use. The stack pointer is decremented before a PUSH and incremented after a POP, so the stack pointer should be initialized to two bytes (in 64Kbyte mode) or four bytes (in 1-Mbyte mode) above the highest stack location.
8XC196NP, 80C196NU USER’S MANUAL SP_BAUD Address: Reset State: SP_BAUD 1FBCH 0000H The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate. The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum BAUD_VALUE is 0000H when using the internal clock source (f) and 0001H when using T1CLK.
REGISTERS SP_BAUD Table C-16. SP_BAUD Values When Using the Internal Clock at 25 MHz SP_BAUD Register Value (Note 1) % Error Baud Rate Mode 0 Mode 1, 2, 3 Mode 0 9600 8515H 80A2H 0 Mode 1, 2, 3 0.15 4800 8A2BH 8144H 0 0.16 2400 9457H 828AH 0 0 1200 A8AFH 8515H 0 0 300 (Note 2) 9457H (Note 2) 0 NOTES: 1. Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baudrate generator. 2.
8XC196NP, 80C196NU USER’S MANUAL SP_CON Address: Reset State: SP_CON 1FBBH 00H The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. For the 80C196NU, it also enables or disables the divide-by-two prescaler.
REGISTERS SP_STATUS Address: Reset State: SP_STATUS 1FB9H 0BH The serial port status (SP_STATUS) register contains bits that indicate the status of the serial port. 7 0 RPE/RB8 Bit Number 7 RI TI FE Bit Mnemonic RPE/RB8 TXE OE — — Function Received Parity Error/Received Bit 8 RPE is set if parity is disabled (SP_CON.2 = 0) and the ninth data bit received is high. RB8 is set if parity is enabled (SP_CON.2 = 1) and a parity error occurred. Reading SP_STATUS clears this bit.
8XC196NP, 80C196NU USER’S MANUAL T1CONTROL Address: Reset State: T1CONTROL 1F90H 00H The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
REGISTERS T2CONTROL Address: Reset State: T2CONTROL 1F94H 00H The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
8XC196NP, 80C196NU USER’S MANUAL TIMERx Address: Reset State: TIMERx x = 1–2 Table C-17 This register contains the value of timer x. This register can be written, allowing timer x to be initialized to a value other than zero. 15 8 Timer Value (high byte) 7 0 Timer Value (low byte) Bit Number 15:0 Function Timer Read the current timer x value from this register or write a new timer x value to this register. Table C-17.
REGISTERS WSR Address: Reset State: WSR 0014H 00H The window selection register (WSR) has two functions. One bit enables and disables the bus-hold protocol. The remaining bits select windows. Windows map sections of RAM into the top of the lower register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA restores it.
8XC196NP, 80C196NU USER’S MANUAL WSR Table C-18.
REGISTERS WSR Table C-18.
8XC196NP, 80C196NU USER’S MANUAL WSR1 Address: Reset State: WSR1 (80C196NU) 0015H 00H Window selection 1 (WSR1) register selects a 32- or 64-byte segment of the upper register file or peripheral SFRs to be windowed into the middle of the lower register file, below any window selected by the WSR. 7 Bit Number 0 — 80C196NU W6 W5 W4 W3 Bit Mnemonic W2 W1 W0 Function 7 — Reserved; always write as zero. 6:0 W6:0 Window Selection These bits specify the window size and window number.
REGISTERS WSR1 Table C-19.
8XC196NP, 80C196NU USER’S MANUAL WSR1 Table C-19.
REGISTERS ZERO_REG Address: Reset State: ZERO_REG 00H 0000H The two-byte zero register (ZERO_REG) is always equal to zero. It is useful as a fixed source of the constant zero for comparisons and calculations. 15 8 Zero (high byte) 7 0 Zero (low byte) Bit Number 15:0 Function Zero This register is always equal to zero.
Glossary
GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this manual. (Chapter 1 discusses notational conventions and general terminology.) 1-Mbyte mode The addressing mode that allows code to reside anywhere in the 1-Mbyte addressing space. 64-Kbyte mode The addressing mode that allows code to reside only in page FFH. accumulator A register or storage location that forms the result of an arithmetic or logical operation.
8XC196NP, 80C196NU USER’S MANUAL chip-select unit The integrated module that selects an external memory device during an external bus cycle. clear The “0” value of a bit or the act of giving it a “0” value. See also set. deassert The act of making a signal inactive (disabled). The polarity (high or low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix.
GLOSSARY far data Data that can be accessed only with extended instructions. See also near data. FET Field-effect transistor. f Lowercase “f” represents the frequency of the internal clock. For the 8XC196NP, f is always equal to FXTAL1 (the input frequency on XTAL1). For the 80C196NU, which employs a phase-locked loop with clock multiplier circuitry, f is equal to either FXTAL1, 2FXTAL1, or 4FXTAL1. The multiplier depends on the clock mode, which is controlled by the PLLEN1 and PLLEN2 input pins.
8XC196NP, 80C196NU USER’S MANUAL ISR See interrupt service routine. LONG-INTEGER A 32-bit, signed variable with values from –231 through +231–1. LSB Least-significant bit of a byte or least-significant byte of a word. MAC See multiply-accumulate. maskable interrupts All interrupts except unimplemented opcode, software trap, and NMI.
GLOSSARY nonvolatile memory Read-only memory that retains its contents when power is removed. Many MCS® 96 microcontrollers are available with either masked ROM, EPROM, or OTPROM. Consult the Automotive Products or Embedded Microcontrollers databook to determine which type of memory is available for a specific device. npn transistor A transistor consisting of one part p-type material and two parts n-type material. p-channel FET A field-effect transistor with a p-type conducting path.
8XC196NP, 80C196NU USER’S MANUAL PSW Processor status word. The high byte of the PSW is the status byte, which contains one bit that globally enables or disables servicing of all maskable interrupts, one bit that enables or disables the PTS, and six Boolean flags that reflect the state of the current program. The low byte of the PSW is the INT_MASK register. A push or pop instruction saves or restores both bytes (PSW + INT_MASK). PTS Peripheral transaction server. hardware interrupt processor.
GLOSSARY reserved memory A memory location that is reserved for factory use or for future expansion. Do not use a reserved memory location except to initialize it with FFH. sampled inputs All input pins, with the exception of RESET#, are sampled inputs. The input pin is sampled one state time before the read buffer is enabled. Sampling occurs during PH1 (while CLKOUT is low) and resolves the value (high or low) of the pin before it is presented to the internal bus.
8XC196NP, 80C196NU USER’S MANUAL special-purpose memory A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and several reserved locations. standard interrupt Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine. state time (or state) The basic time unit of the device; the combined period of the two internal timing signals, PH1 and PH2.
Index
INDEX #, defined, 1-3, A-1 1-Mbyte mode, 5-1 fetching code, 5-23, 5-25 fetching data, 5-26 incrementing SP, 5-11 memory configuration example, 5-31 64-Kbyte mode, 5-1, 5-5 fetching code, 5-23, 5-25 fetching data, 5-26 incrementing SP, 5-11 memory configuration example, 5-27, 5-29 A A15:0, B-6 A19:0, 5-1, 13-2, 13-20 for CCB0 fetch, 13-17 A19:16, 7-11, B-6 See also EPORT Accumulator ACC_0x register, 3-4 ACC_STAT register, 3-5 operating modes fractional mode, 3-3 saturation mode, 3-2 setting mode bits (SME a
8XC196NP, 80C196NU USER’S MANUAL Baud-rate generator SIO port, 8-8 BAUD_VALUE, 8-11, C-42 BHE#, 13-3, B-7 during bus hold, 13-30 See also write-control signals BIT, defined, 4-2 Bit-test instructions, A-21 Block diagram address/data bus, 7-11 clock circuitry, 2-7 core, 2-3 core and peripherals, 2-2 EPA, 10-2 EPORT, 7-13 I/O ports, 7-1, 7-5, 7-11, 7-13, 7-15 SIO port, 8-1, 10-2 Block transfer mode‚ See PTS BMOV instruction, A-2, A-9, A-51, A-56 BMOVI instruction, A-3, A-9, A-10, A-51, A-56 BR (indirect) ins
INDEX CMP instruction, A-3, A-11, A-49, A-53, A-60 CMPB instruction, A-3, A-12, A-50, A-53, A-60 CMPL instruction, A-2, A-12, A-51, A-53, A-60 Code execution, 2-4, 2-5 Code fetches, 5-25 CompuServe forums, 1-10 Conditional jump instructions, A-5 CON_REG0, C-50, C-53 Constants, near, 5-24 CPU, 2-3 CS5:0#, B-7 during bus hold, 13-30 Customer service, 1-8 D D/A converter, 9-10 Data far, 5-24 fetches, 5-26 near, 5-24 types, 4-1–4-5 addressing restrictions, 4-1 converting between, 4-4 defined, 4-1 iC-96, 4-1 P
8XC196NP, 80C196NU USER’S MANUAL resetting the timers, 10-21, C-22 selecting the capture/compare event, 10-20, C-21 selecting the time base, 10-19, C-20 selecting up or down counting, 10-16, 10-17, C-46, C-47 signals, 10-2 using for PWM, 6-26, 6-32 See also port 1, port 6, PWM, timer/counters EPA0_CON, C-50, C-53 EPA0_TIME, C-50, C-53 EPA1_CON, 10-19, C-20, C-50, C-53 EPA1_TIME, C-50, C-53 EPA2_CON, C-50, C-53 EPA2_TIME, C-50, C-53 EPA3:0, B-8 EPA3_CON, 10-19, C-20, C-50, C-53 EPA3_TIME, C-50, C-53 EPA_MAS
INDEX device considerations, 11-1–11-11 device reset, 11-8, 11-9, 11-10, 11-11 interrupt processor, 2-6, 6-1 minimum configuration, 11-1 NMI considerations, 6-6 noise protection, 11-4 reset instruction, 4-14 SIO port considerations, 8-6 HLDA#, 13-4, 13-30, B-8 HLDEN bit, 5-14, 13-32 Hold latency, See bus-hold protocol HOLD#, 13-4, 13-30, B-9 considerations, 7-9 Hypertext manuals and datasheets, downloading, 1-10 I I/O ports after reset, 13-18 Idle mode, 2-12, 12-5–12-6, 12-7 entering, 12-6 exiting, 12-6,
8XC196NP, 80C196NU USER’S MANUAL JNC instruction, A-2, A-5, A-24, A-51, A-58, A-66 JNE instruction, A-2, A-5, A-24, A-51, A-58, A-66 JNH instruction, A-2, A-5, A-25, A-51, A-58, A-66 JNST instruction, A-2, A-5, A-25, A-51, A-58, A-66 JNV instruction, A-2, A-5, A-25, A-51, A-58, A-66 JNVT instruction, A-2, A-5, A-26, A-51, A-58, A-66 JST instruction, A-3, A-5, A-26, A-51, A-58, A-66 Jump instructions, A-64 conditional, A-5, A-58, A-66 unconditional, A-57 JV instruction, A-3, A-5, A-26, A-51, A-58, A-66 JVT
INDEX map, A-2 reserved, A-3, A-52 Operand types, See data types Operands, addressing, 4-12 Operating modes, 2-12 See also 1-Mbyte mode, 64-Kbyte mode OR instruction, A-2, A-33, A-49, A-54, A-61 ORB instruction, A-2, A-33, A-49, A-54, A-61 Oscillator and powerdown mode, 12-7 external crystal, 11-6 on-chip, 11-5 Overflow (V) flag, A-4, A-5, A-25, A-26 Overflow-trap (VT) flag, A-4, A-5, A-11, A-26, A-27 P P1.
8XC196NP, 80C196NU USER’S MANUAL Power consumption, reducing, 2-12, 12-7 Powerdown mode, 2-12, 12-7–12-12 circuitry, external, 12-11 controlling, 13-15 disabling, 12-6, 12-7 enabling, 12-7 entering, 12-6, 12-7 exiting, 12-8, 12-11 with EXTINT, 12-8–12-12 with RESET#, 12-8 Prefetch queue, 2-5, 5-23 Priority encoder, 6-4 Priority, instruction fetch versus data fetch, 5-23 Processor status word‚ See PSW Product information, ordering, 1-6 Program counter‚ See PC Program memory, 5-2, 5-5, 5-25 PSW, 2-4, 4-13, 6
INDEX See also windows Register RAM and idle mode, 12-5 and powerdown mode, 12-7 Registers ACC_0x, 3-4 ACC_STAT, 3-5 allocating, 4-12 EPA_MASK, 10-3 EPA_PEND, 10-3 EP_DIR, 7-12, 7-14, 7-16, 7-17 EP_MODE, 7-12, 7-14, 7-16, 7-17, 7-18 EP_PIN, 7-12, 7-14, 7-16, 7-17 EP_REG, 7-12, 7-16, 7-17, 7-18 considerations, 7-18 INT_MASK, 6-3, 6-10, 6-14, 8-2, 10-3, 12-2 INT_MASK1, 6-3, 6-10, 6-14, 10-3, 12-3 INT_PEND, 6-3, 6-4, 6-15, 8-2, 10-3, 12-3 INT_PEND1, 6-4, 6-15, 10-3, 12-3 naming conventions, 1-4 P1_DIR, 10-3 P
8XC196NP, 80C196NU USER’S MANUAL Serial I/O port‚ See SIO port Set, defined, 1-3 SETC instruction, A-3, A-36, A-52, A-59, A-67 SFRs and idle mode, 12-5 and powerdown mode, 12-7 CPU, 5-12 table of, 5-12 peripheral, 5-7 and windows, 5-13 table of, 5-8 reserved, 4-12, 5-9 with indirect or indexed operations, 4-12, 5-9 with read-modify-write instructions, 5-7 Shift instructions, A-59, A-66 SHL instruction, A-3, A-37, A-47, A-59, A-66 SHLB instruction, A-3, A-37, A-47, A-59, A-66 SHLL instruction, A-3, A-38, A-
INDEX W T1DIR, 10-2, B-11 T2CLK, 10-2, B-11 T2CONTROL, C-51, C-54 T2DIR, 10-2, B-11 Technical support, 1-11 Terminology, 1-3 TIJMP instruction, A-2, A-44, A-51, A-57, A-64 Timer/counters, 2-11, 10-5, 10-6 and PWM, 10-12, 10-13, 10-14, 10-15 cascading, 10-6 configuring pins, 10-2 count rate, 10-6 resolution, 10-6 SFRs, 10-3 See also EPA TIMER1, C-51, C-54 TIMER2, C-51, C-54 Timing HLDA#, 13-30 HOLD#, 13-30 instruction execution, A-60–A-61 internal, 2-7, 2-9 interrupt latency, 6-7–6-10, 6-23 PTS cycles, 6-1
8XC196NP, 80C196NU USER’S MANUAL and SIO baud rate, 8-12, 8-13 hardware connections, 11-6, 11-7 XTAL2, 11-2, B-12 hardware connections, 11-6, 11-7 Y y, defined, 1-4 Z Zero (Z) flag, A-4, A-5, A-22, A-23, A-24, A-25, C-34 Index-12
