Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual September 2006 Order Number: 252480-006US
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—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Contents 1.0 Introduction ............................................................................................................ 26 1.1 About This Document......................................................................................... 26 1.1.1 How to Read This Document .................................................................... 26 1.2 Other Relevant Documents .....................................
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 3.4 3.5 3.6 Data Cache .......................................................................................................60 3.4.1 Data Cache Overview ..............................................................................60 3.4.2 Cacheability ...........................................................................................63 3.4.3 Reconfiguring the Data Cache as Data RAM ..........................
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 3.7 3.8 3.9 3.6.11.2 SELDCSR JTAG Register........................................................... 103 3.6.11.3 DBGTX JTAG Command ........................................................... 105 3.6.11.4 DBGTX JTAG Register .............................................................. 105 3.6.11.5 DBGRX JTAG Command ........................................................... 106 3.6.11.6 DBGRX JTAG Register........
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 3.9.1 3.9.2 3.9.3 3.9.4 3.10 Interrupt Latency.................................................................................. 159 Branch Prediction.................................................................................. 160 Addressing Modes ................................................................................. 160 Instruction Latencies .............................................................
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 Initializing PCI Controller Configuration and Status Registers for Data Transactions .. 219 6.3.1 Example: AHB Memory Base Address Register, AHB I/O Base Address Register, and PCI Memory Base Address Register .............................................................................................. 220 6.3.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 6.14.2.11DMA Control Register............................................................... 265 6.14.2.12AHB Memory Base Address Register........................................... 266 6.14.2.13AHB I/O Base Address Register ................................................. 266 6.14.2.14PCI Memory Base Address Register............................................ 267 6.14.2.15AHB Doorbell Register..........................
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 8.9 8.10 9.0 Register Descriptions ....................................................................................... 319 8.9.1 Timing and Control Registers for Chip Select 0 ......................................... 319 8.9.2 Timing and Control Registers for Chip Select 1 ......................................... 319 8.9.3 Timing and Control Registers for Chip Select 2 .........................................
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 11.3 11.2.1 Monitored Events South AHB and North AHB ............................................ 375 11.2.2 Monitored SDRAM Events....................................................................... 377 11.2.3 Cycle Count ......................................................................................... 377 Register Descriptions...................................................................................
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 14.4.9 Timer Status........................................................................................ 415 15.0 Ethernet MAC A ..................................................................................................... 416 15.1 Ethernet Coprocessor....................................................................................... 417 15.1.1 Ethernet Coprocessor APB Interface ............................
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 15.2.45Unicast Address 6 ................................................................................. 444 15.2.46Core Control ........................................................................................ 444 16.0 Ethernet MAC B ...................................................................................................... 446 17.0 High-Speed Serial Interfaces ........................................
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 18.5.3 18.5.4 18.5.5 18.5.6 18.5.7 18.5.8 18.5.9 18.5.2.5 Sent Stall (SST)...................................................................... 484 18.5.2.6 Force Stall (FST)..................................................................... 484 18.5.2.7 Receive FIFO Not Empty (RNE) ................................................. 484 18.5.2.8 Setup Active (SA) ..................................................
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 18.5.9.1 Receive FIFO Service (RFS) ...................................................... 498 18.5.9.2 Receive Packet Complete (RPC)................................................. 498 18.5.9.3 Bit 2 Reserved ........................................................................ 498 18.5.9.4 Bit 3 Reserved ........................................................................ 498 18.5.9.5 Sent Stall (SST) ..........
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 18.5.15.6 Bit 5 Reserved...................................................................... 511 18.5.15.7 Bit 6 Reserved...................................................................... 511 18.5.15.8 Transmit Short Packet (TSP) .................................................. 511 18.5.16 UDC Endpoint 14 Control/Status Register (UDCCS14).............................. 512 18.5.16.1 Receive FIFO Service (RFS) .....
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 18.5.27.1 Endpoint 9 Byte Count (BC[7:0])............................................. 526 18.5.28 UDC Byte Count Register 12 (UBCR12) .................................................. 527 18.5.28.1 Endpoint 12 Byte Count (BC[7:0]) ........................................... 527 18.5.29 UDC Byte Count Register 14 (UBCR14) .................................................. 528 18.5.29.1 Endpoint 14 Byte Count (BC[7:0]) ..
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 21.3 21.4 21.5 Functional Description...................................................................................... 557 AHB Interface ................................................................................................. 558 21.4.1 Queue Control ..................................................................................... 559 21.4.2 Queue Status.................................................
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Initiated PCI TYPE 0 Configuration Read Cycle ............................................................ 227 Initiated PCI Type-0 Configuration Write Cycle ........................................................... 228 Initiated PCI Type-1 Configuration Read Cycle ...
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 T1 Transmit Frame................................................................................................. 448 T1 Receive Frame .................................................................................................. 448 E1 Transmit Frame.................................................................................................
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 70 71 69 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 TX RX Control Register (TXRXCTRL) ............................................................................98 Normal RX Handshaking ............................................................................................
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 Pipelines and Pipe Stages ........................................................................................ 169 Network Processor Functions ................................................................
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 Processors’ with Ethernet Interface ........................................................................... 436 Ethernet MAC B Registers ........................................................................................ 436 Processors with HSS ..................................................................
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Revision History Date Revision Description 1. 2. 3. 4. 006 Added the 533MHz IXP423 to Figure 2 Updated Table 3.1.1.1, Table 3.8.2.1, and the note for Table 126 Updated Section 12.1 Added clarifying information regarding the MDI Interface to Section 15.1.3, Section 15.2.46, and Table 153 5. Added additional description information to bit 3 of Table 124 6.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor— Date Revision Description 003 Incorporated specification changes, specification clarifications and document changes from the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Specification Update (252702-003). 1. Added Section 2.5, AHB Queue Manager 2. Updated Ethernet MAC A and High-Speed Serial Interfaces sections. 3. Added footnote to Table 1, Processor Features 4.
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 25
Intel® IXP42X product line and IXC1100 control plane processors—Introduction 1.0 Introduction 1.1 About This Document This document is the main reference for the external architecture of the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor. 1.1.1 How to Read This Document Familiarity with ARM* Version 5TE Architecture is necessary in order to understand some aspects of this document.
Introduction—Intel® IXP42X product line and IXC1100 control plane processors 1.3.2 Acronyms and Terminology Table 1. Acronyms and Terminology Acronym/ Terminology Description AAL ATM Adaptation Layers AES Advanced Encryption Standard AHB Advanced High-Performance Bus APB Advanced Peripheral Bus API Application Program Interface ARBS South Arbiter Assert The logically active value of a signal or bit.
Intel® IXP42X product line and IXC1100 control plane processors—Introduction Table 1.
Introduction—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 29
Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line 2.0 Overview of Product Line The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor contain an ARM* V5TE-compliant microprocessor referred to as the Intel XScale® Processor. The Intel® IXP42X product line and IXC1100 control plane processors are designed with Intel 0.18-micron production semiconductor process technology.
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors Figure 1. Intel® IXP425 Network Processor Block Diagram HSS-1 HSS-0 UTOPIA 2 WAN/Voice NPE UTOPIA (Max 24 xDSL PHYs) AAL, HSS, HDLC Ethernet NPE A MII-0 Ethernet MAC Ethernet NPE B MII-1 Ethernet MAC SHA-1/MD5, DES/3DES, AES UART Interrupt 921Kbaud Controller North AHB Arbiter AHB/APB Bridge PMU (AHB) SDRAM Controller 8 - 256 MB 32-Bit South AHB Arbiter 133.
Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line Figure 2. Intel® IXP423 Network Processor Block Diagram HSS-1 HSS-0 UTOPIA-2 WAN/Voice NPE UTOPIA (Max 24 xDSL PHYs) AAL, HSS, HDLC Ethernet NPE A MII-0 Ethernet MAC Ethernet NPE B MII-1 Ethernet MAC UART Interrupt 921Kbaud Controller North AHB Arbiter AHB/APB Bridge PMU (AHB) SDRAM Controller 8 - 256 MB 32-Bit South AHB Arbiter 133.
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors Figure 3. Intel® IXP422 Network Processor Block Diagram Ethernet NPE A MII-0 Ethernet MAC 133.32 MHz x 32 bits North Advance High-Performance Bus Queue Status Bus Ethernet NPE B MII-1 Ethernet MAC SHA-1/MD5, DES, 3DES, AES UART Interrupt 921Kbaud Controller North/South AHB Bridge Timers AHB/APB Bridge 66.
Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line Figure 4. Intel® IXP421 Network Processor Block Diagram HSS-1 HSS-0 UTOPIA 2 WAN/Voice NPE UTOPIA (Max 4 xDSL PHYs) AAL, HSS 133.32 MHz x 32 bits North Advance High-Performance Bus Queue Status Bus Ethernet NPE A MII-0 Ethernet MAC UART Interrupt 921Kbaud Controller North/South AHB Bridge Timers AHB/APB Bridge 66.
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors Figure 5. Intel® IXP420 Network Processor and Intel® IXC1100 Control Plane Processor Block Diagram Ethernet NPE A MII-0 Ethernet MAC 133.32 MHz x 32 bits North Advance High-Performance Bus Queue Status Bus Ethernet NPE B MII-1 North AHB Arbiter Ethernet MAC UART Interrupt 921Kbaud Controller North/South AHB Bridge Timers AHB/APB Bridge 66.
Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line The IXP42X product line and IXC1100 control plane processors have been equipped to efficiently handle audio processing through the support of 16-bit data types and 16-bit operations. These audio-coding enhancements center around multiply and accumulate operations which accelerate many of the audio filter operations. 2.1.
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors 2.1.1.3 Memory Management The Intel XScale processor implements the Memory Management Unit (MMU) Architecture specified in the ARM Architecture Reference Manual. The MMU provides access protection and virtual-to-physical address translation. The MMU Architecture also specifies the caching policies for the instruction cache and data cache.
Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line 2.1.1.7 Intel XScale® Processor Performance Monitoring Two performance-monitoring counters have been added to the Intel XScale processor that can be configured to monitor various events in the Intel XScale processor. These events allow a software developer to measure cache efficiency, detect system bottlenecks, and reduce the overall latency of programs.
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors 2.3 Internal Bus The internal bus architecture of the Intel XScale processor is designed to allow parallel processing to occur and isolate bus utilization based on particular traffic patterns. The bus is segmented into three major buses: the North AHB, the South AHB, and the APB. The North AHB is a 133.32 MHz, 32-bit bus that can be mastered by the WAN NPE or both of the Ethernet NPEs.
Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line communicated to the NPEs via the flag bus. Combined queue status for queues 32-63 are communicated to the NPEs via the event bus. The two interrupts, one for queues 031 and one for queues 32-63, provide status interrupts to the Intel XScale processor. For more information on the AHB Queue Manager, see Section 21.0, “AHB Queue Manager (AQM)” on page 556. 2.
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors The memory controller only supports 32-bit memory. If a x16 memory chip is used, a minimum of two memory chips would be required to facilitate the 32-bit interface required by the IXP42X product line and IXC1100 control plane processors. A maximum of four SDRAM memory chips may be attached to the processors. The memory controller internally interfaces to the North AHB and South AHB with independent peripherals.
Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line 2.12 Universal Asynchronous Receiver Transceiver The UART interfaces are 16550-compliant UARTs with the exception of transmit and receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 UART specification. The interface can be configured to support speeds from 1,200 baud to 921 Kbaud.
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors • Watch-Dog Timer • Timestamp Timer • Two general-purpose timers For more information on the timers, see Section 14.0, “Timers” on page 408. 2.16 JTAG Testability is supported on the IXP42X product line and IXC1100 control plane processors through the Test Access Port (TAP) Controller implementation, which is based on IEEE 1149.1 (JTAG) Standard Test Access Port and Boundary-Scan Architecture.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.0 Intel XScale® Processor This chapter provides functional descriptions of the Intel XScale® Processor. 3.1 Memory Management Unit This section describes the memory management unit implemented in Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors The attributes associated with a particular region of memory are configured in the memory management page table and control the behavior of accesses to the instruction cache, data cache, mini-data cache, and the write buffer. These attributes are ignored when the MMU is disabled.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.1.1.2.2 Details on Data Cache and Write Buffer Behavior If the MMU is disabled, all data accesses will be non-cacheable and non-bufferable. This is the same behavior as when the MMU is enabled and a data access uses a descriptor with X, C, and B all set to 0. The X, C, and B bits determine when the processor should place new data into the Data Cache. The cache places data into the cache in lines (also called blocks).
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 4. Data Cache and Buffer Behavior When X = 1 CB Cacheable Bufferable Write Policy Line Allocation Policy Notes 0 0 - - - - Unpredictable -- do not use 0 1 N Y - - Writes will not coalesce into buffers1 1 0 (Mini Data Cache) - - - Cache policy is determined by MD field of Auxiliary Control register2 1 1 Y Y Write Back Read/Write Allocate Notes: 1.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 6. Valid MMU and Data/Mini-Data Cache Combinations MMU Data/mini-data Cache Off Off On Off On On 3.1.3 MMU Control 3.1.3.1 Invalidate (Flush) Operation The entire instruction and data TLB can be invalidated at the same time with one command or they can be invalidated separately. An individual entry in the data or instruction TLB can also be invalidated.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 1. Enabling the MMU ; This routine provides software with a predictable way of enabling the MMU. ; After the CPWAIT, the MMU is guaranteed to be enabled. Be aware ; that the MMU will be enabled sometime after MCR and before the instruction ; that executes after the CPWAIT.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 2. Locking Entries into the Instruction TLB ; R1, R2 and R3 contain the virtual addresses to translate and lock into ; the instruction TLB. ; The value in R0 is ignored in the following instruction.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 3.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Only entries 0 through 30 can be locked in either TLB; entry 31can never be locked. If the lock pointer is at entry 31, a lock operation will update the TLB entry with the translation and ignore the lock. In this case, the round-robin pointer will stay at entry 31. Figure 7.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors A fetched line will be written into the cache if it is cacheable. Code is designated as cacheable when the Memory Management Unit (MMU) is disabled or when the MMU is enable and the cacheable (C) bit is set to 1 in its corresponding page. See “Memory Management Unit” on page 44 for a discussion on page attributes. Note that an instruction fetch may “miss” the cache but “hit” one of the fetch buffers.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor • A fetch buffer is allocated • The instruction cache sends a fetch request to the external bus. This request is for a 32-byte line. • Instructions words are returned back from the external bus, at a maximum rate of 1 word per core cycle.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 4.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 5. Enabling the Instruction Cache ; Enable the ICache MRC P15, 0, R0, C1, C0, 0 ; Get the control register ORR R0, R0, #0x1000 ; set bit 12 -- the I bit MCR P15, 0, R0, C1, C0, 0 ; Set the control register CPWAIT The entire instruction cache along with the fetch buffers are invalidated by writing to coprocessor 15, register 7. (See Table 18, “Cache Functions” on page 81 for the exact command.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors As a result: no fetches of cacheable code should occur while locking instructions into the cache. • The code being locked into the cache must be cacheable • The instruction cache must be enabled and invalidated prior to locking down lines. Failure to follow these requirements will produce unpredictable results when accessing the instruction cache.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 7. Locking Code into the Cache lockMe: ; This is the code that will be locked into the cache mov r0, #5 add r5, r1, r2 . . . lockMeEnd: . . .
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Figure 10. BTB Entry DATA TAG Branch Address[31:9,1] History Bits[1:0] Target Address[31:1] The BTB takes the current instruction address and checks to see if this address is a branch that was previously seen. The BTB uses bits [8:2] of the current address to read out the tag and then compares this tag to bits [31:9,1] of the current instruction address.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor A new entry is stored into the BTB when the following conditions are met: • The branch instruction has executed • The branch was taken • The branch is not currently in the BTB The entry is then marked valid and the history bits are set to WT. If another valid branch exists at the same entry in the BTB, it will be evicted by the new branch.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors a cacheable write miss when write allocate is specified by its page attribute. Page attribute bits determine whether a line gets allocated into the data cache or mini-data cache. Figure 12. Data Cache Organization Set 31 way 0 way 1 Example: 32-Kbyte cache 32 bytes (cache line) Set Index This example shows Set 0 being selected by the set index.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Figure 13. Mini-Data Cache Organization Example: 2K byte cache Set 31 way 0 way 1 32 bytes (cache line) Set Index This example shows Set 0 being selected by the set index.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors caching is specified for that area of memory. If the cache does not contain the requested data, the access ‘misses’ the cache, and the sequence of events that follows depends on the configuration of the cache, the configuration of the MMU and the page attributes, which are described in “Cacheability” on page 63. The data/mini-data cache is still accessed even though it is disabled.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor If there is no outstanding fill request for that line, the current store request is placed in the fill buffer and a 32-byte external memory read request is made. If the pending buffer or fill buffer is full, the Intel XScale processor will stall until an entry is available. 2. The 32-bytes of data can be returned back to the Intel XScale processor in any word order, i.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors The data cache and mini-data cache are protected by parity to ensure data integrity; there is one parity bit per byte of data. (The tags are NOT parity protected.) When a parity error is detected on a data/mini-data cache access, a data abort exception occurs. Before servicing the exception, hardware will set bit 10 of the Fault Status Register register.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor A simple software routine is used to globally clean the data cache. It takes advantage of the line-allocate data cache operation, which allocates a line into the data cache. This allocation evicts any cache dirty data back to external memory. Example 9 shows how data cache can be cleaned.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 9. Global Clean Operation ; ; ; ; ; Global Clean/Invalidate THE DATA CACHE R1 contains the virtual address of a region of cacheable memory reserved for this clean operation R0 is the loop count; Iterate 1024 times which is the number of lines in the data cache ;; Macro ALLOCATE performs the line-allocation cache operation on the ;; address specified in register Rx.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor The line-allocate operation does not require physical memory to exist at the virtual address specified by the instruction, since it does not generate a load/fill request to external memory. Also, the line-allocate operation does not set the 32 bytes of data associated with the line to any known value. Reading this data will produce unpredictable results.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 10. Locking Data into Data Cache ; R1 contains the virtual address of a region of memory to lock, ; configured with C=1 and B=1 ; R0 is the number of 32-byte lines to lock into the data cache. In this ; example 16 lines of data are locked into the cache. ; MMU and data cache are enabled prior to this code.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 11. Creating Data RAM ; R1 contains the virtual address of a region of memory to configure as data RAM, ; which is aligned on a 32-byte boundary. ; MMU is configured so that the memory region is cacheable. ; R0 is the number of 32-byte lines to designate as data RAM. In this example 16 ; lines of the data cache are re-configured as data RAM.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 11. Creating Data RAM MACRO ALLOCATE Rx MCR P15, 0, Rx, C7, C2, 5 ENDM MACRO DRAIN MCR P15, 0, R0, C7, C10, 4 ; drain pending loads and stores ENDM DRAIN MOV R4, #0x0 MOV R5, #0x0 MOV R2, #0x1 MCR P15,0,R2,C9,C2,0 ; Put the data cache in lock mode CPWAIT MOV R0, #16 LOOP1: ALLOCATE R1 ; Allocate and lock a tag into the data cache at ; address [R1].
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Tags can be locked into the data cache by enabling the data cache lock mode bit located in coprocessor 15, register 9. (See Table 20, “Cache Lock-Down Functions” on page 83 for the exact command.) Once enabled, any new lines allocated into the data cache will be locked down. Note that the PLD instruction will not affect the cache contents if it encounters an error while executing.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors All reads and writes to external memory occur in program order when coalescing is disabled in the write buffer. If coalescing is enabled in the write buffer, writes may occur out of program order to external memory. Program correctness is maintained in this case by comparing all store requests with all the valid entries in the fill buffer.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Unless otherwise noted, unused bits in coprocessor registers have unpredictable values when read. For compatibility with future implementations, software should not rely on the values in those bits. Table 7.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 8. LDC/STC Format when Accessing CP14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 cond 1 1 0 P U N W L Bits 31:28 24:23,21 CRd Description cond - ARM condition codes - P, U, W - specifies 1 of 3 addressing modes identified by addressing mode 5 in the ARM* Architecture Reference Manual. - N - should be 0 for CP14 coprocessors.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 9. 3.5.1.1 CP15 Registers (Sheet 2 of 2) Register (CRn) Opcode_2 Access Description 11 - 12 - Unpredictable Reserved 13 0 Read / Write Process ID (PID) 14 0 Read / Write Breakpoint Registers 15 0 Read / Write (CRm = 1) CP Access Register 0: ID and Cache Type Registers Register 0 houses two read-only register that are used for part identification: an ID register and a cache type register.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 11. Cache Type Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 0 0 0 0 1 0 1 1 0 0 0 Dsize 1 0 1 0 1 0 0 0 8 7 6 Isize 5 4 3 2 1 0 1 0 1 0 1 0 reset value: As Shown Bits Description Read-as-Zero / Write Ignored Reserved 28:25 Read / Write Ignored Cache class = 0b0101 The caches support locking, write back and round-robin replacement.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 12.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 13.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.5.1.4 Register 3: Domain Access Control Register Table 15. Domain Access Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 9 8 D4 7 6 D3 5 4 3 D2 2 D1 1 0 D0 reset value: unpredictable Bits 31:0 3.5.1.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.5.1.7 Register 6: Fault Address Register Table 17. Fault Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fault Virtual Address reset value: unpredictable Bits Access 31:0 3.5.1.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor The line-allocate command allocates a tag into the data cache specified by bits [31:5] of Rd. If a valid dirty line (with a different MVA) already exists at this location it will be evicted. The 32 bytes of data associated with the newly allocated line are not initialized and therefore will generate unpredictable results if read.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 20 shows the command for locking down entries in the instruction and data cache. The entry to lock in the instruction cache is specified by the virtual address in Rd. The data cache locking mechanism follows a different procedure than the instruction cache. The data cache is placed in lock down mode such that all subsequent fills to the data cache result in that line being locked in, as controlled by Table 21.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 22. 3.5.1.12 TLB Lockdown Functions Function opcode_2 CRm Data Instruction Translate and Lock D TLB entry 0b000 0b1000 MVA MCR p15, 0, Rd, c10, c8, 0 Unlock I TLB 0b001 0b0100 Ignored MCR p15, 0, Rd, c10, c4, 1 Unlock D TLB 0b001 0b1000 Ignored MCR p15, 0, Rd, c10, c8, 1 Register 11-12: Reserved These registers are reserved. Reading and writing them yields unpredictable results. 3.5.1.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.5.1.15 Register 14: Breakpoint Registers The Intel XScale processor contains two instruction breakpoint address registers (IBCR0 and IBCR1), one data breakpoint address register (DBR0), one configurable data mask/address register (DBR1), and one data breakpoint control register (DBCON). The Intel XScale processor also supports a 256-entry, trace buffer that records program execution information.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 12. Disallowing access to CP0 ;; The following code clears bit 0 of the CPAR. ;; This will cause the processor to fault if software ;; attempts to access CP0. Table 26.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.5.2.1 Performance Monitoring Registers The performance monitoring unit contains a control register (PMNC), a clock counter (CCNT), interrupt enable register (INTEN), overflow flag register (FLAG), event selection register (EVTSEL) and four event counters (PMN0 through PMN3).
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 30. Table 31. Clock and Power Management Function Data Instruction Read CCLKCFG ignored MRC p14, 0, Rd, c6, c0, 0 Write CCLKCFG CCLKCFG value MCR p14, 0, Rd, c6, c0, 0 CCLKCFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCLKCFG reset value: unpredictable 3.5.2.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors • Debug Handler SW requirements and suggestions 3.6.1 3.6.2 Definitions Debug handler: Debug handler is event handler that runs on IXP42X product line and IXC1100 control plane processors, when a debug event occurs. Debugger: The debugger is software that runs on a host system outside of IXP42X product line and IXC1100 control plane processors.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.6.3.1 Halt Mode When the debug unit is configured for halt mode, the reset vector is overloaded to serve as the debug vector. A new processor mode, DEBUG mode (CPSR[4:0] = 0x15), is added to allow debug exceptions to be handled similarly to other types of ARM exceptions. When a debug exception occurs, the processor switches to debug mode and redirects execution to a debug handler, via the reset vector.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 33.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.6.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR) The Vector Trap bits allow instruction breakpoints to be set on exception vectors without using up any of the breakpoint registers. When a bit is set, it acts as if an instruction breakpoint was set up on the corresponding exception vector. A debug exception is generated before the instruction in the exception vector executes.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors • Exception vector trap • Trace-buffer full break When a debug exception occurs, the processor’s actions depend on whether the debug unit is configured for Halt mode or Monitor mode. Table 34 shows the priority of debug exceptions relative to other processor exceptions. Table 34. Event Priority Event Reset 3.6.5.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor • CPSR[5] = 0 • CPSR[6] = 1 • CPSR[7] = 1 • PC = 0x0 Note: When the vector table is relocated (CP15 Control Register[13] = 1), the debug vector is relocated to 0xffff0000. Following a debug exception, the processor switches to debug mode and enters SDS, which allows the following special functionality: • All events are disabled. SWI or undefined instructions have unpredictable results.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors • Instruction breakpoint • BKPT instruction The processor ignores vector traps during monitor mode. When an exception occurs in monitor mode, the processor takes the following actions: • Disables the trace buffer • Sets DCSR.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 35.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 37.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor On a data breakpoint, the processor generates a debug exception and re-directs execution to the debug handler before the next instruction executes. The processor reports the data breakpoint by setting the DCSR.MOE to 0b010. The link register of a data breakpoint is always PC (of the next instruction to execute) + 4, regardless of whether the processor is configured for monitor mode or halt mode. 3.6.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.8.1 RX Register Ready Bit (RR) The debugger and debug handler use the RR bit to synchronize accesses to RX. Normally, the debugger and debug handler use a handshaking scheme that requires both sides to poll the RR bit.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.6.8.2 Overflow Flag (OV) The Overflow flag is a sticky flag that is set when the debugger writes to the RX register while the RR bit is set. The flag is used during high-speed download to indicate that some data was lost.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.8.5 Conditional Execution Using TXRXCTRL All of the bits in TXRXCTRL are placed such that they can be read directly into the CC flags using an MCR instruction. To simplify the debug handler, the TXRXCTRL register should be read using the following instruction: mrc p14, 0, r15, C14, C0, 0 This instruction will directly update the condition codes in the CPSR.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.6.10 Receive Register (RX) The RX register is the receive buffer used by the debug handler to get data sent by the debugger through the JTAG interface. Table 44.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.11.2 SELDCSR JTAG Register Placing the “SELDCSR” JTAG instruction in the JTAG IR, selects the DCSR JTAG Data register (Figure 15), allowing the debugger to access the DCSR, generate an external debug break, set the hold_rst signal, which is used when loading code into the instruction cache during reset. Figure 15.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Figure 16. SELDCSR Data Register DCSR 0 0 1 0 2 1 0 Capture_DR DBG_SR TDI 35 34 3 ignored TDO Update_DR DBG_REG 34 33 TCK 2 1 0 DBG.HLD_RST DBG.BRK DBG.DCSR 3.6.11.2.1 DBG.HLD_RST The debugger uses DBG.HLD_RST when loading code into the instruction cache during a processor reset. Details about loading code into the instruction cache are in “Downloading Code in ICache” on page 116.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors A debugger sets an external debug break by scanning data into the DBG_SR with DBG_SR[2] set and the desired value to set the DCSR JTAG writable bits in DBG_SR[34:3]. Once an external debug break is set, it remains set internally until a debug exception occurs. In Monitor mode, external debug breaks detected during abort mode are pended until the processor exits abort mode.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor A Capture_DR loads the TX register value into DBG_SR[34:3] and TXRXCTRL[28] into DBG_SR[0]. The other bits in DBG_SR are loaded as shown in Figure 33. The captured TX value is scanned out during the Shift_DR state. Data scanned in is ignored on an Update_DR. A ‘1’ captured in DBG_SR[0] indicates the captured TX data is valid.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors The captured data is scanned out during the Shift_DR state. Care must be taken while scanning in data. While polling TXRXCTRL[31], incorrectly setting DBG_SR[35] or DBG_SR[1] may cause unpredictable behavior following an Update_DR. Update_DR parallel loads DBG_SR[35:1] into DBG_REG[34:0].
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Figure 20. DBGRX Data Register RX TXRXCTRL[31] 0 0 1 2 1 Capture_DR DBG_SR TDI 35 34 3 TDO 0 DBG.RR cleared by RX Write Logic Update_DR DBG_REG 34 33 2 1 TCK 0 DBG.FLUSH DBG.D DBG.RX DBG.V 3.6.11.6.3 DBG.RR The debugger uses DBG.RR as part of the synchronization that occurs between the debugger and debug handler for accessing RX. This bit contains the value of TXRXCTRL[31] after a Capture_DR.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.11.6.5 DBG.RX DBG.RX is written into the RX register based on the output of the RX Write Logic. Any data that needs to be sent from the debugger to the processor must be loaded into DBG.RX with DBG.V set to 1. DBG.RX is loaded from DBG_SR[34:3] when the JTAG enters the Update_DR state. DBG.RX is written to RX following an Update_DR when the RX Write Logic enables the RX register. 3.6.11.6.6 DBG.D DBG.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 46. CP 14 Trace Buffer Register Summary CP14 Register Number Register Name 11 Trace Buffer Register (TBREG) 12 Checkpoint 0 Register (CHKPT0) 13 Checkpoint 1 Register (CHKPT1) Any access to the trace buffer registers in User mode will cause an undefined instruction exception. Specifying registers which do not exist has unpredictable results. 3.6.12.1.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.12.1.2 Trace Buffer Register (TBREG) The trace buffer is read through TBREG, using MRC and MCR. Software should only read the trace buffer when it is disabled. Reading the trace buffer while it is enabled, may cause unpredictable behavior of the trace buffer. Writes to the trace buffer have unpredictable results.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 49. Message Byte Formats Message Name Message Byte Type Message Byte Format # Address Bytes Exception exception 0b0VVV CCCC 0 non-exception 0b1000 CCCC 0 non-exception 0b1100 CCCC 0 Direct Branch1 Check-Pointed Direct Branch1 Indirect Branch 2 non-exception 0b1001 CCCC 4 Check-Pointed Indirect Branch2 non-exception 0b1101 CCCC 4 Roll-over non-exception 0b1111 1111 0 Notes: 1.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors of the instruction not matching the CC flags. In the case of back-to-back branches the word count would be 0 indicating that no instructions executed after the last branch and before the current one. A rollover message is used to keep track of long traces of code that do not have control flow changes.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Figure 22. Indirect Branch Entry Address Byte Organization target[31:24] Trace buffer is read by software in this direction. The message byte is always the last of the 5 bytes in the entry to be read. target[23:16] target[15:8] target[7:0] indirect br msg 3.6.13.2 Trace Buffer Usage IXP42X product line and IXC1100 control plane processors’ trace buffer is 256 bytes in length.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors The trace buffer must be initialized prior to its initial usage, then again prior to each subsequent usage. Initialization is done be reading the entire trace buffer.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.6.14 Downloading Code in ICache On IXP42X product line and IXC1100 control plane processors, a 2-K mini instruction cache — physically separate from the 32-K main instruction cache — can be used as an on-chip instruction RAM. An external host can download code directly into either instruction cache through JTAG. In addition to downloading code, several cache functions are supported.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.14.2 LDIC JTAG Data Register The LDIC JTAG Data Register is selected when the LDIC JTAG instruction is in the JTAG IR. An external host can load and invalidate lines in the instruction cache through this data register. Figure 24.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.6.14.3 LDIC Cache Functions The IXP42X product line and IXC1100 control plane processors support four cache functions that can be executed through JTAG. Two functions allow an external host to download code into the main instruction cache or the mini instruction cache through JTAG. Two additional functions are supported to allow lines to be invalidated in the instruction cache.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Figure 25. Format of LDIC Cache Functions VA[31:5] Invalidate IC Line 0 0 0 0 0 0 32 31 Invalidate Mini IC x x 5 0 ... x 0 0 0 0 0 1 32 31 P 2 5 2 0 Data Word 7 . . . Load Main IC (CMD = 0b010) - indicates first bit shifted in - indicates last bit shifted in Data Word 0 P and Load Mini IC (CMD = 0b011) VA[31:5] 32 31 0 0 0 5 CMD 2 0 All packets are 33 bits in length.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor During a cold reset (in which both a processor reset and a JTAG reset occurs) it can be guaranteed that the instruction cache will be invalidated since the JTAG reset takes the processor out of any of the modes listed above. During a warm reset, if a JTAG reset does not occur, the instruction cache is not invalidated by reset when any of the above modes are active.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 2. Load the SELDCSR JTAG instruction into JTAG IR and scan in a value to set the Halt Mode bit in DCSR and to set the hold_rst signal. For details of the SELDCSR, refer to “SELDCSR JTAG Register” on page 103. 3. After hold_rst is set, de-assert the Reset pin. Internally the processor remains held in reset. 4. After Reset is de-asserted, wait 2030 TCKs. 5. Load the LDIC JTAG instruction into JTAG IR. 6.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Figure 27.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.14.5 Dynamically Loading IC After Reset An external host can load code into the instruction cache “on the fly” or “dynamically.” This occurs when the host downloads code while the processor is not being reset. However, this requires strict synchronization between the code running on the IXP42X product line and IXC1100 control plane processors and the external host.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor that line. Failure to invalidate a line prior to writing it may cause unpredictable operation by the processor. • When the host completes its download, the host must wait a minimum of 15 TCKs, then switch the JTAG IR to DBGRX, and complete the handshaking (by scanning in a value that sets DBG_SR[35]). This clears TXRXCTL[31] and allows the debug handler code to exit the polling loop.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 51. Debug-Handler Code to Implement Synchronization During Dynamic Code Download # Before the download can start, all outstanding instruction fetches must complete. # The MCR invalidate IC by line function serves as a barrier instruction in # the core. All outstanding instruction fetches are guaranteed to complete before # the next instruction executes.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Another possibility is for a more complete debug handler is downloaded during reset. The debug handler may support some operations, such as read memory, write memory, etc. However, other operations, such as reading or writing a group of CP register, can be downloaded dynamically.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors While the processor is still in reset, the debugger should set up the DCSR to trap the reset vector. This causes a debug exception to occur immediately when the processor comes out of reset. Execution is redirected to the debug handler allowing the debugger to perform any necessary initialization. The reset vector trap is the only debug exception that can occur with debug globally disabled (DCSR[31]=0).
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor For the indirect branch cases, a temporary scratch register may be necessary to hold intermediate values while computing the final target address. DBG_r13 can be used for this purpose (see “Debug Handler Restrictions” on page 128 for restrictions on DBG_r13 usage). 3.6.15.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.6.15.2.3 Dynamic Debug Handler On the IXP42X product line and IXC1100 control plane processors, the debug handler and override vector tables reside in the 2-Kbyte, mini instruction cache, separate from the main instruction cache. A “static” Debug Handler is downloaded during reset.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor If the dynamic function is already downloaded in the main instruction cache, the debugger immediately downloads the address, signalling the handler to continue. The static Debug Handler only needs to support one dynamic function command. Multiple dynamic functions can be downloaded to different addresses and the debugger uses the function’s address to specify which dynamic function to execute.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors The download bit acts as a branch flag, signalling to the handler to continue with the download. This removes the need for a counter in the debug handler. The overflow flag indicates that the debugger attempted to download the next word before the debugger read the previous word.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor These actions ensure that the application program executes correctly after the debugger has been disconnected. 3.6.16 Software Debug Notes and Errata • Trace buffer message count value on data aborts: LDR to non-PC that aborts gets counted in the exception message. But an LDR to the PC that aborts does not get counted on exception message. • SW Note on data abort generation in Special Debug State.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.7 Performance Monitoring This section describes the performance monitoring facility of the IXP42X product line and IXC1100 control plane processors. The events that are monitored can provide performance information for compiler writers, system application developers and software programmers. 3.7.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 53.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 55. Performance Monitor Count Register (PMN0 - PMN3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Event Counter reset value: unpredictable Bits 31:0 3.7.2.3 Access Description 32-bit event counter - Reset to ‘0’ by PMNC register.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.7.2.4 Interrupt Enable Register (INTEN) Each counter can generate an interrupt request when it overflows. INTEN enables interrupt requesting for each counter. Table 57. Interrupt Enable Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P 3 P 2 P 1 P 0 C reset value: [4:0] = 0b00000, others unpredictable Bits 31:5 3.7.2.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 58. Overflow Flag Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P 3 P 2 P 1 P 0 C reset value: [4:0] = 0b00000, others unpredictable Bits 31:5 4 3 2 1 0 3.7.2.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 59. Event Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 evtCount3 evtCount2 9 8 7 6 evtCount1 5 4 3 2 1 0 evtCount0 reset value: unpredictable Bits 31:24 23:16 15:8 7:0 3.7.3 Access Description Read / Write Event Count 3 (evtCount3) Identifies the source of events that PMN3 counts. See Table 60 for a description of the values this field may contain.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.7.4 Performance Monitoring Events Table 60 lists events that may be monitored. Each of the Performance Monitor Count Registers (PMN0, PMN1, PMN2, and PMN3) can count any listed event. Software selects which event is counted by each PMNx register by programming the evtCountx fields of EVTSEL. Table 60.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor performance statistics could be gathered (like hit rates, number of write-backs per data cache miss, and number of times the data cache buffers fill up per request). 3.7.4.1 Instruction Cache Efficiency Mode PMN0 totals the number of instructions that were executed, which does not include instructions fetched from the instruction cache that were never executed.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.7.4.4 Data/Bus Request Buffer Full Mode The Data Cache has buffers available to service cache misses or uncacheable accesses. For every memory request that the Data Cache receives from the processor core a buffer is speculatively allocated in case an external memory request is required or temporary storage is needed for an unaligned access. If no buffers are available, the Data Cache will stall the processor core.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor • Total number of data write-back requests to external memory can be derived solely with PMN1. 3.7.4.6 Instruction TLB Efficiency Mode PMN0 totals the number of instructions that were executed, which does not include instructions that were translated by the instruction TLB and never executed.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 14. Configuring the Performance Monitor ; Configure the performance monitor with the following values: ; EVTSEL.evtCount0 = 7, EVTSEL.evtCount1 = 0 instruction cache efficiency ; INTEN.inten = 0x7 set all counters to trigger an interrupt on overflow ; PMNC.C = 1 reset CCNT register ; PMNC.P = 1 reset PMN0 and PMN1 registers ; PMNC.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 16. Computing the Results ; Assume CCNT overflowed CCNT = 0x0000,0020 ;Overflowed and continued counting Number of instructions executed = PMN0 = 0x6AAA,AAAA Number of instruction cache miss requests = PMN1 = 0x0555,5555 Instruction Cache miss-rate = 100 * PMN1/PMN0 = 5% CPI = (CCNT + 2^32)/Number of instructions executed = 2.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.8.2.2 26-Bit Architecture The Intel XScale processor does not support 26-bit architecture. 3.8.2.3 Thumb The Intel XScale processor supports the thumb instruction set. 3.8.2.4 ARM* DSP-Enhanced Instruction Set The Intel XScale® Processor implements ARM’s DSP-enhanced instruction set which is a set of instructions that boost the performance of signal processing applications.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.8.3 Extensions to ARM* Architecture The Intel XScale processor adds a few extensions to the ARM Version 5TE architecture to meet the needs of various markets and design requirements. The following is a list of the extensions which are discussed in the next sections. • A DSP coprocessor (CP0) has been added that contains a 40-bit accumulator and eight new instructions.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 62.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor MIA does not support unsigned multiplication; all values in Rs and Rm will be interpreted as signed data values. MIA is useful for operating on signed 16-bit data that was loaded into a general purpose register by LDRSH. The instruction is only executed if the condition specified in the instruction matches the condition code status. Table 64.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 65.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Access to the internal accumulator is allowed in all processor modes (user and privileged) as long bit 0 of the Coprocessor Access Register is set. (See “Register 15: Coprocessor Access Register” on page 85 for more details). The IXP42X product line and IXC1100 control plane processors implement two instructions MAR and MRA that move two ARM registers to acc0 and move acc0 to two ARM registers, respectively. Table 66.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 67.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor This instruction executes in any processor mode. 3.8.3.2 New Page Attributes The Intel XScale processor extends the page attributes defined by the C and B bits in the page descriptors with an additional X bit. This bit allows four more attributes to be encoded when X=1. These new encodings include allocating data for the mini-data cache and write-allocate caching.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 69. First-Level Descriptors 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SBZ Coarse page table base address Section base address SBZ TEX Fine page table base address Table 70.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 17. CPWAIT: Canonical Method to Wait for CP15 Update ;; The following macro should be used when software needs to be ;; assured that a CP15 update has taken effect. ;; It may only be used while in a privileged mode, because it ;; accesses CP15.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 72. Exception Summary (Sheet 2 of 2) Exception Description Exception Type1 Precise Updates FAR Lock Abort Data Y N MMU Data Data Y Y External Data Data N N Data Cache Parity Data N N Software Interrupt Software Interrupt Y N Undefined Instruction Undefined Instruction Y N Debug Events2 varies varies N Notes: 1.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 74. Processors’ Encoding of Fault Status for Prefetch Aborts FS[10,3:0]* Domain FAR Instruction MMU Exception Several exceptions can generate this encoding: - translation faults - domain faults, and - permission faults It is up to software to figure out which one occurred.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 75. Intel XScale® Processor Encoding of Fault Status for Data Aborts (Sheet 2 of 2) Priorit y Lowest Note: Sources FS[10,3:0]* Domain FAR Lock Abort This data abort occurs on an MMU lock operation (data or instruction TLB) or on an Instruction Cache lock operation.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Example 18. Shielding Code from Potential Imprecise Aborts ;; Example of code that maintains architectural state through the ;; window where an imprecise fault might occur. LD R0, [R1] ; R1 points to stall-until-complete ; region of memory NOP NOP NOP ; Code beyond this point is guaranteed not to see any aborts ; from the LD.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Example 19. Speculatively issuing PLD ;; R0 points to a node in a linked list. A node has the following layout: ;; Offset Contents ;;---------------------------------;; 0 data ;; 4 pointer to next node ;; This code computes the sum of all nodes in a list. The sum is placed into R9. ;; MOV R9, #0 ; Clear accumulator sumList: 3.8.3.4.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Maximum Interrupt Latency can be reduced by: • Ensuring that the interrupt vector and interrupt service routine are resident in the instruction cache. This can be accomplished by locking them down into the cache. • Removing or reducing the occurrences of hardware page table walks.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors • Cycle Distance from A to B The cycle distance from cycle A to cycle B is (B-A) -- that is, the number of cycles from the start of cycle A to the start of cycle B. Example: the cycle distance from cycle 3 to cycle 4 is one cycle. • Issue Latency The cycle distance from the first issue clock of the current instruction to the issue clock of the next instruction.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor the code fragment, there is a result dependency between the UMLAL instruction and the SUB instruction. In Table 77, UMLAL starts to issue at cycle 0 and the SUB issues at cycle 5. thus the Result Latency is five. Table 77.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 80.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 81.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Table 82. Multiply Implicit Accumulate Instruction Timings Mnemonic MIA Table 83.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Table 86. Table 87.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.9.4.10 Miscellaneous Instruction Timing Table 91. Exception-Generating Instruction Timings Table 92. 3.9.4.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.10.1.1 About This Section This guide assumes that you are familiar with the ARM instruction set and the C language. It consists of the following sections: • “Introduction” on page 167 — Outlines the contents of this guide. • “Processors’ Pipeline” on page 168 — This section provides an overview of IXP42X product line and IXC1100 control plane processors pipeline behavior.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.2.1.2 Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Pipeline Organization The IXP42X product line and IXC1100 control plane processors single-issue superpipeline consist of a main execution pipeline, MAC pipeline, and a memory access pipeline. These are shown in Figure 29, with the main execution pipeline shaded. Figure 29.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor While instructions are issued in-order, the main execution pipeline, memory, and MAC pipelines are not lock-stepped, and, therefore, have different execution times. This means that instructions may finish out of program order. Short ‘younger’ instructions may be finished earlier than long ‘older’ ones.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.2.2.2 Pipeline Stalls The progress of an instruction can stall anywhere in the pipeline. Several pipe stages may stall for various reasons. It is important to understand when and how hazards occur in the IXP42X product line and IXC1100 control plane processors’ pipeline. Performance degradation can be significant if care is not taken to minimize pipeline stalls. 3.10.2.3 Main Execution Pipeline 3.10.2.3.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor The ID unit decodes the instruction and specifies which registers are accessed in the RFU. Based upon this information, the RFU determines if it needs to stall the pipeline due to a register dependency. A register dependency occurs when a previous instruction is about to modify a register value that has not been returned to the RFU and the current instruction needs to access that same register.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.2.5 Multiply/Multiply Accumulate (MAC) Pipeline The Multiply-Accumulate (MAC) unit executes the multiply and multiply-accumulate instructions supported by the IXP42X product line and IXC1100 control plane processors.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor if (a + b) Code generated for the if condition without using an add instruction to set condition codes is: ;Assume r0 contains the value a, and r1 contains the value b add r0,r0,r1 cmp r0, #0 However, code can be optimized as follows making use of add instruction to set condition codes: ;Assume r0 contains the value a, and r1 contains the value b adds r0,r0,r1 The instructions that increment or decrement the loop cou
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.3.1.2 Optimizing Branches Branches decrease application performance by indirectly causing pipeline stalls. Branch prediction improves the performance by lessening the delay inherent in fetching a new instruction stream. The number of branches that can accurately be predicted is limited by the size of the branch target buffer.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor The above code segment would not incur any branch misprediction penalties and would take three cycles to execute assuming best case conditions. As can be seen, using conditional instructions speeds up execution significantly. However, the use of conditional instructions should be carefully considered to ensure that it does improve performance.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors If we make the assumptions that both paths are equally likely to be taken and that branches are mis-predicted 50% of the time, the costs of using conditional execution Vs using branches can be computed as follows: Cost of using conditional instructions: 50 50 1 + ⎛ --------- × 10⎞ + ⎛ --------- × 10⎞ = 11 ⎝ 100 ⎠ ⎝ 100 ⎠ cycles Cost of using branches: 50 50 50 1 + ⎛ --------- × 7⎞ + ⎛ --------- × 6⎞ + ⎛ --------- × 4⎞
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.10.3.2 Bit Field Manipulation The IXP42X product line and IXC1100 control plane processors shift and logical operations provide a useful way of manipulating bit fields.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors ;Multiplication of R0 mov r0, r0, LSL ;Multiplication of R0 add r0, r0, r0, by 2n #n by 2n+1 LSL #n · n m Multiplication by an integer constant that can be expressed as ( 2 + 1 ) ⋅ ( 2 ) can similarly be optimized as: ;Multiplication of r0 by an integer constant that can be ;expressed as (2n+1)*(2m) add r0, r0, r0, LSL #n mov r0, r0, LSL #m Please note that the above optimization should only be used in cases where th
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.10.4 Cache and Prefetch Optimizations This section considers how to use the various cache memories in all their modes and then examines when and how to use prefetch to improve execution efficiencies. 3.10.4.1 Instruction Cache The IXP42X product line and IXC1100 control plane processors have separate instruction and data caches.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors • Interrupt handlers • Real time clock handlers • OS critical code • Time critical application code The disadvantage to locking code into the cache is that it reduces the cache size for the rest of the program. How much code to lock is very application dependent and requires experimentation to optimize.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.10.4.2.2 Write-Through and Write-Back Cached Memory Regions Write through memory regions generate more data traffic on the bus. Therefore is not recommended that the write-through policy be used. The write back policy must be used whenever possible. However, in a multiprocessor environment it will be necessary to use a write through policy if data is shared across multiple processors.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.4.2.5 Mini-Data Cache The mini-data cache is best used for data structures, which have short temporal lives, and/or cover vast amounts of data space. Addressing these types of data spaces from the Data cache would corrupt much if not all of the Data cache by evicting valuable data. Eviction of valuable data will reduce performance.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor If the structure is not sized to a multiple of the cache line size, then the prefetch address must be advanced appropriately and will require extra prefetch instructions. Consider the following example: struct { long ia; long ib; long ic; long id; long ie; } tdata[IMAX]; ADDRESS preadd = tdata for (i=0, i
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.4.3.2 Memory Page Thrashing Memory page thrashing occurs because of the nature of SDRAM. SDRAMs are typically divided into four banks. Each bank can have one selected page where a page address size for current memory components is often defined as 4 k. Memory lookup time or latency time for a selected page address is currently two to three bus clocks.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.10.4.4.4 Bandwidth Limitations Overuse of prefetches can usurp resources and degrade performance. This happens because once the bus traffic requests exceed the system resource capacity, the processor stalls.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors int a_array[NMAX]; int b_array[NMAX]; int ix; for (i=0; i
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor struct employee { struct employee *prev; struct employee *next; int ssno; int empid; float Year2DatePay; float Year2DateTax; float Year2Date401KDed; float Year2DateOtherDed; }; 3.10.4.4.6 Cache Blocking Cache blocking techniques, such as strip-mining, are used to improve temporal locality of the data.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors for(i=0; i
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor Note the order reversal of the prefetches in relationship to the usage. If there is a cache conflict and data is evicted from the cache then only the data from the first prefetch is lost. 3.10.4.4.9 Loop Interchange As mentioned earlier, the sequence in which data is accessed affects cache thrashing. Usually, it is best to access data in a contiguous spatially address range.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.4.4.11 Prefetch to Reduce Register Pressure Pre-fetch can be used to reduce register pressure. When data is needed for an operation, then the load is scheduled far enough in advance to hide the load latency. However, the load ties up the receiving register until the data can be used.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor ldr r0, [r5] add r1, r2, r3 sub r8, r2, r3 add r6, r0, r1 mul r9, r2, r3 Note that this rearrangement may not be always possible. Consider the following example: cmp r1, #0 addne r4, r5, #4 subeq r4, r5, #4 ldr r0, [r4] cmp r0, #10 In the example above, the LDR instruction cannot be moved before the ADDNE or the SUBEQ instructions because the LDR instruction depends on the result of these instructions.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors ; all other registers are in use sub r1, r6, r7 mul r3,r6, r2 mov r2, r2, LSL #2 orr r9, r9, #0xf add r0,r4, r5 ldr r6, [r0] add r8, r6, r8 add r8, r8, #4 orr r8,r8, #0xf ; The value in register r6 is not used after this In the code sample above, the ADD and the LDR instruction can be moved before the MOV instruction. Note that this would prevent pipeline stalls if the load hits the data cache.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor sequentially should not exceed four. Also note that a preload instruction may cause a fill buffer to be used. As a result, the number of preload instructions outstanding should also be considered to arrive at the number of loads that are outstanding. Similarly, the number of write buffers also limits the number of successive writes that can be issued before the processor stalls. No more than eight stores can be issued.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors 3.10.5.1.2 Scheduling Load and Store Multiple (LDM/STM) LDM and STM instructions have an issue latency of 2-20 cycles depending on the number of registers being loaded or stored. The issue latency is typically two cycles plus an additional cycle for each of the registers being loaded or stored assuming a data cache hit.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor add sub mov r1, r2, r3 r6, r7, r8 r4, r1, LSL #2 All data processing instructions incur a two cycle issue penalty and a two-cycle result penalty when the shifter operand is a shift/rotate by a register or shifter operand is RRX. Since the next instruction would always incur a 2 cycle issue penalty, there is no way to avoid such a stall except by re-writing the assembler instruction.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Please refer to “Instruction Latencies” on page 160 to get the instruction latencies for various multiply instructions. The multiply instructions should be scheduled taking into consideration these instruction latencies. 3.10.5.4 Scheduling SWP and SWPB Instructions The SWP and SWPB instructions have a five-cycle issue latency.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor mra add mov mov r6, r2, r0, r1, r7, acc0 r2, #1 r6 r7 The MAR (MCRR) instruction has an issue latency, a result latency, and a resource latency of two cycles. Due to the two-cycle issue latency, the pipeline would always stall for one cycle following a MAR instruction. The use of the MAR instruction should, therefore, be used only where absolutely necessary. 3.10.5.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors Consider the code sample: mrs orr add r0, cpsr r0, r0, #1 r1, r2, r3 The ORR instruction above would incur a one cycle stall due to the two-cycle result latency of the MRS instruction. In the code example above, the ADD instruction can be moved before the ORR instruction to prevent this stall. 3.10.5.
Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor 3.10.7.1.1 Multiple Word Load and Store The LDM/STM instructions are one word long and let you load or store multiple registers at once. Use the LDM/STM instructions instead of a sequence of loads/stores to consecutive addresses in memory whenever possible. 3.10.7.1.
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 201
Intel® IXP42X product line and IXC1100 control plane processors—Network Processor Engines (NPE) 4.0 Network Processor Engines (NPE) The Network Processor Engines (NPE) are dedicated function processors containing hardware co-processors that are integrated into the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor. The NPEs are used to off load processing functions required by the Intel XScale® Processor.
Network Processor Engines (NPE)—Intel® IXP42X product line and IXC1100 control plane processors are difficult for a processor to implement. The type of functions implemented by the coprocessors are serialization/de-serialization, CRC checking/generation, DES/3DES, AES, SHA-1, MD-5, and HDLC bit-stuffing/de-stuffing. These coprocessors are implemented in hardware, therefore allowing the coprocessors and the Network Processor Engine core to operate in parallel.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus 5.0 Internal Bus The internal bus architecture of the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor are designed to allow parallel processing to occur and isolate bus utilization based upon particular traffic patterns. The bus is segmented into three major buses, the North AHB, the South AHB, and the APB.
Internal Bus—Intel® IXP42X product line and IXC1100 control plane processors The arbiters also have the capability to handle split transfers.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Table 96.
Internal Bus—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 207
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.0 PCI Controller The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor contains a 32-bit, 66-MHz PCI interface compatible with PCI Version 2.2. The PCI interface is capable of operating as either a host or an option (i.e., not the host).
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 30. Processors’ PCI Bus Configured as a Host PCI_REQ0 PCI_GNT0 PCI Bused Signals Intel® 82559 PCI-to-Ethernet Controller PCI_REQ1 PCI_GNT1 Intel® IXP42X Product Line / IXC1100 Control Plane Processor PCI-to-VGA Controller PCI_REQ2 PCI_GNT2 Intel® PCI-to-802.11 Controller PCI_REQ3 PCI_GNT3 PCI-to-ATA HDD Controller B1734-02 Figure 31.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller The IXP42X product line and IXC1100 control plane processors PCI Controller block diagram is given in Figure 32. Figure 32.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors target interface — in conjunction with the target interface FIFOs — will use the South AHB Master interface of the PCI Controller to provided read and write access to AHB agents, PCI Controller PCI Configuration registers (through Configuration cycles). The PCI Controller Configuration and Status Registers accessible through Target transactions will be accessed directly from the PCI-Target Interface.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller pre-fetch CSR mechanism. Refer to “PCI Controller Configured as Host” on page 213 for additional details. For PCI bus memory cycles, the PCI Initiator interface will receive requests for PCI transfer from the PCI Controller DMA channels.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors gaining access to the South AHB Master Controller’s services, then the PCI Target interface would gain access to the South AHB Master Controller’s services again, followed by the second DMA channel gaining access to the South AHB Master Controller’s services, etc. On the second level of arbitration for the South AHB Master Controller’s services, the two DMA channels will alternate for priority access.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Once the PCI controller has determined that the mode of operation is to be host, the IXP42X product line and IXC1100 control plane processors are required to configure the rest of the PCI bus. However, before the IXP42X product line and IXC1100 control plane processors can configure the rest of the PCI bus, the PCI Controller must be configured.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors (Reserved) Bus Segment Number Device Number Function Number Register Number 0 1 2 7 8 10 11 15 16 23 24 Type 1 Configuration Address Phase 31 Figure 34.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller It is also noteworthy to mention that the PCI Controller does not interpret or manipulate the contents of the Non-Pre-fetch Registers. The address, command, byte enables, and write data are passed to the PCI bus as-is. For example, I/O read and I/O write requests must be set-up such that the byte-enables are consistent with the 2 LSBs of the address in accordance with the PCI local-bus specification.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors memory transactions with no adverse side effects to reads. Only bits (31:26) would be written. Now, the IXP42X product line and IXC1100 control plane processors must read Base Address Register 0 to determine the Address Space, Address space type (memory or I/O), and any limitations to reading this address space. 6. Write a hexadecimal value of 0x00010010 to the PCI Non-Pre-fetch Access Address (PCI_NP_AD) Register.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.2 PCI Controller Configured as Option The IXP42X product line and IXC1100 control plane processors can be configured as an option function on the PCI bus. As with configuring the PCI Controller as a host functions, the IXP42X product line and IXC1100 control plane processors, functioning as an option does not require the Internal Arbiter function in the PCI Controller to be enabled.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors An access to the IXP42X product line and IXC1100 control plane processors’ PCI Controller PCI Configuration Registers occurs when the PCI_IDSEL input is asserted, the PCI command field as represented by the PCI Command/Byte enable signals is a configuration read or write, PCI_AD[1:0] = 00 indicating a type 0 configuration cycle, and the PCI Controller Target Interface is allowed to accept Type 0 Configuration Cycles by asserting
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller processors. The IXP42X product line and IXC1100 control plane processors PCI Controller can be configured to support four 16-Mbyte locations for PCI Target Memory Cycle transactions using the AHB Memory Base Address (PCI_AHBMEMBASE) register and the PCI Base Address Registers. The AHB Memory Base Address (PCI_AHBMEMBASE) register consists of four 8-bit fields.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors — BAR4 = 0xA4000000 — BAR5 = 0xA5123400 3. An external PCI device initiates a PCI bus transfer to the IXP42X product line and IXC1100 control plane processors’ BAR1. The PCI address looks like the following PCI Address = 0xA100402C. The address placed on the South AHB is 0100402C.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller • Bits 31:24 of the PCI Memory Base Address Register (PCI_PCIMEMBASE) register correspond to the first 16-Mbyte window from South AHB address 0x48000000 to 0x48FFFFFF • Bits 23:16 of the PCI Memory Base Address Register (PCI_PCIMEMBASE) register correspond to the second 16-Mbyte window from South AHB address 0x49000000 to 0x49FFFFFF • Bits 15:8 of the PCI Memory Base Address Register (PCI_PCIMEMBASE) register correspond to the t
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors The IXP42X product line and IXC1100 control plane processors are a single-function, Type 0 Configuration space when functioning as a PCI option. For detailed information on the values to program the PCI Controller Configuration and Status Registers, see the PCI Local Bus Specification, Rev. 2.2.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 1. An AHB master that wants to write a particular PCI Configuration Register writes PCI_CRP_AD_CBE register first. Assume that the AHB master wants to write a hexadecimal value of 0x85008086 to the Retry Timeout/TRDY Timeout (PCI_RTOTTO) Register. The PCI_CRP_AD_CBE register is written with a hexadecimal 0x00010040. Note that bits 23:20 are set to hexadecimal 0. For write accesses byte enables are active low.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Table 100. PCI Byte Enables Using CRP Access Method PCI_CRP_AD_CBE(23:20 ) PCI_CRP_WDATA (31:24) PCI_CRP_WDATA (24:16) 1010 X 1011 X PCI_CRP_WDATA (15:8) PCI_CRP_WDATA (7:0) X 1100 X 1101 X 1110 X X 1111 Table 101. Table 102. 6.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Target Interface is used to accept transaction request from other AHB Masters. The AHB Master Interface is used to initiate transaction requests to other AHB Targets. The two DMA channels as well as the PCI Target Interface use the AHB Master Interface. The AHB Target Interface can accept 8-bit (1 Byte) transactions, 16-bit transactions, and 32-bit transactions.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors The IXP42X product line and IXC1100 control plane processors will drive all the byte enables asserted during all memory cycle reads of the external PCI device, no matter what the PCI_NP_CBE register contains in the byte enable bits. To read non-prefetch memory sub-DWORDS (8-bit or 16-bit), use I/O reads. If it is necessary to use memory cycle reads of sub-DWORDS, a hardware resolution may be required.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Figure 36. Initiated PCI Type-0 Configuration Write Cycle PCI_CLK INT_REQ_N INT_GNT_N PCI_FRAME_N PCI_AD (31:0) 0x00000110 DATA 0xB 0x0 PCI_IDSEL PCI_C/BE_N PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N 6.6.4 Initiated Type-1 Read Transaction The following transaction is a PCI Configuration Read Cycle initiated from the IXP42X product line and IXC1100 control plane processors.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors 6.6.5 Initiated Type-1 Write Transaction The following transaction is a PCI Configuration Write working-site Cycle initiated from the IXP42X product line and IXC1100 control plane processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP42X product line and IXC1100 control plane processors.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Figure 39. Initiated PCI Memory Read Cycle PCI_CLK PCI_REQ_N PCI_GNT_N PCI_FRAME_N PCI_AD (31:0) 0x00000014 DATA PCI_IDSEL PCI_C/BE_N 0x6 0x0 PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N 6.6.7 Initiated Memory Write Transaction The following transaction is a PCI Memory Write Cycle initiated from the IXP42X product line and IXC1100 control plane processors.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 40. Initiated PCI Memory Write Cycle PCI_CLK INT_REQ_N INT_GNT_N PCI_FRAME_N PCI_AD (31:0) 0x00000014 DATA PCI_IDSEL PCI_C/BE_N 0x7 0x0 PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N 6.6.8 Initiated I/O Read Transaction The following transaction is a PCI I/O Read Cycle initiated from the IXP42X product line and IXC1100 control plane processors.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller implemented on the IXP42X product line and IXC1100 control plane processors. The transaction is initiated to address location hexadecimal 0x00000015. The value of binary 01 in PCI_AD (1:0) indicates that the transfer is a valid byte address of the first byte of 32-bit word address 0x00000014 (0x00000014 + 0x00000001 = 0x00000015).
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 43. Initiated PCI Burst Memory Read Cycle PCI_CLK INT_REQ_N INT_GNT_N PCI_FRAME_N PCI_AD (31:0) 0x00000014 DATA 0 0x6 0x0 DATA 1 PCI_IDSEL PCI_C/BE_N PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N 6.6.11 Initiated Burst Memory Write Transaction The following transaction is a two word bursting PCI Memory Write Cycle initiated from the IXP42X product line and IXC1100 control plane processors.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Figure 44. Initiated PCI Burst Memory Write Cycle PCI_CLK INT_REQ_N INT_GNT_N PCI_FRAME_N PCI_AD (31:0) 0x00000014 DATA 0 DATA 1 PCI_IDSEL PCI_C/BE_N 0x7 0x0 PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N 6.7 PCI Controller Functioning as Bus Target The IXP42X product line and IXC1100 control plane processors can be the target of PCI transactions.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors For each direction, when a DMA channel is executing one transfer using the active DMA register set, the other DMA register set can be set-up by the Intel XScale processor to specify the next transfer. Both DMA channels can run concurrently so that individual PCI-to-AHB transfers and AHB-to-PCI transfers that make up the DMA transfers are interleaved on the AHB and PCI bus.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Bit 28 of the Length Register is used to provide a byte swap on the DMA data as data is transferred from the AHB to the PCI bus or from the PCI Bus to AHB, depending upon the direction of the DMA transfer. When bit 28 is set to logic 1, a byte swap will occur on the DMA data. Figure 45 and Figure 46 demonstrates the DMA transfer byte lane swapping. Figure 45. Figure 46.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Additionally, while the AHB Master Interface is in use by a DMA channel, PCI requests that appear in the Target Receive FIFO are flagged to allow these received requests to gain access of the AHB bus. Access to the PCI Controller Control and Status Registers from the AHB is unrestricted while the DMA channels are operating.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Assume that this DMA channel is enabled prior to the end of the first eight-word burst of the first write DMA transfer ending. The DMA read transfer to the PCI bus becomes interleaved with the first write transfer. So the first eight words of the read starts towards completion. 7. Update the AHB to PCI DMA Length Register 1 (PCI_ATPDMA1_LENGTH) with PCI_ATPDMA1_LENGTH = 0x90000006.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors PCI_PTADMA0/1_LENGTH registers respectively. If the channel enable bit is set in the PCI_PTADMA0/1_LENGTH register, the DMA transfer commences. 2. The DMA Controller signals the AHB Slave Interface to retry all access attempts from the AHB bus and waits for any pending AHB accesses of the PCI Bus to complete. 3.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller The PCI Door Bell Register (PCI_PCIDOORBELL) register can only be written by the AHB. The external PCI device must write logic 1 to all set bits in the PCI Door Bell Register (PCI_PCIDOORBELL) in order to clear the bits set by the Intel XScale processor. An example of using the PCI Door Bell (PCI_PCIDOORBELL) is as follows: 1.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors • A Doorbell is “pushed” by an external PCI device The PCI Interrupt Status Register (PCI_ISR) indicates the source(s) of the PCI Controller Interrupt signal (PCC_INT). The PCI Controller Interrupt Enable (PCC_INTEN) Register provides an enable for each of the sources located in the PCI Interrupt Status Register (PCI_ISR).
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Bit 4 (AHB Big-endian Addressing Mode) defines to the PCI Controller how the data being sent to and from the AHB master and target interfaces are addressed. Figure 47 through Figure 52 shows the various configurations and the values returned from the PCI Controller when the AHB Master and Target Interfaces are configured in both big endian and little endian mode of operation.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 47. Byte Lane Routing During PCI Target Accesses of the AHB – AHB Configured as a Big-Endian Bus Read, pci_csr.PDS = 1 Write, pci_csr.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Figure 48. Byte Lane Routing During PCI Target Accesses of the AHB – AHB Configured as a Little-Endian Bus Read, pci_csr.PDS = 1 Write, pci_csr.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 49. Byte Lane Routing During AHB Memory Mapped Accesses of the PCI Bus – AHB Configured as a Big-Endian Bus Read, pci_csr.ADS = 1 Write, pci_csr.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Figure 50. Byte Lane Routing During AHB Memory Mapped Accesses of the PCI Bus – AHB configured as a Little-Endian Bus Read, pci_csr.ADS = 1 Write, pci_csr.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 51.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Figure 52. Byte Lane Routing During Configuration and Status Register Accesses PCI CSR Read 31 PCI Data 24 23 2 3 31 16 15 24 23 8 PCI CSR Write 7 8 7 31 PCI Data 0 1 16 15 0 0 24 23 3 31 2 24 23 8 7 0 1 16 15 0 8 7 0 CSR Register CSR Register AHB CSR Read 31 24 23 16 15 8 AHB CSR Write 7 0 CSR Register 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 CSR Register 31 AHB Data 6.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors 3. Wait 1ms to satisfy minimum reset assertion time of the PCI specification. 4. Configure the PCI clock GPIO for the proper PCI bus frequency (defined in the section GPIO). 5. Enable the PCI clock GPIO to drive the PCI clock 6. Wait 100 µs to satisfy the “minimum reset assertion time from clock stable” requirement of the PCI specification. 7. Set the PCI reset GPIO output to drive a 1. This releases the PCI bus.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller Table 103. 6.14.1.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors PCI_SRCR Register (Sheet 1 of 2) Reset Value PCI Access AHB Access Detected Parity Error. Set when this device detects a parity error on the bus even when parity handling is disabled. Writing a 1 to this bit clears it. 0 RW1C RW1C SSE Signaled System Error. Set when this device generates a System Error SERR#. Writing a 1 to this bit clears it. 0 RW1C RW1C 29 RMA Received Master Abort.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller PCI_SRCR Register (Sheet 2 of 2) Reset Value PCI Access AHB Access Bus Master Enable. When set, enables this device to act as a bus Master. 0 RW RW MAE Memory Access Enable. When set to a 1, enables memory accesses as a target. 0 RW RW IOAE I/O Access Enable. When set to a 1, enables I/O accesses as a target. 0 RW RW Bits Name 2 BME 1 0 6.14.1.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors PCI_BHLC Register Reset Value PCI Access AHB Access 0x00 RO RO Single Function/Multi-Function Device. Set to 0 to identify this device as a single-function PCI device. 0 RO RO Header Type[6:0] Configuration Header Type for this device. Set to 00 0x00 RO RO 15:1 0 Latency Timer[7:2] Latency Timer value in units of four PCI bus clocks.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.14.1.6 Base Address 1 Register (PCI_BAR1) Register Name: PCI_BAR1 Hex Offset Address: 0x14 Reset Hex Value: 0x00000008 Register PCI Base Address register for AHB memory space access. Format as specified in the PCI 2.2 Local Bus Description: Specification. 24 23 4 RWBase FixedBase Bits Name 31:2 4 RWBase 23:4 FixedBase 3 PREF 2:1 Type Relocatable anywhere in 32-bit address space.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors 6.14.1.8 Base Address 3 Register (PCI_BAR3) Register Name: PCI_BAR3 Hex Offset Address: 0x1C Reset Hex Value: 0x00000008 Register PCI Base Address register for AHB memory space access. Format as specified in the PCI 2.2 Local Bus Description: Specification 24 23 4 RWBase FixedBase Bits Name 31:2 4 RWBase 23:4 FixedBase 3 PREF Pre-fetchable memory indicator.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.14.1.10 Base Address 5 Register (PCI_BAR5) Register Name: PCI_BAR5 Hex Offset Address: 0x24 Reset Hex Value: 0x00000001 Register PCI Base Address register for AHB I/O space access. Format as specified in the PCI 2.2 Local Bus Description: Specification. 8 7 RWBase Name 31:8 RWBase 7:2 Reset Value PCI Access AHB Access 0x000000 RW RW 0x00 RO RO Description Read/Write bits of Base Address register.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors 6.14.1.12 Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register (PCI_LATINT) Register Name: PCI_LATENT Hex Offset Address: 0x3C Reset Hex Value: 0x00000100 Register Miscellaneous register provides Max Latency, Min Grant, Interrupt Pin and Interrupt Line parameters as Description: specified in the PCI 2.2 Local Bus Specification Access: See below.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.14.2 PCI Controller Configuration and Status Registers These registers are accessible from the AHB and are memory mapped in the AHB address space. Table 104 shows the address map for the Control and Status Register. The PCI offset is relative to the base address in PCI_BAR4 for accesses from the PCI bus. Table 104.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors 6.14.2.1 PCI Controller Non-pre-fetch Address Register (PCI_NP_AD) Register Name: PCI_NP_AD Hex Offset Address: 0xC0000000 Reset Hex Value: 0x00000000 Register PCI non-pre-fetch access address register. Provides address for CSR-initiated non-pre-fetch PCI Description: accesses. Access: See below.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.14.2.3 PCI Controller Non-Pre-fetch Write Data Register (PCI_NP_WDATA) Register Name: PCI_NP_WDATA Hex Offset Address: 0xC0000008 Reset Hex Value: 0x00000000 Register PCI non-pre-fetch access write data register. Provides write data for CSR-initiated non-pre-fetch PCI Description: write access. Access: See below. 31 0 NP_WDATA PCI_NP_WDATA Register Bits Name 31:0 np_wdata 6.14.2.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors PCI_CRP_AD_CBE Register Bits Name Description Reset Value PCI Access AHB Access 0x00 RO RO 31:2 4 (Reserved) – Read as 0 23:2 0 CRP_BE Active-low byte enables for a PCI configuration port write access.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.14.2.7 PCI Controller Configuration Port Read Data Register (PCI_CRP_RDATA) Register Name: PCI_CRP_RDATA Hex Offset Address: 0xC0000018 Reset Hex Value: 0x00000000 Register PCI configuration port read data register. Provides read data for CSR-initiated read accesses of the PCI Description: Controller PCI configuration registers in the PCI Core. Access: See below.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors PCI_CSR (Sheet 2 of 2) Register Reset Value PCI Access AHB Access AHB big-endian addressing. When 0, little-endian addressing is employed on both AHB master and slave interfaces. When 1, big-endian addressing is implemented. 0 RO RW PDS PCI byte swap. Controls byte lane data routing between PCI and AHB buses during PCI Target accesses of the AHB bus. When 1, byte lane swapping is performed. When 0, no swapping is done.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller PCI_ISR (Sheet 2 of 2) Register Bits Name Description PPE PCI Parity Error. Set to a 1 when a parity error occurs on the PCI bus: Parity error detected during Master Interface read cycle. pad_perr_n (PERR#) asserted by an external target during a Master write cycle. 1 PFE PCI Fatal Error.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors 6.14.2.11 DMA Control Register (PCI_DMACTRL) Register Name: Hex Offset Address: PCI_DMACTRL 0xC0000028 Reset Hex Value: 0x00000000 Register Control and status for the DMA Controller channels. Description: Name 31:1 6 4 3 1 (Rsvd) Description (Reserved) – Read as 0 Reset Value PCI Access AHB Access 0x0000 RO RO PADE1 PCI to AHB DMA error for buffer 1.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller PCI_DMACTRL (Sheet 2 of 2) Register Bits 4 Name Description Reset Value PCI Access AHB Access APDC0 AHB to PCI DMA complete for buffer 0. Set to a 1 when the DMA transfer specified by the pci_atpdma0_xxx registers is complete or terminated due to an error. If the APDCEN bit is a 1, the pcc_atpdma_int output is asserted high. 0 RO RW1C 000 RO RO APDCEN AHB to PCI DMA Complete interrupt enable.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors PCI_AHBIOBASE Register Bits Name 31:2 4 23:0 Reset Value PCI Access AHB Access 0x00 RO RO 0x000000 RO RW Description (Reserved) – Read as 0 Iobase 6.14.2.14 Upper 24 AHB address bits for PCI accesses that target pci_bar5.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller PCI_AHBDOORBELL Register Bits 31:0 Name ADB 6.14.2.16 Reset Value PCI Access AHB Access 0x00000000 RW1S RW1C (RW if pci_csr.DBT =1) Description PCI generated doorbell interrupt to an AHB agent. Normally read/write-1-to-set from PCI and read/ write-1-to-clear from AHB. Read/write from the AHB side if Doorbell Test mode is enabled by setting pci_csr.DBT to a 1.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors 6.14.2.18 AHB to PCI DMA PCI Address Register 0 (PCI_ATPDMA0_PCIADDR) Register Name: PCI_ATPDMA0_PCIADDR Hex Offset Address: 0xC0000044 Reset Hex Value: 0x00000000 Register Destination address on the PCI bus for AHB to PCI DMA transfers. Paired with pci_atpdma1_pciaddr to Description: allow buffering of DMA transfer requests. Access: See below.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller 6.14.2.20 AHB to PCI DMA AHB Address Register 1 (PCI_ATPDMA1_AHBADDR) Register Name: PCI_ATPDMA1_AHBADDR Hex Offset Address: 0xC000004C Reset Hex Value: 0x00000000 Register Source address on the AHB bus for AHB to PCI DMA transfers. Paired with pci_atpdma0_ahbaddr to allow Description: buffering of DMA transfer requests. Access: See below.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors Register PCI_ATPDMA1_LENGTH Bits Name Description Reset Value PCI Access AHB Access 31 EN Channel enable. When set to a 1, executes a DMA transfer if wordcount is nonzero. When 0, the channel is disabled. Hardware clears this bit when the DMA transfer is complete. 0 RO RW 00 RO RO 0 RO RW 0x000 RO RO 0x0000 RO RW 30:2 9 28 (Reserved). Read as 0. Data Swap indicator.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller PCI_PTADMA0_PCIADDR Register Bits Name 31:2 address 1:0 Reset Value Description PCI word address PCI Access AHB Access 0x00000000 RO RW 00 RO RO Lower PCI address bits hard-wired to zero. 6.14.2.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors PCI_PTADMA1_AHBADDR Register Bits Name 31:2 Address 1:0 Reset Value Description AHB word address PCI Access AHB Access 0x00000000 RO RW 00 RO RO Lower AHB address bits hard-wired to zero. 6.14.2.
Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller PCI_PTADMA1_LENGTH (Sheet 2 of 2) Register Bits Name Description Reset Value PCI Access AHB Access 28 DS Data Swap indicator. When set to a 1, data from the PCI bus is byte swapped before being sent to the AHB bus. When 0, no swapping is done. 0 RO RW 0x000 RO RO 0x0000 RO RW 27:1 6 15:0 (Reserved). Read as 0. wordcount Number of words to transfer.
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 275
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller 7.0 SDRAM Controller The SDRAM Controller performs data movement between the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor and an attached SDRAM. The SDRAM Controller is a target only function on both AHB interfaces and supports a maximum of 256 Mbyte of addressable space. Table 105 shows the supported memory configuration. Support is included for two memory banks of SDRAM devices.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 53.
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller Figure 54.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors After decoding is complete, the SDRAM Controller completes the read or write transaction to the SDRAM. Byte and half-word transfers are implemented by controlling the DQM pins of the SDRAM. The SDRAM Controller performs byte lane steering for write operations to the SDRAM. Read operations performed by the SDRAM Controller to the SDRAM do not support byte-lane steering.
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller to-data delay will be initialized to two clocks. The initial value in bit 3 will be logic 0. If a CAS to data delay of three clocks is required, bit 3 of the SDRAM Configuration (SDR_CONFIG) Register must be set to logic 1. Bits 2:0 of the SDRAM Configuration (SDR_CONFIG) Register are used to configure the SDRAM Controller to operate with a given physical memory configuration.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors An example of configuring the SDRAM Configuration (SDR_CONFIG) Register is shown below: 1. Assume that the application being configured is a 256-Mbyte configuration using four chips (32 Mbyte x 16) and a CAS to data delay of three clocks. See Figure 54 for an SDRAM Connection Example of a similar configuration. 2. A hexadecimal value of 0x0000000Dis written to 0xCC000000.
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller Table 109. SDRAM Command Description (Sheet 2 of 2) Command Name SDR_IR[2: 0] Description Auto-Refresh 100 Used to produce a refresh command to the SDRAM to avoid loss of data. The times between successive refresh commands is a function of the SDRAM that is chosen. Burst Terminate 101 A command issued to the SDRAM to terminate a current fixed length burst.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors 7.2.1 Initializing the SDRAM Once the Intel XScale processor configures the SDRAM Configuration (SDR_CONFIG) Register and the SDRAM Refresh (SDR_REFRESH) Register, the following sequence of commands — using the SDRAM Instruction (SDR_IR) Register — must be performed to initialize the SDRAM. (This routine can change depending on the SDRAM part that is connected to the SDRAM interface.
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller A page hit is valid if the memory location falls within the location as specified by the open page register: Table 111.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors Table 112. Data Transfer Sizes of AHB Size Description 8 bits Byte 16 bits Half word 32 bits Word 7.3 SDRAM Memory Accesses 7.3.1 Read Transfer When the AHBs generate a read transaction with an address located in the SDRAM space, a read from SDRAM is initiated. The SDRAM detects the read initiation request from the AHB.
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller 7.3.1.2 Read Burst Transfer (Interleaved AHB Reads) The timing diagram in Figure 56 shows read requests from an NPE on the North AHB and the Intel XScale processor on the South. Both masters access different memory banks. Figure 56.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 57. SDRAM Write Example SDM_CLK COMMAND ACTIVE NOP NOP WRITE WRITE WRITE SDM_ADDR RAS XX XX CAS CAS CAS SDM_DATA XX XX XX D0 D1 D2 SDM_DQM HI HI HI LOW LOW SDM_CKE HI HI HI HI HI 7.
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller Register Name: SDR_CONFIG Hex Offset Address: 0xCC000000 Reset Hex Value: 0x00000010 Register Configuration of the memory/memory controller. Description: 3 Bits Name 31:21 (Reserved) 5 Enable 64Mbit 4 RAS Latency 1 = Three-cycle latency. This is hard-coded. 3 CAS Latency 1 = Three-cycle latency. Default is two-cycle latency. 2:0 Memory Config Note: 2 0 Mem config SDR_CONFIG Register 7.4.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors Register Name: SDR_IR Hex Offset Address: Register Description: 0xCC000008 Reset Hex Value: 0x00000000 Instruction register, holds commands that determine operation mode of the SDRAM controller and mode register for SDRAMs. Access: Read/Write 31 16 15 3 0 Instruction (command) (Reserved) SDR_IR Register Bits 2 Name Description 31:3 (Reserved) Commands to be sent out to the SDRAM.
Intel® IXP42X product line and IXC1100 control plane processors—SDRAM Controller Table 115.
SDRAM Controller—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 291
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.0 Expansion Bus Controller The Expansion Bus Controller provides an interface from internal South AHB to external flash, Host-Port Interfaces (HPI), SRAM and other devices such as ATM control interfaces, and DSPs used for voice applications. The Expansion Bus includes a 24-bit address bus and a 16-bit-wide data path and maps transfers between the South AHB and external devices.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors One of these general-purpose configuration registers is used to capture the value on the address pins immediately after reset. In the Expansion Bus Interface, 24 address lines are used to capture this configuration information at the release of reset. When power up is complete and reset is asserted, the 24 address lines are configured as inputs.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller When bit 31 of the Configuration Register 0 (EXP_CNFG0) is set to logic 1, the Expansion Bus accesses occupy the lowest 256-Mbytes of address space. When bit 31 of the Configuration Register 0 (EXP_CNFG0) is set to logic 0, the SDRAM occupies the lowest 256 Mbytes of address. On reset, bit 31 of the Configuration Register 0 (EXP_CNFG0) is set to logic 1.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 58. Chip Select Address Allocation CNFG[3:0] = 0b1111 SIZE = 2(9 + CNFG) SIZE = 224 SIZE = 16 MBytes base + 0xFFFFFFF .. .
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller Table 118. Expansion Bus Address and Data Byte Steering South AHB Bus Cycle Device Connected to Expansion Bus (8-bit or 16bit) 32-bit write 8-bit Not allowed. 32-bit write 16-bit Not allowed.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors 8.4 Expansion Bus Connections Figure 60 shows a typical connection for various devices connected on the expansion bus. Note that GPIO(0) is used as an example, and that your design can use any GPIO port. Also note that EX_CS2_N and EX_CS7_N are shown as examples, and that your design can use any EX_CS_N port. Figure 60.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.5 Expansion Bus Interface Configuration There are eight registers — called the Timing and Control (EXP_TIMING_CS) Registers — that define the operating mode for each chip select. When designing with the Expansion Bus Interface, placing the devices on the correct chip selects is required.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors Each chip select can be independently enabled or disabled by setting a value in bit 31 of each Timing and Control (EXP_TIMING_CS) Register. Setting bit 31 — of the Timing and Control (EXP_TIMING_CS) Register — to logic 0 disables the corresponding chip select. Setting bit 31 — of the Timing and Control (EXP_TIMING_CS) Register — to logic 1 enables the corresponding chip select.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller • T2 – Setup/Chip Select Timing • T3 – Strobe Timing • T4 – Hold Timing • T5 – Recovery Phase The expansion-bus address is used to present the 24 bits of the address [23:0] used for the expansion bus access accompanied by an address latch enable output signal, EX_ALE. The address phase normally last one clock cycle, in non-multiplexed mode, and two clock cycles, in multiplexed mode.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors the T3 – Strobe Timing parameter to be two clock cycles in length ensures that any data sent to the DSP is captured regardless of when the EX_RDY signal is asserted by the DSP. The Hold Phase of an expansion-bus access is provided to allow a hold time for data to remain valid after the data strobe has transitioned to an invalid state.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller The T4 (Hold Timing) period is the time interval in which Chip Select will be held after READ is deasserted. T4 prevents bus contention while Chip Select is asserted, in case the peripheral driving the bus continues to send data out after READ has been deasserted. During T4 no other transaction can start, since the current transaction will not finish until Chip Select is deasserted by the processor.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors Figure 62. I/O Wait Extended Phase Timing T1=3 h T2=3 h T3=F h T4=3 h T5=F h 4 Cycles 4 Cycles 16 Cycles 4 Cycles 16 Cycles .... EX_ CLK .... 2 Cycles EX_CS_ N[0] Valid Address EX_ADDR[23 :0 ] EX_ IOWAIT_N EX_RD_N Valid Data EX_DATA[15:0] B5243- 01 8.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller The byte identification signal, EX_HBIL, is used to determine the byte transfer order. (EX_HBIL is driven low for the first byte of the transfer and driven high for the second byte.) The byte order bit (BOB) in the HPIC register (contained in the DSP) — within the HPI device — is used to determine the placement for the two bytes of the transfer.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors 8.8 Expansion Bus Interface Access Timing Diagrams 8.8.1 Intel® Multiplexed-Mode Write Access Figure 63.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.8.2 Intel® Multiplexed-Mode Read Access Figure 64.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors 8.8.3 Intel® Simplex-Mode Write Access Figure 65.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.8.4 Intel® Simplex-Mode Read Access Figure 66.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors 8.8.5 Motorola* Multiplexed-Mode Write Access Figure 67.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.8.6 Motorola* Multiplexed-Mode Read Access Figure 68.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors 8.8.7 Motorola* Simplex-Mode Write Access Figure 69.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.8.8 Motorola* Simplex-Mode Read Access Figure 70.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors TI* HPI-8 Write Access Figure 71. Expansion-Bus Write (TI* HPI-8 Mode) 2-4 Cycles Valid Data EX_DATA[15:0] (hdin) EX_RDY_N (hrdy) EX_WR_N (hds1_n) EX_ADDR[0] (hbil) EX_RD_N (hr_w_n) Valid Address EX_ADDR[23:0] (hcntl) EX_CLK EX_CS_N[0] (hcs_n) T5 T4 T3 2-16 Cycles T2 3-4 Cycles T1 3-4 Cycles HPI-8 Mode Write Accesses September 2006 Order Number: 252480-006US 1-16 Cycles B4361-01 8.8.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller TI* HPI-8 Read Access Figure 72. Expansion-Bus Read (TI* HPI-8 Mode) 1-16 Cycles Valid Data 2-4 Cycles EX_DATA[15:0] (hdout) EX_RDY_N (hrdy) EX_WR_N (hds1_n) EX_ADDR[0] (hbil) EX_RD_N (hr_w_n) Valid Address EX_ADDR[23:0] (hcntl) EX_CS_N[0] (hcs_n) EX_CLK 3-4 Cycles 3-4 Cycles 2-16 Cycles T2 HPI-8 Mode Read Accesses T1 T3 T4 T5 B4357-01 8.8.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors TI* HPI-16, Multiplexed-Mode Write Access Figure 73.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller TI* HPI-16, Multiplexed-Mode Read Access Figure 74. Expansion-Bus Read (TI* HPI-16 Multiplexed Mode) 1-16 Cycles 2-4 Cycles Valid Data EX_DATA[15:0] (hdout) EX_RDY_N (hrdy) EX_WR_N (hds1_n) EX_RD_N (hr_w_n) Valid Address EX_ADDR[23.0] (hcntl) EX_CS_N[0] (hcs_n) EX_CLK 3-4 Cycles 3-4 Cycles 2-16 Cycles T2 HPI-16 Multiplex Read Mode T1 T3 T4 T5 B4356-01 8.8.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors TI* HPI-16 Simplex-Mode Write Access Figure 75. Expansion-Bus Write (TI* HPI-16 Simplex Mode) September 2006 Order Number: 252480-006US Valid Data Valid Address EX_DATA[15:0] (hdin) EX_RDY_N (hrdy) EX_WR_N (hds1_n) EX_RD_N (hr_w_n) EX_ADDR[23:0] (ha) EX_CS_N[0] (hcs_n) EX_CLK HPI-16 Simplex Write Mode T1 3-4 Cycles T2 3-4 Cycles T3 2-16 Cycles T4 2-4 Cycles T5 1-16 Cycles B4360-01 8.8.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller TI* HPI-16 Simplex-Mode Read Access Figure 76. Expansion-Bus Read (TI* HPI-16 Simplex Mode) 1-16 Cycles 2-4 Cycles Valid Data EX_DATA[15:0] (hdout) EX_RDY_N (hrdy) EX_WR_N (hds1_n) EX_RD_N (hr_w_n) Valid Address EX_ADDR[23:0] (hcntl) EX_CS_N[0] (hcs_n) EX_CLK 3-4 Cycles 3-4 Cycles 2-16 Cycles T2 HPI-16 Simplex Read Mode T1 T3 T4 T5 B4359-01 8.8.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors 8.9 Register Descriptions Table 122.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.9.3 Timing and Control Registers for Chip Select 2 Register Name: EXP_TIMING_CS2 Hex Offset Address: 0XC4000008 Reset Hex Value: 0x00000000 Register Timing and Control Registers Description: Access: Read/Write. 2 1 0 BYTE_EN (Rsvd) 3 (Rsvd) CNFG[3:0] 4 WR_EN T5 5 SPLT_EN T4 6 MUX_EN T3 10 9 HRDY_POL 8.9.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors 8.9.6 Timing and Control Registers for Chip Select 5 Register Name: EXP_TIMING_CS5 Hex Offset Address: 0XC4000014 Reset Hex Value: 0x00000000 Register Timing and Control Registers Description: Access: Read/Write. 3 2 1 0 BYTE_EN (Rsvd) 4 (Rsvd) CNFG[3:0] 5 WR_EN T5 6 SPLT_EN T4 9 MUX_EN T3 10 HRDY_POL 8.9.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller Table 123.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors These configuration bits are made available to the system as outputs from the Expansion Bus Controller block. With the exception of bits 23, 22 and 21, which are read only, all other bits may be written and read from the South AHB. Register Name: EXP_CNFG0 Hex Offset Address: 0XC4000020 Reset Hex Value: 0x8XXXXXXX Register Configuration Register #0 Description: Table 124.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller Once the boot sequence completes this bit is written to a ‘0,’ switching the default system memory map to place the SDRAM controller at address 0x00000000 to 0x0FFFFFFF. The Expansion Bus Controller now resides at address 0x50000000 to 0x5FFFFFFF. Weak pull-up resistors are placed on each expansion-bus address pin. Table 125.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors Register Name: EXP_CNFG1 Hex Offset Address: 0XC4000024 Reset Hex Value: 0x00000000 Register Configuration Register #1 Description: (Reserved) Table 126. 8 7 2 (Reserved) 1 0 SW_ INT0 9 BYTE_SWAP_EN 31 SW_ INT1 Access: Read/Write.
Intel® IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller 8.10 Expansion Bus Controller Performance Table 127 shows simulated expansion bus throughput. Table 127. Note: Simulated Expansion Bus Performance Intel XScale® Processor Command Expansion Bus Width (bits) Expansion Bus Frequency (MHz) Maximum Sustainable Throughput (MBytes/s) ldrb 8 33 2.01 ldrb 8 66 3.21 ldrb 16 33 2.01 ldrb 16 66 3.21 strb 8 33 1.98 strb 8 66 3.29 ldrh 16 33 4.
Expansion Bus Controller—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 327
Intel® IXP42X product line and IXC1100 control plane processors—AHB/APB Bridge 9.0 AHB/APB Bridge The APB Bridge is used to connect the high-speed AHB to the lower-speed peripherals connected to the APB. The AHB-APB Bridge provides a 32-bit wide data path between the South AHB and the APB. Address bits 31:16 of the AHB bus are not sent to the bridge, but are instead decoded by the AHB arbiter and a select signal is used to indicate that the address references a location downstream of the bridge.
AHB/APB Bridge—Intel® IXP42X product line and IXC1100 control plane processors Figure 77. APB Interface UTOPIA 2 HSS 0 HSS 1 WAN/VOICE NPE MII 0 MDC/MDIO MII 1 ETHERNET NPE A ETHERNET NPE B HIGH SPEED UART CONSOLE UART IBPMU APB AHB/APB BRIDGE SOUTH AHB INTERRUPT CONTROLLER GPIO OS TIMERS USB V1.
Intel® IXP42X product line and IXC1100 control plane processors—AHB/APB Bridge Table 128.
AHB/APB Bridge—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 331
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) 10.0 Universal Asynchronous Receiver Transceiver (UART) The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor supports two Universal Asynchronous Receiver-Transmitter (UART) interfaces. One UART is intended primarily to support debug and control functions.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors 10.1 High Speed UART The UARTs performs serial-to-parallel conversion — on data characters received from a peripheral device or a modem — and parallel-to-serial conversion — on data characters received from the Intel XScale® Processor.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) Figure 79.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors 10.2 Configuring the UART The following sections provide a detailed description of configuring the UART interfaces for operation. 10.2.1 Setting the Baud Rate Each UART contains a programmable baud-rate generator that is capable of taking the 14.7456 MHz, input clock and dividing it by any divisor ranging from 1 to (216 –1).
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) 10.2.2 Setting Data Bits/Stop Bits/Parity The Line Control Register (LCR) is an 8-bit register that enables the system programmer to specify the format of the asynchronous data communications exchange. The serial data format consists of a start bit (logic 0), five to eight data bits, an optional parity bit, and one or two stop bits (logic 1).
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors The Even-Parity Select (EPS) Bit is used to determine the parity type to transmit or check on receive data when the Parity-Enable (PEN) Bit in the Line-Control Register enables parity. When the Parity-Enable bit is logic 1 and the Even-Parity Select bit is logic 0, the parity generator will transmit odd parity and the parity checker will validate against odd parity on the received data.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) Table 132. UART Word-Length Select Configuration WLS Number of Data Bits Contained in Each Transmitted Or Received Character Bit 1 Bit 0 0 0 5-bit character (default) 0 1 6-bit character 1 0 7-bit character 1 1 8-bit character The Line-Control Register is initialized to hexadecimal 0x00 after reset. The Line-Status Register is initialized to hexadecimal 0x60 after reset. 10.2.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors Leaving loop-back mode and returning to normal mode may result in unpredictable activation of the Modem Status Register (MSR). It is recommended that the Modem Status Register be read once to clear the Modem Status Bits in the Modem Status Register. In the loop-back diagnostic mode, data that is transmitted will be immediately received.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) UART Interrupt Enable Register bits 4 through 0 represent five different interrupt types that can be individually enabled/disabled: • Receiver Time Out Interrupt Enable (RTOIE) • Modem Interrupt Enable (MIE) • Receiver Line Status Interrupt Enable (RLSE) • Transmit Data Request Interrupt Enable (TIE) • Receiver Data Available Interrupt Enable (RAVIE) The Receiver Line Status Interrupt Enable a
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors For example, the maximum time between a received character and a Receive Character Time-Out Interrupt is 160 ms at 1,200 baud with a 12-bit receive character (i.e., 1 start, 8 data, 1 parity, and 2 stop bits). (1/ ((1200characters/second)/12characters))) * 4 characters = = 0.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) Receive Interface. Lines Status Register bits 1 through 4 specify which error(s) has occurred — for the character at the bottom of the FIFO or in the Receive Buffer Register. In FIFO mode, Line Status Register bit 1 through 3 is stored with each received character in the Receive FIFO. The Line Status Register shows the status bits of the character at the bottom of the Receive FIFO.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors The error flags position will remain constant, independent of the character size. The mode of operation and FIFO control parameters will be programmed using the FIFO Control Register (FCR). The FIFO Control Register is an 8-bit register that configures the UARTs’ mode of operation.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) If characters less than 8 bits are received, the characters will need to be right-justified. For example, if a 5-bit data character is received having a binary value of 00101. The data read from the Receive Buffer Register will be a hexadecimal 0x05. (Notice that the three most-significant bits of the byte are filled with zeros.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors RBR Register Bits Name 31:8 (Reserved) 7:0 10.4.2 Description In non-FIFO mode, this register holds the character received by the UART’s Receive Shift Register. If fewer than 8 bits are received, the bits are rightjustified and the leading bits are zeroed. In FIFO mode, this register latches the value of the data byte at the bottom of the Receive FIFO.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) DLL Register Bits Name 31:8 7:0 10.4.4 Description (Reserved) Lower byte of compare-value used by the baud rate generator. The DLAB bit in the Line Control Register must be set to logic 1 to access this register.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors IER Register Bits Name 31:8 10.4.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) Priority Level Interrupt origin 2 Receiver Time out occurred: It happens in FIFO mode only, when there is data in the receive FIFO but no activity for a time period. 3 Transmitter requests data: In FIFO mode, the transmit FIFO is half or more than half empty. In non-FIFO mode, THR is read already. 4 (lowest) Modem Status: One or more of the modem input signals has changed state.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors Table 135. UART IDD Bit Mapping Interrupt ID Bits Interrupt SET/RESET Function 3 2 1 0 Priority 0 0 0 1 - 0 1 1 0 Highest Type Source RESET Control None No Interrupt is pending - Receiver Line Status Overrun Error, Parity Error, Framing Error, Break Interrupt Reading the Line Status Register. Non-FIFO mode: Reading the Receiver Buffer Register.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) FCR Register Bits Name 31:8 7:6 (Reserved) Interrupt Trigger Level: When the number of entries in the receive FIFO equals the interrupt trigger level programmed into this field and the Received Data Available Interrupt is enabled (via IER), an interrupt is generated and appropriate bits are set in the IIR.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors LCR Register Bits Name Description DLAB Divisor Latch Access Bit: This bit must be set to logic 1 to access the Divisor Latches of the Baud Rate Generator during a READ or WRITE operation. It must be set low (logic 0) to access the Receiver Buffer, the Transmit Holding Register, or the Interrupt Enable Register.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) 10.4.9 Modem Control Register Register Name: MCR Hex Offset Address: 0xC800 0010 Reset Hex Value: 0x00000000 Register Modem Control Register Description: Name 31:5 4 2 1 0 DTR MCR Register Bits 3 RTS (Reserved) 4 OUT1 5 OUT2 31 LOOP Access: Read/Write.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors 10.4.10 Line Status Register Register Name: LSR Hex Offset Address: 0xC800 0014 Reset Hex Value: 0x00000060 Register Line Status Register Description: Name 31:8 7 6 5 4 3 September 2006 Order Number: 252480-006US 3 BI FE 2 1 0 DR 4 PE 5 LSR (Sheet 1 of 2) Register Bits 6 OE (Reserved) 7 TDRQ 8 TEMT 31 FIFOE Access: Read Only.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) LSR (Sheet 2 of 2) Register Bits 2 1 0 10.4.11 Name Description PE Parity Error: PE indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to logic 1 upon detection of a parity error and is reset to logic 0 when the processor reads the Line Status register.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors MSR Register Bits Name 31:8 (Reserved) DCD Data Carrier Detect: This bit is the complement of the Data Carrier Detect (DCD#) input. This bit is equivalent to bit OUT2 of the Modem Control register if LOOP in the MCR is set to 1. 0 = DCD# pin is 1 1 = DCD# pin is 0 RI Ring Indicator: This bit is the complement of the ring Indicator (RI#) input.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) SPR Register Bits Name 31:8 7 10.4.13 Description (Reserved) SCR No effect on UART functionality Infrared Selection Register The Slow Infrared (SIR) Interface can be used in conjunction with a standard UART to support two-way, wireless communications using infrared radiation.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors ISR (Sheet 2 of 2) Register Bits 2 1 0 10.5 Name Description XMODE Transmit Pulse Width Select: When XMODE is set to 0, clocking of the IRDA transmit and receive logic is done by the UART clock, which must be operating in the 16X mode. When XMODE is set to a 1, the operation of the receive decoder does not change. The transmit encoder, however, generates pulses 1.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) Table 136. 10.5.1.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors THR Register Bits Name Description THR In Non-FIFO mode, This register holds the next data byte to be transmitted. When the Transmit Shift Register becomes empty, the contents of the Transmit Holding Register are loaded into the shift register and the transmit data request (TDRQ) bit in the Line Status Register is set to 1.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) 10.5.1.5 Interrupt Enable Register The DLAB bit in the Line Control Register must be set to logic 0 to access this register. Register Name: IER Hex Offset Address: 0xC800 1004 Reset Hex Value: 0x00000000 Register Interrupt Enable Register Description: Name 31:8 10.5.1.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors Table 137. Priority Levels of Interrupt Identification Register Priority Level Interrupt origin 1 (Highest) Receiver Line Status: One or more error bits were set. 2 Received Data is Available: In FIFO mode, trigger level was reached. In non-FIFO mode, RBR has data.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) Table 138. UART Interrupt Identification Bit Level Definition Interrupt ID Bits Interrupt SET/RESET Function 3 2 1 0 Priority 0 0 0 1 - None No Interrupt is pending - 0 Highest Receiver Line Status Overrun Error, Parity Error, Framing Error, Break Interrupt. Reading the Line Status Register. Received Data Available. Non-FIFO mode: Receive Buffer is full.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors FCR Register Bits Name 31:8 (Reserved) 7:6 ITL 5:3 — 2 1 0 10.5.1.8 Description Interrupt Trigger Level: When the number of entries in the receive FIFO equals the interrupt trigger level programmed into this field and the Received Data Available Interrupt is enabled (via IER), an interrupt is generated and appropriate bits are set in the IIR.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) LCR Register Bits Name Description DLAB Divisor Latch Access Bit: This bit must be set to logic 1 to access the Divisor Latches of the Baud Rate Generator during a READ or WRITE operation. It must be set low (logic 0) to access the Receiver Buffer, the Transmit Holding Register, or the Interrupt Enable Register.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors 10.5.1.9 Modem Control Register Register Name: MCR Hex Offset Address: 0xC800 1010 Reset Hex Value: 0x00000000 Register Modem Control Register Description: Name 31:5 4 2 1 0 DTR MCR Register Bits 3 RTS (Reserved) 4 OUT1 5 OUT2 31 LOOP Access: See below.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) 10.5.1.10 Line Status Register Register Name: LSR Hex Offset Address: 0xC800 1014 Reset Hex Value: 0x00000060 Register Line Status Register Description: Name 31:8 7 6 5 4 3 FE 2 1 0 DR 3 PE 4 OE 5 LSR (Sheet 1 of 2) Register Bits 6 BI (Reserved) 7 TDRQ 8 TEMT 31 FIFOE Access: Read Only.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors LSR (Sheet 2 of 2) Register Bits Name 2 1 0 10.5.1.11 Description PE Parity Error: PE indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to logic 1 upon detection of a parity error and is reset to logic 0 when the processor reads the Line Status register.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) MSR Register Bits Name Description DCD Data Carrier Detect: This bit is the complement of the Data Carrier Detect (DCD#) input. This bit is equivalent to bit OUT2 of the Modem Control Register if LOOP in the MCR is set to 1. 0 = DCD# pin is 1 1 = DCD# pin is 0 RI Ring Indicator: This bit is the complement of the ring Indicator (RI#) input.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors SPR Register Bits Name 31:8 (Reserved) 7 10.5.1.13 Description SCR No effect on UART functionality Infrared Selection Register The Slow Infrared (SIR) Interface can be used — in conjunction with a standard UART — to support two-way, wireless communications using infrared radiation.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous Receiver Transceiver (UART) ISR (Sheet 2 of 2) Register Bits 2 1 0 Name Description XMODE Transmit Pulse Width Select: When XMODE is set to 0, clocking of the IRDA transmit and receive logic is done by the UART clock, which must be operating in the 16X mode. When XMODE is set to a 1, the operation of the receive decoder does not change, but the transmit encoder generates pulses that are 1.
Universal Asynchronous Receiver Transceiver (UART)—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 371
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance Monitoring Unit (IBPMU) 11.0 Internal Bus Performance Monitoring Unit (IBPMU) The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor’ Internal Bus Performance Monitoring Unit (IBPMU) may be used to gather statistics about transactions occurring on North AHB, South AHB, and the SDRAM Controller.
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100 control plane processors The most-significant bit of each three-bit programmable event counter configuration register will select if the programmable event counter is to read an occurrence event or a duration event.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance Monitoring Unit (IBPMU) The programmable event counters (PEC) and the previous master and slave register (PMSR) can be used for easy collection of the gathered statistical information. The programmable event counters can be read periodically or when an interrupt occurs to the Intel® IXP42X product line and IXC1100 control plane processors’ Interrupt Controller.
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100 control plane processors For a duration event, the programmable event counters will count the number of clocks during which a particular condition or set of conditions is valid. Duration measurements examples include: • Bus Acquisition Latency — The elapsed time between when an AHB bus initiator issues a request for the AHB bus, to when the AHB bus initiator is granted the AHB bus.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance Monitoring Unit (IBPMU) Table 142. North and South Modes Event Descriptions (Sheet 1 of 2) Event Bus Components Type Description Bus_idle North AHB South AHB Duration Increments the counter every AHB Bus idle cycle. An idle cycle occurs when there is no activity on the bus due to data being transferred and the bus is not in an overhead cycle.
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100 control plane processors Table 142. Event North and South Modes Event Descriptions (Sheet 2 of 2) Bus Components Type Description Occur Monitors the number of times the master is granted the bus. It increments the counter when the master is the bus initiator. The counter is incremented once for every new transaction. For multi-cycle transactions, the counter increments once on the first cycle.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance Monitoring Unit (IBPMU) 11.3 Register Descriptions Table 143. Internal Bus PMU Register Overview Address 11.3.
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100 control plane processors ESR Register Bits Name Description 31:23 (Reserved). Always zero 22:20 PEC1 ctrl Selects Enable conditions for counter PEC1. 0xx = Occur / Hit 1xx = Duration / Miss Note: The lower two bits select one of four event or duration inputs depending on the mode and which type of event is selected. PEC2 ctrl Selects Enable conditions for counter PEC2.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance Monitoring Unit (IBPMU) Table 144.
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100 control plane processors 11.3.2 PMU Status Register (PSR) The PSR allows access to the over flow flags from the PEC counters. These flags remain set until cleared by writing a 1 to the bit. Register Name: PSR Hex Offset Address: 0xC800 2004 Reset Hex Value: 0x00000000 Register PMU Status Register Description: 11.3.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance Monitoring Unit (IBPMU) 11.3.4 Programmable Event Counters (PEC2) Register Name: PEC2 Hex Offset Address: 0xC800 200C Reset Hex Value: 0x00000000 Register Programmable Event Counter Description: Access: Read. 31 27 26 0 (Reserved) PEC2 PEC2 Register Bits Name 31:27 26:0 11.3.5 Description (Reserved). Always 0 PEC2 This is a 27-bit, read-only counter register.
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100 control plane processors PEC4 Register Bits Name 31:27 26:0 11.3.7 Description (Reserved). Always 0 PEC4 This is a 27-bit, read-only counter register. Programmable Event Counters (PEC5) Register Name: PEC5 Hex Offset Address: 0xC800 2018 Reset Hex Value: 0x00000000 Register Programmable Event Counter Description: Access: Read. 31 27 26 0 (Reserved) PEC5 PEC5 Register Bits Name 31:27 26:0 11.3.
Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance Monitoring Unit (IBPMU) 11.3.9 Programmable Event Counters (PEC7) Register Name: PEC7 Hex Offset Address: 0xC800 2020 Reset Hex Value: 0x00000000 Register Programmable Event Counter Description: Access: Read. 31 27 26 0 (Reserved) PEC7 PEC7 Register Bits Name 31:27 26:0 11.3.10 Description (Reserved). Always 0. PEC7 This is a 27-bit, read-only counter register.
Internal Bus Performance Monitoring Unit (IBPMU)—Intel® IXP42X product line and IXC1100 control plane processors Register Bits 11:8 7:4 3:0 September 2006 Order Number: 252480-006US PSMR (Sheet 2 of 2) Name Description PSN Indicates which of the Slaves on North AHB was previously accessed North AHB Masters: 0001 = SDRAM controller 0010 = AHB-AHB Bridge 0100 = (Reserved) 1000 = (Reserved) PMS Indicates which of the Masters on South AHB was previously accessing the South AHB: 0001 = Intel XScale p
Intel® IXP42X product line and IXC1100 control plane processors—General Purpose Input/ Output (GPIO) 12.0 General Purpose Input/Output (GPIO) The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor provide 16 general-purpose input/output (GPIO) pins for use in capturing and generating application specific input and output signals. Each GPIO can be programmed as either an input or an output. GPIO Pin 14 can be configured similar to GPIO pin 13 or as a clock output.
General Purpose Input/Output (GPIO)—Intel® IXP42X product line and IXC1100 control plane processors The General-Purpose Data Output Register is a 16-bit register with a one-for-one correspondence between the 16 bits of the General-Purpose Data Output Register and the 16-bit GPIO. When logic 1 is written to a bit in the General-Purpose Data Output Register — and the corresponding bit in the General-Purpose Enable Register is set to logic 0 — logic 1 will be replicated to the corresponding GPIO.
Intel® IXP42X product line and IXC1100 control plane processors—General Purpose Input/ Output (GPIO) • GPIT1R represents GPIO 0 through GPIO 7 • GPIT2R represents GPIO 8 through GPIO 15 • General-Purpose Interrupt Type Register 1 bits 0 through 2 represent GPIO0 • General-Purpose Interrupt Type Register 1 bits 3 through 5 represent GPIO2, … • General-Purpose Interrupt Type Register 1 bits 21 through 23 represent GPIO7 • General-Purpose Interrupt Type Register 2 bits 0 through 2 represent GPIO8 • General-Pu
General Purpose Input/Output (GPIO)—Intel® IXP42X product line and IXC1100 control plane processors Once an appropriate interrupt condition is reached, the corresponding bits are set in the General-Purpose Interrupt Status Register (GPISR). The General-Purpose Interrupt Status Register can be read in a polled mode or programmed to generate an interrupt.
Intel® IXP42X product line and IXC1100 control plane processors—General Purpose Input/ Output (GPIO) Table 146. GPIO Clock Frequency Select GPIO15 – Frequency Terminal Count GPIO14 – Frequency Terminal Count Frequency Bit 23 † Table 147. Bit 22 Bit 21 Bit 20 Bit 7 Bit 6 Bit 5 Bit 4 logic 1 0 0 0 0 0 0 0 0 33.33 MHz 0 0 0 1 0 0 0 1 22 MHz 0 0 1 0 0 0 1 0 16.5 MHz 0 0 1 1 0 0 1 1 13.2 MHz 0 1 0 0 0 1 0 0 11 MHz 0 1 0 1 0 1 0 1 9.
General Purpose Input/Output (GPIO)—Intel® IXP42X product line and IXC1100 control plane processors Table 147.
Intel® IXP42X product line and IXC1100 control plane processors—General Purpose Input/ Output (GPIO) GPOUTR Register Bits Name 31:16 12.4.2 Description (Reserved). Reads back 0.
General Purpose Input/Output (GPIO)—Intel® IXP42X product line and IXC1100 control plane processors Register Name: GPINR Hex Offset Address: 0xC800 4008 Reset Hex Value: 0x00000000 Register This register is used to monitor input pins. Description: Access: Read. 31 16 15 0 (Reserved) IN_LEV GPINR Register Bits Name 31:16 - 15:0 12.4.4 Description Not used. Ignored on writes and driven logic 0 on reads.
Intel® IXP42X product line and IXC1100 control plane processors—General Purpose Input/ Output (GPIO) Register Name: GPIT1R Hex Offset Address: 0xC800 4010 Reset Hex Value: 0x00000000 Register This register is used to control interrupt type for GPIO 7:0. Description: Access: See below. 31 24 23 (Reserved) 21 20 GPIO7 18 17 GPIO6 15 14 GPIO5 12 11 GPIO4 12.4.6 8 GPIO3 6 5 GPIO2 3 2 GPIO1 0 GPIO0 GPIT1R Register Bits 9 Name Description 31:24 Not used.
General Purpose Input/Output (GPIO)—Intel® IXP42X product line and IXC1100 control plane processors GPIT2R (Sheet 2 of 2) Register Bits Name 17:15 GPIO13 Not used. GPIO12 000 = Active High 001 = Active Low 010 = Rising Edge 011 = Falling Edge 1xx = Transitional Resets to 000 – Active High 14:12 12.4.
Intel® IXP42X product line and IXC1100 control plane processors—General Purpose Input/ Output (GPIO) Register GPCLKR (Sheet 2 of 2) Bits Name Description 8 MUX14 0 = Control from GPOUTR Register 1 = Clock Output Reset: 0 7:4 CLK0TC Terminal count for a 4-bit up counter @ PCLK. An F in this field and the CLK0DC field is a special case to provide PCLK/2. Reset: 0x0 3:0 CLK0DC Represents the number of counts for which clock output should be low.
General Purpose Input/Output (GPIO)—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 397
Intel® IXP42X product line and IXC1100 control plane processors—Interrupt Controller 13.0 Interrupt Controller The Interrupt Controller takes as inputs 32 individual interrupts. These 32 individual interrupts originate either from the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor internal blocks or from 14 dedicated GPIO pins.
Interrupt Controller—Intel® IXP42X product line and IXC1100 control plane processors pattern to the assignments above for the first eight interrupts with the last interrupt priority assignment being bits 21 through 23 of the interrupt priority register assigning a priority value to interrupt 7. The 3-bit interrupt priorities for each of the first eight interrupts can take on a value from 0 to 7.
Intel® IXP42X product line and IXC1100 control plane processors—Interrupt Controller For instance, interrupt number 0 is disabled and an interrupt occurs on interrupt number 0. The interrupt generated by interrupt number 0 will not be seen by the Intel XScale processor. The Interrupt-Enable Register is a 32-bit register that can individually enable or disable each of the 32 interrupts. Bit 0 of the Interrupt-Enable Register corresponds to interrupt number 0 (WAN/Voice NPE).
Interrupt Controller—Intel® IXP42X product line and IXC1100 control plane processors The FIQ Status Register and the IRQ Status Register are 32-bit registers that have a one-for-one relationship with the interrupt number. Interrupt number 0 (WAN/Voice NPE) will be the status represented on bit 0 of both the FIQ Status Register and the IRQ Status Registers. Interrupt number 31 will be the status represented on bit 31 of both the FIQ Status Register and the IRQ Status Registers.
Intel® IXP42X product line and IXC1100 control plane processors—Interrupt Controller Table 149. 13.5.
Interrupt Controller—Intel® IXP42X product line and IXC1100 control plane processors INTR_ST Register Default Priority Source Int21 21 GPIO GPIO[4] Int22 22 GPIO GPIO[5] Int23 23 GPIO GPIO[6] Int24 24 GPIO GPIO[7] Int25 25 GPIO GPIO[8] Int26 26 GPIO GPIO[9] Int27 27 GPIO GPIO[10] Int28 28 GPIO GPIO[11] Int29 29 GPIO GPIO[12] Int30 30 Expansion Bus SW Interrupt 0 Int31 31 Expansion Bus SW Interrupt 1 Interrup t Bit 1 (Sheet 2 of 2) Description 1.
Intel® IXP42X product line and IXC1100 control plane processors—Interrupt Controller 13.5.2 Interrupt-Enable Register Register Name: INTR_EN Hex Offset Address: 0xC800 3004 Reset Hex Value: 0x00000000 Provides enables for the interrupts. This register allows the Intel XScale processor to disable interrupts Register from selected blocks. Description: To enable an interrupt, a 1 is written into corresponding bit, to disable it, a 0 is written. Access: Read/Write. 31 0 Interrupt Enables 13.5.
Interrupt Controller—Intel® IXP42X product line and IXC1100 control plane processors 13.5.6 Interrupt Priority Register Register Name: INTR_PRTY Hex Offset Address: 0xC800 3014 Reset Hex Value: 0x00FAC688 The highest eight priority interrupts can be programmed via this register, each of the 3-bit sets can be Register programmed to any priority from 0(000) through 7(111). This register applies to both IRQ and FIQ Description: interrupts. Access: Read/Write.
Intel® IXP42X product line and IXC1100 control plane processors—Interrupt Controller INTR_IRQ_ENC_ST Register 13.5.
Interrupt Controller—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 407
Intel® IXP42X product line and IXC1100 control plane processors—Timers 14.0 Timers The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor contain four 32-bit internal timers that increment on the rising edge of a 66.66 MHz (which is 2* OSC_IN input pin.). The watch-dog timer is a 32-bit, down counter that may be used by software applications to monitor inactivity.
Timers—Intel® IXP42X product line and IXC1100 control plane processors The watch-dog interrupt enable bit enables and disables the interrupt that may be generated to the IXP42X product line and IXC1100 control plane processors Interrupt controller when the Watch-Dog Timer Down Counter reaches zero. When the watch-dog interrupt enable bit is set to logic 1, the Watch-Dog Timer Down Counter will cause an interrupt to be generated to the Interrupt Controller when the down counter reaches a value of zero.
Intel® IXP42X product line and IXC1100 control plane processors—Timers The general-purpose-timer, one-shot control bit will be used to select which of the preceding events take place after the general-purpose, timer-down counter reaches a value of 0.
Timers—Intel® IXP42X product line and IXC1100 control plane processors 14.4 Timer Register Definition Table 150.
Intel® IXP42X product line and IXC1100 control plane processors—Timers 14.4.3 General-Purpose Timer 0 Reload Register Name: OST_TIM0_RL Hex Offset Address: 0x C800 5008 Reset Hex Value: 0x00000000 Register General-Purpose Timer 0 Reload Description: Access: Read/Write. 31 2 OST_TIM0_RL Register 14.4.4 Name 31:2 reload_val 1 tim1_one_shot 0 tim0_enable 0 timer control reload_val Bits 1 Description Value loaded into ost_tim0. bits 1 and 0 will be 00.
Timers—Intel® IXP42X product line and IXC1100 control plane processors 14.4.5 General-Purpose Timer 1 Reload Register Name: OST_TIM1_RL Hex Offset Address: 0x C800 5010 Reset Hex Value: 0x00000000 Register General-Purpose Timer 1 Reload Description: Access: Read/Write. 31 2 OST_TIM1_RL Register 14.4.6 Name 31:2 reload_val 0 timer control reload_val Bits 1 Description 1 tim1_one_shot 0 tim1_enable Value loaded into ost_tim1. bits 1 and 0 will be 00.
Intel® IXP42X product line and IXC1100 control plane processors—Timers 14.4.7 Watch-Dog Enable Register Register Name: OST_WDOG_ENAB Hex Offset Address: 0x C800 5018 Reset Hex Value: 0x00000000 Register Watch-Dog Enable Register Description: Access: Read/Write. 31 16 15 3 OST_WDOG_ENAB Register Name 31:3 14.4.8 0 watch-dog enable bits (Reserved) Bits 2 Description (Reserved). Returns 0 if read 2 wdog_cnt_ena Watch-dog count enable bit.
Timers—Intel® IXP42X product line and IXC1100 control plane processors 14.4.9 Timer Status Register Name: OST_STATUS Hex Offset Address: 0x C800 5020 Reset Hex Value: 0x00000000 Register Timer Status Register Description: Access: Read/Bit Clear. 31 5 (Reserved) 0 ost status bits OST_STATUS Register Bits 4 Name Description 31:5 (Reserved). Returns 0 if read 4 warm_reset Logic 1 if a warm reset has occurred. A warm reset is when the watch-dog timer caused the reset to occur.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A 15.0 Ethernet MAC A The functionality supported by the MII Interfaces is tightly coupled with the code written on the Network Processor Engine (NPE) core. This chapter details the full hardware capabilities of the MII Interface contained within the Ethernet coprocessor of the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors One Management Data Interface is shared between the two MII interfaces. The single Management Data Interface is used to configure the physical devices attached to each of the MII interfaces. Figure 80 shows a typical application that may be used in connecting to the MII interface. Figure 80.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A • MII Interface • Management Data Interface 15.1.1 Ethernet Coprocessor APB Interface The APB interface is used to allow the Intel XScale® Processor to communicate directly to configuration and control registers utilized by the Media Access Controller.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors • Bits (25:21) of the MDIO Command (MDIOCMD) Register are used to select the physical interface that is to accept the transmitted data or return the requested data. • Bits (20:16) of the MDIO Command (MDIOCMD) Register are used to select the register within the physical interface that is to accept the transmitted data or return the requested data.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A Figure 82. MDIO Write PREAMBLE 32 consecutive 1s ST MDIOCMD2 (7:0) OC PHY ADDR REG ADDR TA (4:0) (4:0) MDIOCMD1 (7:0) MDC MDIO 4 3 2 1 0 4 3 2 1 0 15 14 13 121110 9 8 7 6 5 4 3 2 1 0 B2171-01 Notes: 1. ST (Start Bits) is a signal that is logic 0 followed by logic 1 after a PREAMBLE stage. 2. OC (Op Code) is a two-bit signal that informs the destination PHYs if the current requested transaction is a read or a write.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors Once the data has reached a predefined trigger point — known as the Buffer Size for Transmit Register (TXBUFFSIZE), in the Transmit FIFO — or the End-of-Frame signal is received, a data packet will begin to be transmitted over the MII interface.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A Transmit Control Register 1 can be accessed directly. Intel, however, recommends that the Transmit Control Register 1 values be manipulated through Intel supplied APIs. Failure to use the Intel-supplied APIs will result in unpredictable results. The Transmit Engine also can be configured to append additional bytes to frames that are smaller than the 64-byte frame minimum.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors period will be the number of transmit clock cycles specified by the 8-bit Transmit Deferral Register minus three transmit clock cycles. The Single Transmit Deferral parameter specifies the Inter Frame Gap. In the two-part deferral process the deferral period is defined using the Transmit Two Part Deferral Parameters 1 Register (TX2PARTDEFPARS1) and Transmit Two Part Deferral Parameters 2 Register (TX2PARTDEFPARS2).
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A Broadcast frames can be dropped and prevented from being sent to the NPE. To accomplish this, the following three conditions must be met: 1. Broadcast Disable bit “b7=1” of the Received Control Register RXCTRL1. 2. Address Mask Registers 1 to 6 are NOT 00 00 00 00 00 00. 3. Address Filter Enable bit “b5=1” of the Received Control Register RXCTRL1.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors (assuming bit 1 of Receive Control Register 1 is set to logic 1) and capture the remaining data. Padded bytes will not be removed from the received packet when bit 1 of Receive Control Register is set to logic 0. If the packet is less than 64 bytes and there are no padded bytes, the packet is determined to be a runt frame.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A The physical interface clock speed will be divided by the host-side clock speed and then rounded to the nearest whole number. The value from this calculation will be written to the Threshold for Internal Clock (THRESH_INTCLK) Register. For the IXP42X product line and IXC1100 control plane processors, the value contained in the Threshold for Internal Clock (THRESH_INTCLK) Register must always be set to hexadecimal 0x01.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2 Register Descriptions The internal registers shown below are accessible via the APB bus interface. Unspecified addresses are reserved and should not be written; if read, a zero value will be returned. All of the Ethernet internal configuration and control registers are directly readable and writeable by the Intel XScale processor via APB bus.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A Address 15.2.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2.2 Transmit Control 2 Register Name: txcrtl2 Hex Offset Address: 0xC8009004 Reset Hex Value: 0x00000000 Register Transmit Control Register Two Description: Access: Read/Write. 31 4 3 Maximum Retries (Reserved) Register 15.2.3 Bits Name 4:31 (Reserved) 3:0 Maximum retries 0 txcrtl2 Description Maximum number of retries for a packet when collisions occur.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A Register rxcrtl1 (Sheet 2 of 2) Bits Name Description 1 Pad strip 1 = Causes the pad bytes to be stripped from receive data. 0 Receive enable 1 = Causes reception to be enabled. Notes: Broadcast packets will only be dropped if the following three conditions are met. 1. “Broadcast Disable” bit,“b7=1”. 2. The Address M ask register is NOT 00 00 00 00 00 00. 3. “Address Filter Enable” bit, “b5=1”.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2.6 Threshold For Partially Empty Register Name: threshpe Hex Offset Address: 0xC8009030 Reset Hex Value: 0x00000000 Register FIFO Partially Full/Empty Threshold Register. The threshold is the number of 32-bit words in the FIFO. Description: Access: Read/Write. 31 8 7 (Reserved) Partial Empty Register Bits Name 31:8 (Reserved) 7:0 15.2.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A Register 15.2.9 Bits Name 31:8 (Reserved) 7:0 Tx Buffer size txbuffsize Description Holds minimum number of bytes of each frame that must be in the Transmit FIFO for that frame's transmission to start. If a complete frame is less than this minimum, it is always transmitted.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2.11 Transmit Two Part Deferral Parameters 1 Register Name: tx2partdefpars1 Hex Offset Address: 0xC8009060 Reset Hex Value: 0x00000000 Register Transmit Two Part Deferral Parameters Register 1. Description: Access: Read/Write. 31 8 7 (Reserved) First Deferral Period Register 15.2.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A Register 15.2.14 Bits Name 31:8 (Reserved) 7:0 Slot Time slottime Description Slot time for back-off algorithm Expressed in number of tx_clk cycles. 128 in MII mode.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2.17 MDIO Command 3 Register Name: mdiocm3 Hex Offset Address: 0x C8009088 Reset Hex Value: 0x00000000 Register MDIO Command Register Description: Access: Read/Write. 31 8 7 (Reserved) 15.2.18 0 MDIO_COMMAND [23:16] MDIO Command 4 Register Name: mdiocm4 Hex Offset Address: 0x C800908C Reset Hex Value: 0x00000000 Register MDIO Command Register Description: Access: Read/Write.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A 15.2.20 MDIO Status 1 Register Name: mdiosts1 Hex Offset Address: 0x C8009090 Reset Hex Value: 0x00000000 Register MDIO Status Register Description: Access: Read Only. 31 8 7 (Reserved) 15.2.21 0 MDIO_STATUS[7:0] MDIO Status 2 Register Name: mdiosts2 Hex Offset Address: 0x C8009094 Reset Hex Value: 0x00000000 Register MDIO Status Register Description: Access: Read Only. 31 8 7 (Reserved) 15.2.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors Register 15.2.24 MDIO Status Bits Name Description 31 Successful read 30:16 (Reserved) Read only. 15:0 Read data Read only. 0 = A successful read 1= A read error. Read only.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A 15.2.26 Address Mask 2 Register Name: addrmask2 Hex Offset Address: 0x C80090A4 Reset Hex Value: 0x00000000 Address Mask Register #1. Second register of six that makes up the Address Mask. Address Mask is used Register with Address for multicast address filtering.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2.30 Address Mask 6 Register Name: addrmask6 Hex Offset Address: 0x C80090B4 Reset Hex Value: 0x00000000 Address Mask Register #1. Sixth register of six that makes up the Address Mask. Address Mask is used Register with Address for multicast address filtering.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A 15.2.32 Address 1 Register Name: addr1 Hex Offset Address: 0x C80090C0 Reset Hex Value: 0x00000000 Address Register #1. First register of six that makes up the Address. Address Mask is used with Address Register for multicast address filtering.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2.36 Address 5 Register Name: addr5 Hex Offset Address: 0x C80090D0 Reset Hex Value: 0x00000000 Address Register #1. Fifth register of six that makes up the Address. Address Mask is used with Address Register for multicast address filtering.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A 15.2.38 Threshold for Internal Clock Register Name: thresh_intclk Hex Offset Address: 0xC80090E0 Reset Hex Value: 0x00000000 Register Threshold for Internal Clock Register Description: Access: Read/Write. 31 8 (Reserved) Register Bits Name 31:8 (Reserved) 7:0 15.2.39 Clock ratio 7 0 CLOCK RATIO thresh_intclk Description Holds ratio of PHY side clock (tx_clk or rx_clk) to sys_clk.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors 15.2.40 Unicast Address 1 Register Name: uniaddr1 Hex Offset Address: 0x C80090F0 Reset Hex Value: 0x00000000 Unicast Address Register #1. First register of six that makes up the Unicast Address. Matched with Register destination address of receive packets for unicast address filtering. (Receive Control Address Filter bit is Description: 1.) If a match occurs, the frame is passed to the NPE. Access: Read/Write.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A 15.2.44 Unicast Address 5 Register Name: uniaddr5 Hex Offset Address: 0x C8009100 Reset Hex Value: 0x00000000 Unicast Address Register #1. Fifth register of six that makes up the Unicast Address. Matched with Register destination address of receive packets for unicast address filtering. (Receive Control Address Filter bit is Description: 1.) If a match occurs, the frame is passed to the NPE. Access: Read/Write.
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors Register Bits Name 31:5 (Reserved) core_control Description 1 = Configures the MDC as an output clock. Set to 1 for the Intel® IXP42X product line and IXC1100 control plane processors MAC A. This bit is reserved on MAC B. 4 Mdc_en 3 Send_jam 1 = Causes a jam sequence to be sent if reception of a packet begins. 2 clr_tx_err Assertion (“1”) causes the Transmit FIFO to be flushed.
Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC B 16.0 Ethernet MAC B Not all of the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor have this functionality. See Table 152. Table 152. Processors’ with Ethernet Interface UTOPIA HSS MII 0 MII 1 AES / DES / 3DES Multi-Channel HDLC SHA-1 / MD-5 IXP425 X X X X X 8 X IXP423 X X X X X X X X X Device IXP422 IXP421 Table 153.
Ethernet MAC B—Intel® IXP42X product line and IXC1100 control plane processors Table 153.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces 17.0 High-Speed Serial Interfaces The functionality supported by the High-Speed Serial (HSS) interfaces are tightly coupled with the code written on the Network Processor Engine (NPE) core. This chapter details the full hardware capabilities of the HSS interfaces contained within the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors These buffers also behave in a ping-pong fashion, so the NPE will read two 32-bit words at a time for processing. The location that each received byte is placed into these FIFOs is a function of a user programmable look-up table (LUT) and the protocol that is being implemented.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces The actual FIFO the byte is extracted from is dependent upon the protocol implemented and the FIFO arrangement. For more details, see the Intel® IXP400 Software Programmer’s Guide. When the HSS transmit interface processes the third byte (time slot 2), the look-up table will indicate that the byte to be transmitted is an unassigned cell.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors • Loop back the transmit to receive interface internally. The following discussion briefly describes these features. For more detail on manipulating these settings, see the Intel® IXP400 Software Programmer’s Guide. The frame length can be set as a variable function with the maximum frame length being 1,024 bits.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces The frame-sync signal is used to allow the HSS interface to synchronize to external devices. The synchronization is obtained by the activity produced on the frame-sync signals. There is a separate frame-sync signal for both transmit and receive for each HSS interface. Using Intel supplied APIs, the HSS frame-sync signals can be programmed to be inputs or outputs.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors Either an internal or external frame-sync pulse or clock can still be utilized. When using the internal frame-sync pulse/clock, the transmit frame-sync pulse/clock is internally looped to the receive side of the HSS interface. If an external frame pulse/clock is used, the clock/frame-sync pulse must be supplied on the transmit frame-sync pulse/ clock pins.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces The behavior of the HSS interface is indifferent to the source of the frame-sync pulse. The frame-sync pulse can be sourced externally or generated internally. Figure 84 and Figure 85 shows an example of the HSS interfaces obtaining synchronization with no offset defined. Figure 84.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors There is one register titled the HSS Clock Divider Register that provides a means to generate a unique data clock for each of the two IXP42X product line and IXC1100 control plane processors’ HSS interfaces. This may help reduce BOM cost by eliminating the need for a clock oscillator in cases where the system can tolerate an imperfect data clock with a certain amount of jitter.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces Table 155. HSS Tx/Rx Clock Output 4.096 MHz 2 T1/E1 512 2 8.192 MHz 4 T1/E1 1,024 2 Notes: 1. These clock speeds are supported using the HSS API. However, the GCI protocol is not supported by the IXP400 software. 2. When the frequencies of 2.048, 4.096, or 8.192 MHz are used for T1, the data rate for each T1 remains at 1.544 MHz by making certain time slots within a frame unassigned and with no data.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors Table 158. Note: HSS Frame Output Characterization 4.096 MHz 512 62.496 -60.0096 8.192 MHz 1024 62.49624 -60.0096 PPM frame length error is calculated from ideal frame frequency. Table 159.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces Figure 86. T1 Transmit Frame hss_tx_clock hss_tx_frame hss_tx_data_out FBit data1 data2 data 191 data 192 FBit data1 In Figure 86, the FBit to be transmitted is stored in the HSS Transmit FIFO. The HSS knows which timeslot in the FIFO is holding the FBit, as it knows from the timeslot counter and frame offset when the FBit should be transmitted.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors • Frame sync active level (high/low). • MSb/LSb-first ordering for transmit and receive. • Data polarity, maintain or invert. • Select to use FBit (not data for T1) at frame start. • Select value for idle timeslots on transmit and unused bit in 56k timeslots. • Select buffer size. • Configure lookup tables. 17.6.2 E1 E1 is a High-Speed Serial stream operating at 2.048 MHz.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces Figure 89. E1 Receive Frame hss_rx_clock hss_rx_frame hss_rx_data data1 data2 data3 data255 data256 data1 data2 By using the IxHssAcc API, the following settings should be considered when configuring HSS interface for E1 operation: • Frame size 256 bits (for E1).
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors • Frame sync simultaneous with first data nibble - set TX frame offset and RX frame offset due to HSS logic, different values due to external device can be accommodated. • Select use of input/output TX/RX frame syncs. • Select use of input/output clock, and clock speed. • Select negative/positive clock for generating/sampling frame in transmit/receive.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces Figure 90. MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame 2.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors Figure 91. MVIP, Frame Mapping a T1 Frame to an E1 Frame 2.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces In Figure 92, the 'a' denotes the first E1 stream, the 'b' denotes the second E1 stream, the 2 streams are interlaced byte wise. Another method of placing E1 stream on this backplane is to process the first entire E1 stream followed by the second complete E2 stream (frame interleaving). Figure 93. MVIP, Byte Interleaving Two T1 Streams Onto a 4.096-Mbps Backplane 4.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors Figure 94. MVIP, Byte Interleaving Four E1 Streams on a 8.192-Mbps Backplane Bus 8.192 MHz clock Frame pulse 6 7 0 1 2 3 4 5 6 7 0 1 Bits Timeslots 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 2 3 4 7 31d 0a 0b 0c 0d 1a 1b 1c 1d 2a 2b 2c 2d 3a 3b 3c 3d 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 6d 7a 7b 7c 7d 8a8b 8c 8d 9a B4253-02 Figure 94 illustrates that 4 E1 streams can be byte interleaved.
Intel® IXP42X product line and IXC1100 control plane processors—High-Speed Serial Interfaces The second T1 frame is then processed and so on until all 4 frames are processed, this fills the entire 128 timeslots available. This mode is also programmable by the NPE.
High-Speed Serial Interfaces—Intel® IXP42X product line and IXC1100 control plane processors September 2006 Order Number: 252480-006US Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor DM 467
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.0 Universal Serial Bus (USB) v1.1 Device Controller This chapter describes the Universal Serial Bus (USB) protocol and its implementationspecific options for device controllers.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors Packets are assembled into groups to produce transactions. Transactions fall into four groups: • Bulk • Control • Interrupt • Isochronous Endpoint 0 is used only to communicate the control transactions that configure the UDC.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller Table 160.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors By decoding the polarity of the UDC+ and UDC- pins and using differential data, four distinct states are represented. Two of the four states are used to represent data. A 1 indicates that UDC+ is high and UDC- is low. A 0 indicates that UDC+ is low and UDCis high. The two remaining states and pairings of the four encodings are further decoded to represent the current state of the USB.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller Each time a 0 occurs, the receiver logic synchronizes the baud clock to the incoming data (thus producing the clock). To ensure the receiver is periodically synchronized, any time six consecutive 1s are detected in the serial bit stream, a 0 is automatically inserted by the transmitter. This procedure is known as “bit stuffing.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors The host is then responsible for assigning a unique address to each device on the bus. Addresses are assigned in the enumeration process, one device at a time. After the host assigns the an address to the UDC, the UDC only responds to transactions directed to that address. The Address field follows the PID in every packet transmitted.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.3.4 Packet Formats USB supports four packet types: • Token • Data • Handshake • Special A PRE (Preamble) PID precedes a low-speed (1.5 Mbps) USB transmission. The UDC supports high-speed (12 Mbps) USB transfers only. PRE packets that signify low-speed devices and the low-speed data transfer that follows such PRE packets are ignored. 18.3.4.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors A data packet consists of a sync; a PID; from 0 to 1,023 bytes of data; and a CRC16 field, as shown in Table 165. Note that the UDC supports a maximum of 8 bytes of data for an Interrupt IN data payload, a maximum of 64 bytes of data for a bulk data payload and a maximum of 256 bytes of data for an isochronous data payload. Table 165. 18.3.4.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller Table 167.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors To assemble control transfers, the host sends a control transaction to tell the UDC what type of control transfer is taking place (control read or control write), followed by one or more data transactions. The setup is the first stage of the control transfer. The device must respond with an ACK or no handshake (if the data is corrupted).
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller • Number of bytes to transfer • Index or offset • Value: used to pass a variable-sized data parameter • Device request Table 171 shows a summary of all device requests. For a full description of host device requests, see the Universal Serial Bus Specification Revision 1.1. Table 171.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors When the device responds to the host, it must specify a legal USB configuration. For example, if the device specifies a configuration of six isochronous endpoints of 256 bytes each, the host is not able to schedule the proper bandwidth and does not take the UDC out of Configuration 0. The user device determines which endpoints to report to the host.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller A control register enables the UDC and masks the interrupt sources in the UDC. A status register indicates the state of the interrupt sources. Each of the 16 endpoints (control, OUT, and IN) have a control or status register. Endpoint 0 (control) has an address for the 16-by-8 data FIFO that can be used to transmit and receive data.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors Table 172. 18.5.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.1.4 Resume Interrupt Request (RESIR) The resume interrupt request bit is set if the SRM bit in the UDC control register is cleared, the UDC is currently in the suspended state, and the USB is driven with resume signalling. 18.5.1.5 Suspend Interrupt Request (SUSIR) The suspend interrupt request register is set when the USB remains idle for more than 6 ms.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors UDCCR Register Bits Name 31:8 18.5.2 Description Reserved for future use Reset interrupt mask.(read/write) 0 = Reset interrupt enabled. 1 = Reset interrupt disabled. 7 REM 6 RSTIR Reset interrupt request (read/write 1 to clear). 1 = UDC was reset by the host. 5 SRM Suspend/resume interrupt mask (read/write). 0 = Suspend/resume interrupt enabled.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller The status stage for all other USB Standard Commands that do not have a data stage, such as SET_ADDRESS, SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and CLEAR_FEATURE, is handled by the UDC and the software must not set IPR. 18.5.2.3 Flush Tx FIFO (FTF) The Flush Tx FIFO bit triggers the reset of the endpoint 0 transmit FIFO.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors Register Name: UDCCS0 Hex Offset Address: 0 x C800B010 Reset Hex Value: 0 x 00000000 Register Universal Serial Bus Device Controller Endpoint 0 Control and Status Register Description: Access: Read/Write 6 5 4 3 2 1 0 FST SST DRWF FTF IPR OPR 8 (Reserved) 7 SA 31 RNE Bits 0 0 0 0 0 0 0 0 X Resets (Above) UDCCS0 Register Bits Name 31:8 18.5.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.3.2 Transmit Packet Complete (TPC) The transmit packet complete bit is set by the UDC when an entire packet is sent to the host. When this bit is set, the IR1 bit in the appropriate UDC status/interrupt register is set if transmit interrupts are enabled. This bit can be used to validate the other status/ error bits in the endpoint 1control/status register.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.3.7 Bit 6 Reserved Bit 6 is reserved for future use. 18.5.3.8 Transmit Short Packet (TSP) The software uses the transmit short packet bit to indicate that the last byte of a data transfer to the FIFO has occurred. This indicates to the UDC that a short packet or zerosized packet is ready to transmit. Software must not set this bit if a 64-byte packet is to be transmitted.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.4.1 Receive FIFO Service (RFS) The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the packet has been error checked by the UDC. A complete packet may be 64 bytes, a short packet, or a zero packet. This bit is not cleared until all data has been read from both buffers. 18.5.4.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors This bit must be polled when the UDCCS2[RPC] bit is set to determine if there is any data in the FIFO that the Intel XScale® processor did not read. The receive FIFO must continue to be read until this bit clears or data will be lost. 18.5.4.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.5 UDC Endpoint 3 Control/Status Register (UDCCS3) The UDC endpoint 3control status register contains four bits that are used to operate endpoint 3, an Isochronous IN endpoint. 18.5.5.1 Transmit FIFO Service (TFS) The transmit FIFO service bit is be set if one or fewer data packets remain in the transmit FIFO. UDCCS3[TFS] is cleared when two complete data packets are in the FIFO.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.5.8 Transmit Short Packet (TSP) Software uses the transmit short packet to indicate that the last byte of a data transfer has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit. Software must not set this bit if a packet of 256 bytes is to be transmitted.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDCCS4[RFS] is not cleared until all data is read from both buffers. 18.5.6.2 Receive Packet Complete (RPC) The receive packet complete bit gets set by the UDC when an OUT packet is received. When this bit is set, the IR4 bit in the appropriate UDC status/interrupt register is set if receive interrupts are enabled.
Universal Serial Bus (USB) v1.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller This bit can be used to validate the other status/error bits in the Endpoint 5 Control/ Status Register. The UDCCS5[TPC] bit is cleared by writing a 1 to it. This clears the interrupt source for the IR5 bit in the appropriate UDC status/interrupt register, but the IR5 bit must also be cleared.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.7.8 Transmit Short Packet (TSP) Software uses the transmit short to indicate that the last byte of a data transfer has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit. Software must not set this bit if a packet of 8 bytes is to be transmitted. When the data packet is successfully transmitted, the UDC clears this bit.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.8.1 Transmit FIFO Service (TFS) The transmit FIFO service bit is active if one or fewer data packets remain in the transmit FIFO. TFS is cleared when two complete packets of data remain in the FIFO. A complete packet of data is signified by loading 64 bytes of data or by setting UDCCS6[TSP]. 18.5.8.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors To ensure that no data is transmitted after the Clear Feature command is sent and the host resumes IN requests, software must clear the transmit FIFO by setting the UDCCS6[FTF] bit. 18.5.8.7 Bit 6 Reserved Bit 6 is reserved for future use. 18.5.8.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.9 UDC Endpoint 7 Control/Status Register (UDCCS7) The UDC Endpoint 7 Control/Status Register contains seven bits that are used to operate endpoint 7, a Bulk OUT endpoint. 18.5.9.1 Receive FIFO Service (RFS) The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the packet has been error checked by the UDC.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors To ensure that no data is transmitted after the Clear Feature command is sent and the host resumes IN requests, software must clear the transmit FIFO by setting the UDCCS7[FTF] bit. 18.5.9.7 Receive FIFO Not Empty (RNE) The receive FIFO not empty bit indicates that unread data remains in the receive FIFO.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDCCS7 (Sheet 2 of 2) Register Bits Name 2 18.5.10 Description (Reserved). Always reads zero. 1 RPC Receive packet complete (read/write 1 to clear). 0 = Error/status bits invalid. 1 = Receive packet has been received and error/status bits are valid. 0 RFS Receive FIFO service (read-only). 0 = Receive FIFO has less than 1 data packet. 1 = Receive FIFO has 1 or more data packets.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.10.6 Bit 5 Reserved Bit 5 is reserved for future use. 18.5.10.7 Bit 6 Reserved Bit 6 is reserved for future use. 18.5.10.8 Transmit Short Packet (TSP) Software uses the transmit short packet to indicate that the last byte of a data transfer has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.11 UDC Endpoint 9 Control/Status Register (UDCCS9) The UDC Endpoint 9 Control/Status Register contains six bits that are used to operate endpoint 9, an isochronous OUT endpoint. 18.5.11.1 Receive FIFO Service (RFS) The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the packet has been error checked by the UDC.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors UDCCS9[RSP] clears when the next OUT packet is received.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller This bit can be used to validate the other status/error bits in the Endpoint 10 Control/ Status Register. The UDCCS10[TPC] bit is cleared by writing a 1 to it. This clears the interrupt source for the IR10 bit in the appropriate UDC status/interrupt register, but the IR10 bit must also be cleared.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.12.8 Transmit Short Packet (TSP) Software uses the transmit short packet to indicate that the last byte of a data transfer has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit. Software must not set this bit if a packet of 8 bytes is to be transmitted. When the data packet is successfully transmitted, the UDC clears this bit.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.13.1 Transmit FIFO Service (TFS) The transmit FIFO service bit is active if one or fewer data packets remain in the transmit FIFO. TFS is cleared when two complete packets of data remain in the FIFO. A complete packet of data is signified by loading 64 bytes of data or by setting UDCCS11[TSP]. 18.5.13.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors The UDCCS11[SST] bit is set when the STALL state is actually entered, but this may be delayed if the UDC is active when the UDCCS11[FST] bit is set. The UDCCS11[FST] bit is automatically cleared when the UDCCS11[SST] bit is set.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDCCS11 (Sheet 2 of 2) Register 18.5.14 Bits Name Description 2 FTF Flush Tx FIFO (always read 0/ write a 1 to set). 1 = Flush Contents of TX FIFO. 1 TPC Transmit packet complete (read/write 1 to clear). 0 = Error/status bits invalid. 1 = Transmit packet has been sent and error/status bits are valid. 0 TFS Transmit FIFO service (read-only).
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors To allow the software to continue to send the STALL condition on the USB bus, the UDCCS12[FST] bit must be set again. The Intel XScale® processor writes a 1 to the sent stall bit to clear it. 18.5.14.6 Force Stall (FST) The Intel XScale® processor can set the force stall bit to force the UDC to issue a STALL handshake to all OUT tokens.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDCCS12 Register Bits Name 31:8 18.5.15 Description Reserved for future use. 7 RSP Receive short packet (read only). 1 = Short packet received and ready for reading. 6 RNE Receive FIFO not empty (read-only). 0 = Receive FIFO empty. 1 = Receive FIFO not empty. 5 FST Force stall (read/write). 1 = Issue STALL handshakes to OUT tokens. 4 SST Sent stall (read/write 1 to clear).
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors The bit’s read value is zero. 18.5.15.4 Transmit Underrun (TUR) The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When the UDC experiences an underrun, UDCCS13[TUR] generates an interrupt. UDCCS13[TUR] is cleared by writing a 1 to it. 18.5.15.5 Bit 4 Reserved Bit 4 is reserved for future use. 18.5.15.6 Bit 5 Reserved Bit 5 is reserved for future use. 18.5.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDCCS13 (Sheet 2 of 2) Register 18.5.16 Bits Name Description 3 TUR Transmit FIFO underrun (read/write 1 to clear). 1 = Transmit FIFO experienced an underrun. 2 FTF Flush Tx FIFO (always read 0/ write a 1 to set). 1 = Flush Contents of TX FIFO. 1 TPC Transmit packet complete (read/write 1 to clear). 0 = Error/status bits invalid.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.16.7 Receive FIFO Not Empty (RNE) The receive FIFO not empty bit indicates that the receive FIFO has unread data in it. When the UDCCS14[RPC] bit is set, this bit must be read to determine if there is any data in the FIFO that Intel XScale® processor did not read. The receive FIFO must continue to be read until this bit clears or data will be lost. 18.5.16.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDCCS14 (Sheet 2 of 2) Register 18.5.17 Bits Name Description 2 ROF Receive overflow (read/write 1 to clear). 1 = Isochronous data packets are being dropped from the host because the receiver is full. 1 RPC Receive packet complete (read/write 1 to clear). 0 = Error/status bits invalid. 1= Receive packet has been received and error/status bits are valid.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.17.5 Sent STALL (SST) The sent stall bit is set by the UDC in response to FST successfully forcing a userinduced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation from the host PC when a STALL handshake is returned automatically.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDCCS15 Register Bits Name 31:8 7 Reserved for future use. TSP 6 18.5.18 Description Transmit short packet (read/write 1 to set). 1 = Short packet ready for transmission. (Reserved). Always reads 0. 5 FST Force STALL (read/write). 1 = Issue STALL handshakes to IN tokens. 4 SST Sent STALL (read/write 1 to clear). 1 = STALL handshake was sent.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors UICR0 Register Bits Name 31:8 18.5.19 Description Reserved for future use. 7 IM7 Interrupt Mask for Endpoint 7. 0 = Receive interrupt enabled. 1 = Receive interrupt disabled. 6 IM6 Interrupt Mask for Endpoint 6. 0 = Transmit interrupt enabled. 1 = Transmit interrupt disabled. 5 IM5 Interrupt mask for Endpoint 5. 0 = Transmit interrupt enabled. 1 = Transmit interrupt disabled.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller Register Name: UICR1 Hex Offset Address: 0 x C800B054 Reset Hex Value: 0x000000FF Register Universal Serial Bus Device Controller Interrupt Control Register 1 Description: Access: Read/Write 6 5 4 3 2 1 0 IM12 IM11 IM10 IM9 IM8 (Reserved) 7 IM13 8 IM14 31 IM15 Bits 1 1 1 1 1 1 1 1 Resets (Above) UICR1 Register Bits Name 31:8 18.5.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors The bits in USIR0 and USIR1 are controlled by a mask bit in the UDC Interrupt Control Register (UICR0/1). The mask bits, when set, prevent a status bit in the USIRx from being set. If the mask bit for a particular status bit is cleared and an interruptible condition occurs, the status bit is set. To clear status bits, the Intel XScale® processor must write a 1 to the position to be cleared.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.20.7 Endpoint 6 Interrupt Request (IR6) The interrupt request bit gets set if the IM6 bit in the UDC Interrupt Control Register is cleared and the IN packet complete (TPC) in UDC endpoint 6 control/status register gets set. The IR6 bit is cleared by writing a 1 to it. 18.5.20.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.21 UDC Status/Interrupt Register 1 (USIR1) 18.5.21.1 Endpoint 8 Interrupt Request (IR8) The interrupt request bit is set if the IM8 bit in the UDC Interrupt Control Register is cleared and the IN packet complete (TPC) or Transmit Underrun (TUR) in UDC Endpoint 8 Control/Status Register is set. The IR8 bit is cleared by writing a 1 to it. 18.5.21.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.21.8 Endpoint 15 Interrupt Request (IR15) The interrupt request bit is set if the IM15 bit in the UDC interrupt control is set. The IR15 bit is cleared by writing a 1 to it.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.22.2 Isochronous Packet Error Endpoint 4 (IPE4) The isochronous packet error for Endpoint 4 is set if Endpoint 4 is loaded with a data packet that is corrupted. This status bit is used in the interrupt generation of endpoint 4. To maintain synchronization, the software must monitor this bit when it services an SOF interrupt and reads the frame number.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UFNHR Register Bits Name 31:8 18.5.23 Description Reserved for future use. 7 SIR SOF Interrupt Request (read/write 1 to clear). 1 = SOF has been received. 6 SIM SOF interrupt mask. 0 = SOF interrupt enabled. 1 = SOF interrupt disabled. 5 IPE14 Isochronous Packet Error Endpoint 14 (read/write 1 to clear). 1 = Status indicator that data in the endpoint fifo is corrupted.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.24.1 Endpoint 2 Byte Count (BC[7:0]) The byte count is updated after each byte is read. When software receives an interrupt that indicates the endpoint has data, it can read the byte count register to determine the number of bytes that remain to be read. The number of bytes that remain in the input buffer is equal to the byte count +1.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UBCR4 Register Bits Name 31:8 7:0 18.5.26 Description (Reserved) Byte Count (read-only). Number of bytes in the FIFO is Byte Count plus 1 (BC+1). BC UDC Byte Count Register 7 (UBCR7) The Byte-Count Register maintains the remaining byte count in the active buffer of out endpoint 7. 18.5.26.1 Endpoint 7 Byte Count (BC[7:0]) The byte count is updated after each byte is read.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors Register Name: UBCR9 Hex Offset Address: 0 x C800B074 Reset Hex Value: 0x00000000 Register Universal Serial Bus Device Endpoint 9 Byte Count Description: Access: Read-Only Bits 31 8 7 0 (Reserved) BC[7:0] X 0 0 0 0 0 0 0 0 Resets (Above) UBCR9 Register Bits Name 31:0 7:0 18.5.28 Description (Reserved) Byte Count (read-only).
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller 18.5.29 UDC Byte Count Register 14 (UBCR14) The Byte-Count Register maintains the remaining byte count in the active buffer of out endpoint 14. 18.5.29.1 Endpoint 14 Byte Count (BC[7:0]) The byte count is updated after each byte is read.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors Register Name: UDDR0 Hex Offset Address: 0 x C800B080 Reset Hex Value: Register Description: 0x00000000 Universal Serial Bus Device Endpoint 0 Data Register Access: Read/Write Bits 31 8 0 (Reserved) (Data) X Resets (Above) UDDR0 Register Bits Name 31:8 7:0 18.5.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller Since it is double-buffered, up to two packets of data may be ready. Via direct read from the Intel XScale® processor, the data can be removed from the UDC. If one packet is being removed and the packet behind it has already been received, the UDC will issue a NAK to the host the next time it sends an OUT packet to endpoint 2.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.34 UDC Data Register 4 (UDDR4) Endpoint 4 is a double-buffered, isochronous OUT endpoint that is 256 bytes deep. The UDC generates an interrupt when the EOP is received. Because it is double-buffered, up to two packets of data may be ready. The data can be removed from the UDC via a direct read from the Intel XScale® processor.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDDR5 Register Bits Name 31:8 7:0 18.5.36 Description Reserved for future use. DATA Top of endpoint data currently being loaded. UDC Data Register 6 (UDDR6) Endpoint 6 is a double-buffered, bulk IN endpoint that is 64 bytes deep. Data can be loaded via direct Intel XScale® processor writes. Because it is double-buffered, up to two packets of data may be loaded for transmission.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors Register Name: UDDR7 Hex Offset Address: 0 x C800B680 Reset Hex Value: 0x00000000 Register Universal Serial Bus Device Endpoint 7 Data Register Description: Access: Read Bits 31 8 7 0 (Reserved) (8-Bit Data) X 0 0 0 0 0 0 0 0 Resets (Above) UDDR7 Register Bits Name 31:8 7:0 18.5.38 Description Reserved for future use. DATA Top of endpoint data currently being read.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller Because it is double-buffered, up to two packets of data may be ready. The data can be removed from the UDC via a direct read from the Intel XScale® processor. If one packet is being removed and the packet behind it has already been received, the UDC issues a NAK to the host the next time it sends an OUT packet to Endpoint 9.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors 18.5.41 UDC Data Register 11 (UDDR11) Endpoint 11 is a double-buffered, bulk IN endpoint that is 64 bytes deep. Data can be loaded via direct Intel XScale® processor writes. Because it is double-buffered, up to two packets of data may be loaded for transmission.
Intel® IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB) v1.1 Device Controller UDDR11 Register Bits Name 31:8 7:0 18.5.43 Description Reserved for future use. DATA Top of endpoint data currently being loaded. UDC Data Register 13 (UDDR13) Endpoint 13 is a double-buffered, isochronous IN endpoint that is 256 bytes deep. Data can be loaded via direct Intel XScale® processor writes.
Universal Serial Bus (USB) v1.1 Device Controller—Intel® IXP42X product line and IXC1100 control plane processors Register Name: UDDR14 Hex Offset Address: 0 x C800BE00 Reset Hex Value: 0x00000000 Register Universal Serial Bus Device Endpoint 14 Data Register Description: Access: Read Bits 31 8 7 0 (Reserved) (8-Bit Data) X 0 0 0 0 0 0 0 0 Resets (Above) UDDR14 Register Bits Name 31:8 7:0 18.5.45 Description Reserved for future use.
Intel® IXP42X product line and IXC1100 control plane processors—UTOPIA Level-2 19.0 UTOPIA Level-2 The functionality supported by the UTOPIA Level-2 interface is tightly coupled with the code written on the Network Processor Engine (NPE). This chapter details the full hardware capabilities of the UTOPIA-2 interface contained within the UTOPIA Level-2 coprocessor of the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor.
UTOPIA Level-2—Intel® IXP42X product line and IXC1100 control plane processors When operating in single-PHY (SPHY) mode, the UTOPIA Level-2 interface will support octet- or cell-level handshaking as defined by the UTOPIA Level-2 specification. When configured in multiple-PHY (MPHY) mode, only cell-level handshaking is supported. The hardware interface allows connection of up to 31 physical interface devices, as defined in the UTOPIA Level-2 specification.
Intel® IXP42X product line and IXC1100 control plane processors—UTOPIA Level-2 Figure 97. UTOPIA Level-2 Coprocessor UTOPIA Coprocessor UTOPIA Level 2 Receive Interface UTOPIA Level 2 Transmit Interface 19.
UTOPIA Level-2—Intel® IXP42X product line and IXC1100 control plane processors To allow the most flexibility, a logical address to physical address table is provided. The look-up table makes it possible for the five addresses — that were called out, above — not to be in sequential order. For example, the following logical to physical address map could be used for the above example of five physical interfaces.
Intel® IXP42X product line and IXC1100 control plane processors—UTOPIA Level-2 • There are eight active physical interfaces connected, named A through H, that map to logical address 0 through 7. • Physical Interface A is the currently selected physical interface for clock cycles 0 through18. • Notice on clock 8 that the result from Physical Interface G is that Physical Interface G is ready to receive a cell.
UTOPIA Level-2—Intel® IXP42X product line and IXC1100 control plane processors In addition to supporting data transmission and HEC generation, the Transmit Module maintains some statistical values. The statistics that can be maintained are on a single physical port address on a specified VPI/VCI address value.
Intel® IXP42X product line and IXC1100 control plane processors—UTOPIA Level-2 control plane processors by driving their UTP_IP_FCI (also known as RX_EMPTY_N/ RX_CLAV) signal, to inform the UTOPIA Level-2 Interface that the physical interface is ready to send a cell. The Receive Port Status (RXPORTSTAT) register, contained within the Receive Module, stores the polling result for each of the physical interfaces.
UTOPIA Level-2—Intel® IXP42X product line and IXC1100 control plane processors Figure 99. UTOPIA Level-2 MPHY Receive Polling 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 27 UTP_RX_CLK UTP_RX_ADDR (4:0) D E F G H A B C A G H 53 1 D E F UTP_RX_FCI (a.k.a. – RX_CLAV) UTP_RX_FCO (a.k.a.
Intel® IXP42X product line and IXC1100 control plane processors—UTOPIA Level-2 19.4 MPHY Polling Routines The UTOPIA Level-2 coprocessor implements a round-robin polling algorithm. The Receive and Transmit modules use a logical-to-physical address-translation table to determine the actual physical interface that is to be polled. This feature allows the designer complete control over the physical address polling sequence.
UTOPIA Level-2—Intel® IXP42X product line and IXC1100 control plane processors The UTOPIA Level-2 interface requires both transmit and receive clock inputs to be supplied from an external source. The transmit module and receive module of the UTOPIA Level-2 interface can have independent clocks running at separate clock speeds.
Intel® IXP42X product line and IXC1100 control plane processors—JTAG Interface 20.0 JTAG Interface The JTAG signals JTG_TCK, JTG_TRST_N, and JTAG_TDI will be routed to both the Test Logic Unit (TLU) and the Intel XScale® Processor. The Test Logic Unit is a unit that is provided to implement JTAG functions that are specific the Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor.
JTAG Interface—Intel® IXP42X product line and IXC1100 control plane processors Figure 100.
Intel® IXP42X product line and IXC1100 control plane processors—JTAG Interface Test logic operation is designed such that no disturbance is caused to on-chip system logic operation as the result of such an error. 20.1.2 Run-Test/Idle State The TAP controller enters the Run-Test/Idle state between scan operations. The controller remains in this state as long as the JTG_TMS is held at logic 0.
JTAG Interface—Intel® IXP42X product line and IXC1100 control plane processors 20.1.6 Exit1-DR State The Exit1-DR state is a temporary controller state. When the TAP controller is in the Exit1-DR state and JTG_TMS is logic 1 on the rising edge of JTG_TCK, the controller enters the Update-DR state, which terminates the scanning process. If JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller enters the Pause-DR state. The instruction does not change while the TAP controller is in this state.
Intel® IXP42X product line and IXC1100 control plane processors—JTAG Interface 20.1.10 Select-IR-Scan State The Select-IR Scan state is a temporary controller state. The test data registers selected by the current instruction retain their previous state. In this state, if JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated.
JTAG Interface—Intel® IXP42X product line and IXC1100 control plane processors The instruction does not change and the instruction register retains its state. The controller remains in this state as long as JTG_TMS is logic 0. When JTG_TMS changes to logic 1 on the rising edges of JTG_TCK, the controller moves to the Exit2-IR state. 20.1.15 Exit2-IR State The Exit2-IR state is a temporary state.
Intel® IXP42X product line and IXC1100 control plane processors—JTAG Interface Table 174. JTAG Instruction Set (Sheet 2 of 2) Op Code Intel XScale® Processor or IXP425 Op Code (X= XScale, I = IXP425, R = Reserved) Instruction Name 0000011 R Reserved 0000111 X LDIC Used for loading the Intel XScale processor instruction cache. 0001001 X DCSR Used for accessing the Debug Control/Status Register.
JTAG Interface—Intel® IXP42X product line and IXC1100 control plane processors Data is received, from JTG_TDI, through a shift register and exits through JTG_TDO one bit at a time on the rising edge of JTG_TCK. The data can then be copied (parallel loaded) into the associated read/write register when the data-register_write command is loaded in the JTAG Instruction Register and the TAP controller enters the Update-DR state.
Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM) 21.0 AHB Queue Manager (AQM) The purpose of this chapter is to outline the functionality of the AHB Queue Manager (AQM) which helps users to better understand the software and hardware architecture. The Intel® IXP400 Software manages these queues. 21.1 Overview The AHB Queue Manager (AQM) provides queue functionality for various internal blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM.
AHB Queue Manager (AQM)—Intel® IXP42X product line and IXC1100 control plane processors • Provides Underflow and Overflow Status Flags for each of the queues 0-31 • Two Intel XScale processor interrupts, one for queues 0-31 and one for queues 3263 • Individual interrupt enables for each queue • Programmable interrupt source for each of the queues 0-31 as the assertion or deassertion of 1 of 4 status flags, E, NE, NF or F • NE status flag used as the interrupt source for each of the queues 32-63 • Provides
Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM) returned via the AHB and for a queue write request, the data from the AHB is written into the queue. Following a queue access, the read or write pointer is incremented and the status for the accessed queue is updated as needed 21.4 AHB Interface The AHB interface provides read/write access to all AQM configuration/status registers, queues and SRAM. The AQM is a slave with a 32 bit data bus configuration on the AHB.
AHB Queue Manager (AQM)—Intel® IXP42X product line and IXC1100 control plane processors Table 176. AHB Queue Manager Memory Map 0x00417 Queue 0 to 31 Underflow/Overflow Status Register 2 x 4 Bytes 0x00410 0x0040F Queue 0 to 31 Interrupt Status Register 4 x 4 bytes 0x00400 0x003FF Queue 0 to 63 Read/Write Access 64 x 16 bytes 0x00000 21.4.
Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM) interface is written into SRAM at the calculated queue address. When the read and write pointers are equal, the queue is either full or empty as determined by the full or empty status flags. When a read request of an empty queue buffer is performed, queue control will return zeroes in the data field to the AHB interface and will set the Underflow Status Flag.
AHB Queue Manager (AQM)—Intel® IXP42X product line and IXC1100 control plane processors than or equal to the full watermark, the queue is considered nearly full. If the number of completely full entries is less than or equal to the empty watermark, the queue is considered nearly empty. Of course, status may be read at any time by an AHB read of the appropriate status register. The status read will reflect the status of the queue at the time of the read, respecting all previous AHB operations.
Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM) bus. Following each queue access where queue status is updated, status will be transmitted on the Flag Bus, and only then. The Flag Bus Strobe(s) will be asserted high for one clock cycle to indicate the presence of status on the Flag Bus. 21.4.2.3 Status Interrupts Two processor interrupts will be provided, one for queues 0-31, aqm_int[0], and one for queues 32-63, aqm_int[1].
AHB Queue Manager (AQM)—Intel® IXP42X product line and IXC1100 control plane processors Register Name: QUEACC (0 <= n <=63) Physical Address: Queue #n 0x(0000 + 16n + 4x) Register Description: Access: Reset Hex Value: Not Applicable Queue #n access register. There are 1-4 addresses (0 <= x <=3), as determined by the programmed entry size, for requesting read/write accesses to individual queues. No physical data resides at these addresses.
Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM) Register Name: Physical Address: Register Description: QUEUOSTAT (0 <= n <=1) Queue #n 0x(0410 + 4n) Reset Hex Value: 0x00000000 Queue underflow/overflow status register for the queues 0-31. OF/UF: ‘1’ – Overflow/Underflow has occurred Access: Read/Write 21.5.
AHB Queue Manager (AQM)—Intel® IXP42X product line and IXC1100 control plane processors Register Name: QUEUPPSTATF 0x041C Physical Address: Register Description: Reset Hex Value: 0x00000000 Queue status register for queues 32-63. F: ‘1’ – flag set 21.5.
Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM) 21.5.7 Queue Interrupt Enable Register 0 – 1 Register Name: QUEIEREG(0 <= n <=1) Reg #n 0x(0430 + 4n) Physical Address: Register Description: Reset Hex Value: 0x00000000 Interrupt enables for the queues 0-63. IE: ‘1’ – Enable 21.5.
AHB Queue Manager (AQM)—Intel® IXP42X product line and IXC1100 control plane processors empty queues but until the queue configuration words have been set, this state is somewhat inconsistent. Write accesses to any of the Queue Configuration Words 0-31 cause the corresponding queue status to be communicated on the Flag Bus. Once the AQM is fully configured, these configuration words should be used for read only purposes to monitor queue pointers.
Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM) Register Name: QUECONFIG (0 <= n <=63) Physical Address: Queue #n 0x(2000 + 4n) Reset Hex Value: 0xUUUUUUUU Register Description: Queue #n configuration word located in SRAM. Access: 31 24 23 Queue (n) Queue (n) NF NE Watermark Watermark Register Q (n) Buffer Size Q (n) Entry Size 16 15 Queue (n) Base Address 8 Res.
