User's Manual

4-36 Vol. 3

PAGING

Page-fault exceptions occur only due to an attempt to use a linear address. Failures

to load the PDPTE registers with PAE paging (see Section 4.4.1) cause general-

protection exceptions (#GP(0)) and not page-fault exceptions.

4.8 ACCESSED AND DIRTY FLAGS

For any paging-structure entry that is used during linear-address translation, bit 5 is

the accessed flag.

For paging-structure entries that map a page (as opposed to

referencing another paging structure), bit 6 is the dirty flag. These flags are

provided for use by memory-management software to manage the transfer of pages

and paging structures into and out of physical memory.

Whenever the processor uses a paging-structure entry as part of linear-address

translation, it sets the accessed flag in that entry (if it is not already set).

Whenever there is a write to a linear address, the processor sets the dirty flag (if it is

not already set) in the paging-structure entry that identifies the final physical

address for the linear address (either a PTE or a PDE in which the PS flag is 1).

Memory-management software may clear these flags when a page or a paging struc-

ture is initially loaded into physical memory. These flags are “sticky,” meaning that,

once set, the processor does not clear them; only software can clear them.

A processor may cache information from the paging-structure entries in TLBs and

paging-structure caches (see Section 4.10). This fact implies that, if software

changes an accessed flag or a dirty flag from 1 to 0, the processor might not set the

corresponding bit in memory on a subsequent access using an affected linear

address (see Section 4.10.3.3). See Section 4.10.3.2 for how software can ensure

that these bits are updated as desired.

NOTE

The accesses used by the processor to set these flags may or may not

be exposed to the processor’s self-modifying code detection logic. If

the processor is executing code from the same memory area that is

being used for the paging structures, the setting of these flags may

or may not result in an immediate change to the executing code

stream.

1. With PAE paging, the PDPTEs are not used during linear-address translation but only to load the

PDPTE registers for some executions of the MOV CR instruction (see Section 4.4.1). For this rea-

son, the PDPTEs do not contain accessed flags with PAE paging.