User's Manual

6-8 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
EFLAGS.OF (overflow) flag. The trap handler for this exception resolves the overflow
condition. Upon return from the trap handler, program or task execution continues at
the instruction following the INTO instruction.
The abort-class exceptions do not support reliable restarting of the program or task.
Abort handlers are designed to collect diagnostic information about the state of the
processor when the abort exception occurred and then shut down the application and
system as gracefully as possible.
Interrupts rigorously support restarting of interrupted programs and tasks without
loss of continuity. The return instruction pointer saved for an interrupt points to the
next instruction to be executed at the instruction boundary where the processor took
the interrupt. If the instruction just executed has a repeat prefix, the interrupt is
taken at the end of the current iteration with the registers set to execute the next
iteration.
The ability of a P6 family processor to speculatively execute instructions does not
affect the taking of interrupts by the processor. Interrupts are taken at instruction
boundaries located during the retirement phase of instruction execution; so they are
always taken in the “in-order” instruction stream. See
Chapter 2, “Intel® 64 and IA-
32 Architectures,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, for more information about the P6 family processors’ microarchi-
tecture and its support for out-of-order instruction execution.
Note that the Pentium processor and earlier IA-32 processors also perform varying
amounts of prefetching and preliminary decoding. With these processors as well,
exceptions and interrupts are not signaled until actual “in-order” execution of the
instructions. For a given code sample, the signaling of exceptions occurs uniformly
when the code is executed on any family of IA-32 processors (except where new
exceptions or new opcodes have been defined).
6.7 NONMASKABLE INTERRUPT (NMI)
The nonmaskable interrupt (NMI) can be generated in either of two ways:
• External hardware asserts the NMI pin.
• The processor receives a message on the system bus (Pentium 4, Intel Core Duo,
Intel Core 2, Intel Atom, and Intel Xeon processors) or the APIC serial bus (P6
family and Pentium processors) with a delivery mode NMI.
When the processor receives a NMI from either of these sources, the processor
handles it immediately by calling the NMI handler pointed to by interrupt vector
number 2. The processor also invokes certain hardware conditions to insure that no
other interrupts, including NMI interrupts, are received until the NMI handler has
completed executing (see
Section 6.7.1, “Handling Multiple NMIs”).
Also, when an NMI is received from either of the above sources, it cannot be masked
by the IF flag in the EFLAGS register.