User's Manual

6-10 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
is an interrupt. As with the INT n instruction (see Section 6.4.2, “Software-Generated
Exceptions”), when an interrupt is generated through the INTR pin to an exception
vector, the processor does not push an error code on the stack, so the exception
handler may not operate correctly.
The IF flag can be set or cleared with the STI (set interrupt-enable flag) and CLI
(clear interrupt-enable flag) instructions, respectively. These instructions may be
executed only if the CPL is equal to or less than the IOPL. A general-protection excep
-
tion (#GP) is generated if they are executed when the CPL is greater than the IOPL.
(The effect of the IOPL on these instructions is modified slightly when the virtual
mode extension is enabled by setting the VME flag in control register CR4: see
Section 17.3, “Interrupt and Exception Handling in Virtual-8086 Mode.” Behavior is
also impacted by the PVI flag: see Section 17.4, “Protected-Mode Virtual Interrupts.”
The IF flag is also affected by the following operations:
• The PUSHF instruction stores all flags on the stack, where they can be examined
and modified. The POPF instruction can be used to load the modified flags back
into the EFLAGS register.
• Task switches and the POPF and IRET instructions load the EFLAGS register;
therefore, they can be used to modify the setting of the IF flag.
• When an interrupt is handled through an interrupt gate, the IF flag is automati-
cally cleared, which disables maskable hardware interrupts. (If an interrupt is
handled through a trap gate, the IF flag is not cleared.)
See the descriptions of the CLI, STI, PUSHF, POPF, and IRET instructions in Chapter
3, “Instruction Set Reference, A-M,” in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2A, for a detailed description of the operations
these instructions are allowed to perform on the IF flag.
6.8.2 Masking Instruction Breakpoints
The RF (resume) flag in the EFLAGS register controls the response of the processor
to instruction-breakpoint conditions (see the description of the RF flag in
Section 2.3,
“System Flags and Fields in the EFLAGS Register”).
When set, it prevents an instruction breakpoint from generating a debug exception
(#DB); when clear, instruction breakpoints will generate debug exceptions. The
primary function of the RF flag is to prevent the processor from going into a debug
exception loop on an instruction-breakpoint. See
Section 16.3.1.1, “Instruction-
Breakpoint Exception Condition,” for more information on the use of this flag.