User's Manual

Vol. 3 8-13
MULTIPLE-PROCESSOR MANAGEMENT
8.2.3.3 Stores Are Not Reordered With Earlier Loads
The Intel-64 memory-ordering model ensures that a store by a processor may not
occur before a previous load by the same processor. This is illustrated by the
following example:
Assume r1 == 1.
• Because r1 == 1, processor 1’s store to x occurs before processor 0’s load from
x.
• Because the Intel-64 memory-ordering model prevents each store from being
reordered with the earlier load by the same processor, processor 1’s load from y
occurs before its store to x.
• Similarly, processor 0’s load from x occurs before its store to y.
• Thus, processor 1’s load from y occurs before processor 0’s store to y, implying
r2 == 0.
8.2.3.4 Loads May Be Reordered with Earlier Stores to Different
Locations
The Intel-64 memory-ordering model allows a load to be reordered with an earlier
store to a different location. However, loads are not reordered with stores to the
same location.
The fact that a load may be reordered with an earlier store to a different location is
illustrated by the following example:
At each processor, the load and the store are to different locations and hence may be
reordered. Any interleaving of the operations is thus allowed. One such interleaving
Example 8-2. Stores Are Not Reordered with Older Loads
Processor 0 Processor 1
mov r1, [ _x] mov r2, [ _y]
mov [ _y], 1 mov [ _x], 1
Initially x == y == 0
r1 == 1 and r2 == 1 is not allowed
Example 8-3. Loads May be Reordered with Older Stores
Processor 0 Processor 1
mov [ _x], 1 mov [ _y], 1
mov r1, [ _y] mov r2, [ _x]
Initially x == y == 0
r1 == 0 and r2 == 0 is allowed