User's Manual

Vol. 3 8-41
MULTIPLE-PROCESSOR MANAGEMENT
gives software a consistent view of memory, independent of the processor on which
it is running. See Section 11.11, “Memory Type Range Registers (MTRRs),” for infor-
mation on setting up MTRRs.
8.7.4 Page Attribute Table (PAT)
Each logical processor has its own PAT MSR (IA32_PAT). However, as described in
Section 11.12, “Page Attribute Table (PAT),” the PAT MSR settings must be the same
for all processors in a system, including the logical processors.
8.7.5 Machine Check Architecture
In the Intel HT Technology context as implemented by processors based on Intel
NetBurst microarchitecture, all of the machine check architecture (MCA) MSRs
(except for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs) are duplicated for
each logical processor. This permits logical processors to initialize, configure, query,
and handle machine-check exceptions simultaneously within the same physical
processor. The design is compatible with machine check exception handlers that
follow the guidelines given in
Chapter 15, “Machine-Check Architecture.”
The IA32_MCG_STATUS MSR is duplicated for each logical processor so that its
machine check in progress bit field (MCIP) can be used to detect recursion on the
part of MCA handlers. In addition, the MSR allows each logical processor to deter
-
mine that a machine-check exception is in progress independent of the actions of
another logical processor in the same physical package.
Because the logical processors within a physical package are tightly coupled with
respect to shared hardware resources, both logical processors are notified of
machine check errors that occur within a given physical processor. If machine-check
exceptions are enabled when a fatal error is reported, all the logical processors within
a physical package are dispatched to the machine-check exception handler. If
machine-check exceptions are disabled, the logical processors enter the shutdown
state and assert the IERR# signal.
When enabling machine-check exceptions, the MCE flag in control register CR4
should be set for each logical processor.
On Intel Atom family processors that support Intel Hyper-Threading Technology, the
MCA facilities are shared between all logical processors on the same processor core.
8.7.6 Debug Registers and Extensions
Each logical processor has its own set of debug registers (DR0, DR1, DR2, DR3, DR6,
DR7) and its own debug control MSR. These can be set to control and record debug
information for each logical processor independently. Each logical processor also has
its own last branch records (LBR) stack.