User's Manual

Vol. 3 8-45
MULTIPLE-PROCESSOR MANAGEMENT
disabled on a logical processor basis. Typically, if software controlled clock modula-
tion is going to be used, the feature must be enabled for all the logical processors
within a physical processor and the modulation duty cycle must be set to the same
value for each logical processor. If the duty cycle values differ between the logical
processors, the processor clock will be modulated at the highest duty cycle selected.
8.7.13.4 External Signal Compatibility
This section describes the constraints on external signals received through the pins
of a processor supporting Intel Hyper-Threading Technology and how these signals
are shared between its logical processors.
• STPCLK# — A single STPCLK# pin is provided on the physical package of the
Intel Xeon processor MP. External control logic uses this pin for power
management within the system. When the STPCLK# signal is asserted, the
processor core transitions to the stop-grant state, where instruction execution is
halted but the processor core continues to respond to snoop transactions.
Regardless of whether the logical processors are active or halted when the
STPCLK# signal is asserted, execution is stopped on both logical processors and
neither will respond to interrupts.
In MP systems, the STPCLK# pins on all physical processors are generally tied
together. As a result this signal affects all the logical processors within the system
simultaneously.
• LINT0 and LINT1 pins — A processor supporting Intel Hyper-Threading
Technology has only one set of LINT0 and LINT1 pins, which are shared between
the logical processors. When one of these pins is asserted, both logical
processors respond unless the pin has been masked in the APIC local vector
tables for one or both of the logical processors.
Typically in MP systems, the LINT0 and LINT1 pins are not used to deliver
interrupts to the logical processors. Instead all interrupts are delivered to the
local processors through the I/O APIC.
• A20M# pin — On an IA-32 processor, the A20M# pin is typically provided for
compatibility with the Intel 286 processor. Asserting this pin causes bit 20 of the
physical address to be masked (forced to zero) for all external bus memory
accesses. Processors supporting Intel Hyper-Threading Technology provide one
A20M# pin, which affects the operation of both logical processors within the
physical processor.
The functionality of A20M# is used primarily by older operating systems and not
used by modern operating systems. On newer Intel 64 processors, A20M# may
be absent.