User's Manual

Vol. 3 9-9
PROCESSOR MANAGEMENT AND INITIALIZATION
9.4 MODEL-SPECIFIC REGISTERS (MSRS)
Most IA-32 processors (starting from Pentium processors) and Intel 64 processors
contain a model-specific registers (MSRs). A given MSR may not be supported across
all families and models for Intel 64 and IA-32 processors. Some MSRs are designated
as architectural to simplify software programming; a feature introduced by an archi
-
tectural MSR is expected to be supported in future processors. Non-architectural
MSRs are not guaranteed to be supported or to have the same functions on future
processors.
MSRs that provide control for a number of hardware and software-related features,
include:
• Performance-monitoring counters (see Chapter 20, “Introduction to Virtual-
Machine Extensions”).
• Debug extensions (see Chapter 20, “Introduction to Virtual-Machine Exten-
sions.”).
• Machine-check exception capability and its accompanying machine-check archi-
tecture (see Chapter 15, “Machine-Check Architecture”).
• MTRRs (see Section 11.11, “Memory Type Range Registers (MTRRs)”).
• Thermal and power management.
• Instruction-specific support (for example: SYSENTER, SYSEXIT, SWAPGS, etc.).
• Processor feature/mode support (for example: IA32_EFER,
IA32_FEATURE_CONTROL).
The MSRs can be read and written to using the RDMSR and WRMSR instructions,
respectively.
When performing software initialization of an IA-32 or Intel 64 processor, many of
the MSRs will need to be initialized to set up things like performance-monitoring
events, run-time machine checks, and memory types for physical memory.
Lists of available performance-monitoring events are given in Appendix A, “Perfor-
mance Monitoring Events”, and lists of available MSRs are given in Appendix B,
“Model-Specific Registers (MSRs)” The references earlier in this section show where
the functions of the various groups of MSRs are described in this manual.
9.5 MEMORY TYPE RANGE REGISTERS (MTRRS)
Memory type range registers (MTRRs) were introduced into the IA-32 architecture
with the Pentium Pro processor. They allow the type of caching (or no caching) to be
specified in system memory for selected physical address ranges. They allow
memory accesses to be optimized for various types of memory such as RAM, ROM,
frame buffer memory, and memory-mapped I/O devices.
In general, initializing the MTRRs is normally handled by the software initialization
code or BIOS and is not an operating system or executive function. At the very least,