User's Manual

10-54 Vol. 3

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

priorities of the local APICs by resetting Arb ID register of each agent to its current

APIC ID value. (The Pentium 4 and Intel Xeon processors do not implement the Arb

ID register.)

Section 10.11, “APIC Bus Message Passing Mechanism and Protocol (P6 Family,

Pentium Processors),” describes the APIC bus arbitration protocols and bus message

formats, while Section 10.7.1, “Interrupt Command Register (ICR),” describes the

INIT level de-assert IPI message.

Note that except for the SIPI IPI (see Section 10.7.1, “Interrupt Command Register

(ICR)”), all bus messages that fail to be delivered to their specified destination or

destinations are automatically retried. Software should avoid situations in which IPIs

are sent to disabled or nonexistent local APICs, causing the messages to be resent

repeatedly.

10.9 HANDLING INTERRUPTS

When a local APIC receives an interrupt from a local source, an interrupt message

from an I/O APIC, or and IPI, the manner in which it handles the message depends

on processor implementation, as described in the following sections.

10.9.1 Interrupt Handling with the Pentium 4 and Intel Xeon

Processors

With the Pentium 4 and Intel Xeon processors, the local APIC handles the local inter-

rupts, interrupt messages, and IPIs it receives as follows:

1. It determines if it is the specified destination or not (see Figure 10-24). If it is the

specified destination, it accepts the message; if it is not, it discards the message.

2. If the local APIC determines that it is the designated destination for the interrupt

and if the interrupt request is an NMI, SMI, INIT, ExtINT, or SIPI, the interrupt is

sent directly to the processor core for handling.

Figure 10-24. Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and

Intel Xeon Processors)

Wait to Receive

Bus Message

Belong to

Destination?

Discard

Message

Yes