User's Manual

Vol. 3 10-55

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

3. If the local APIC determines that it is the designated destination for the interrupt

but the interrupt request is not one of the interrupts given in step 2, the local

APIC sets the appropriate bit in the IRR.

4. When interrupts are pending in the IRR and ISR register, the local APIC

dispatches them to the processor one at a time, based on their priority and the

current task and processor priorities in the TPR and PPR (see

Section 10.9.3.1,

“Task and Processor Priorities”).

5. When a fixed interrupt has been dispatched to the processor core for handling,

the completion of the handler routine is indicated with an instruction in the

instruction handler code that writes to the end-of-interrupt (EOI) register in the

local APIC (see

Section 10.9.5, “Signaling Interrupt Servicing Completion”). The

act of writing to the EOI register causes the local APIC to delete the interrupt

from its ISR queue and (for level-triggered interrupts) send a message on the

bus indicating that the interrupt handling has been completed. (A write to the EOI

ExtINT, or SIPI.)

10.9.2 Interrupt Handling with the P6 Family and Pentium

Processors

With the P6 family and Pentium processors, the local APIC handles the local inter-

rupts, interrupt messages, and IPIs it receives as follows (see Figure 10-25).