User's Manual

11-8 Vol. 3
MEMORY CACHE CONTROL
(depending on the write policy currently in force) can also write it out to memory. If
the operand is to be written out to memory, it is written first into the store buffer, and
then written from the store buffer to memory when the system bus is available.
(Note that for the Pentium processor, write misses do not result in a cache line fill;
they always result in a write to memory. For this processor, only read misses result in
cache line fills.)
When operating in an MP system, IA-32 processors (beginning with the Intel486
processor) and Intel 64 processors have the ability to snoop other processor’s
accesses to system memory and to their internal caches. They use this snooping
ability to keep their internal caches consistent both with system memory and with
the caches in other processors on the bus. For example, in the Pentium and P6 family
processors, if through snooping one processor detects that another processor
intends to write to a memory location that it currently has cached in shared state,
the snooping processor will invalidate its cache line forcing it to perform a cache line
fill the next time it accesses the same memory location.
Beginning with the P6 family processors, if a processor detects (through snooping)
that another processor is trying to access a memory location that it has modified in
its cache, but has not yet written back to system memory, the snooping processor
will signal the other processor (by means of the HITM# signal) that the cache line is
held in modified state and will preform an implicit write-back of the modified data.
The implicit write-back is transferred directly to the initial requesting processor and
snooped by the memory controller to assure that system memory has been updated.
Here, the processor with the valid data may pass the data to the other processors
without actually writing it to system memory; however, it is the responsibility of the
memory controller to snoop this operation and update memory.
11.3 METHODS OF CACHING AVAILABLE
The processor allows any area of system memory to be cached in the L1, L2, and L3
caches. In individual pages or regions of system memory, it allows the type of
caching (also called memory type) to be specified (see
Section 11.5). Memory types
currently defined for the Intel 64 and IA-32 architectures are (see Table 11-2):
• Strong Uncacheable (UC) —System memory locations are not cached. All
reads and writes appear on the system bus and are executed in program order
without reordering. No speculative memory accesses, page-table walks, or
prefetches of speculated branch targets are made. This type of cache-control is
useful for memory-mapped I/O devices. When used with normal RAM, it greatly
reduces processor performance.
NOTE
The behavior of FP and SSE/SSE2 operations on operands in UC
memory is implementation dependent. In some implementations,
accesses to UC memory may occur more than once. To ensure
predictable behavior, use loads and stores of general purpose