User's Manual

Vol. 3 11-25
MEMORY CACHE CONTROL
11.5.4 Disabling and Enabling the L3 Cache
On processors based on Intel NetBurst microarchitecture, the third-level cache can
be disabled by bit 6 of the IA32_MISC_ENABLE MSR. The third-level cache disable
flag (bit 6 of the IA32_MISC_ENABLE MSR) allows the L3 cache to be disabled and
enabled, independently of the L1 and L2 caches. Prior to using this control to disable
or enable the L3 cache, software should disable and flush all the processor caches, as
described earlier in
Section 11.5.3, “Preventing Caching,” to prevent of loss of infor-
mation stored in the L3 cache. After the L3 cache has been disabled or enabled,
caching for the whole processor can be restored.
Newer Intel 64 processor with L3 do not support IA32_MISC_ENABLES[bit 6], the
procedure described in Section 11.5.3, “Preventing Caching,” apply to the entire
cache hierarchy.
11.5.5 Cache Management Instructions
The Intel 64 and IA-32 architectures provide several instructions for managing the
L1, L2, and L3 caches. The INVD, WBINVD, and WBINVD instructions are system
instructions that operate on the L1, L2, and L3 caches as a whole. The PREFETCHh
and CLFLUSH instructions and the non-temporal move instructions (MOVNTI,
MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD), which were introduced in
SSE/SSE2 extensions, offer more granular control over caching.
The INVD and WBINVD instructions are used to invalidate the contents of the L1, L2,
and L3 caches. The INVD instruction invalidates all internal cache entries, then
generates a special-function bus cycle that indicates that external caches also should
be invalidated. The INVD instruction should be used with care. It does not force a
write-back of modified cache lines; therefore, data stored in the caches and not
written back to system memory will be lost. Unless there is a specific requirement or
benefit to invalidating the caches without writing back the modified lines (such as,
during testing or fault recovery where cache coherency with main memory is not a
concern), software should use the WBINVD instruction.
The WBINVD instruction first writes back any modified lines in all the internal caches,
then invalidates the contents of both the L1, L2, and L3 caches. It ensures that cache
coherency with main memory is maintained regardless of the write policy in effect
(that is, write-through or write-back). Following this operation, the WBINVD instruc
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tion generates one (P6 family processors) or two (Pentium and Intel486 processors)
special-function bus cycles to indicate to external cache controllers that write-back of
modified data followed by invalidation of external caches should occur. The amount of
time or cycles for WBINVD to complete will vary due to the size of different cache
hierarchies and other factors. As a consequence, the use of the WBINVD instruction
can have an impact on interrupt/event response time.
The PREFETCHh instructions allow a program to suggest to the processor that a
cache line from a specified location in system memory be prefetched into the cache
hierarchy (see
Section 11.8, “Explicit Caching”).