Manualshelf

User's Manual

ManualsBrandsIntel ManualsWebcamIntel Intel Webcam 253668-032US
591592593594595596597598599600
13-18 Vol. 3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR
instructions, and provides a more constrained list of features than using all 1's in the
save mask.
The advantage of using a mask value of all-bits-set-to-1 for XSAVE/XRSTOR is that it
can simplify system software’s support for processor extended state management,
when multiple generations of hardware may support different number of processor
extended states as reported by CPUID. However, there may be additional implemen
-
tation requirement of software modification that may arise due to a particular system
software or specific details introduced by a new processor extended state.
13.8.1 Application Programming Model and Processor Extended
States
New instruction set extensions may be introduced over time and operating on a
processor extended state that must be enabled in the XFEATURE_ENABLED_MASK
register (XCR0). The general application programming model for using such instruc
-
tion set extensions are:
• Check if OS has enabled processor extended state management. If
CPUID.01H:ECX.OSXSAVE is 1, the OS has enabled the
XSAVE/XRSTOR/XSETBV/XGETBV instructions and the
XFEATURE_ENABLED_MASK register, and it has indicated support for the
processor extended state management.
Applications do not need to check the value of CPUID.01H:ECX.XSAVE because
“CPUID.01H:ECX.OSXSAVE = 1” implies OS has successfully verified
CPUID.01H:ECX.XSAVE = 1. CPUID.01H:ECX.OSXSAVE reflects the value of
CR4.OSXSAVE, and this bit cannot be set to 1 unless CPUID.01H:ECX.XSAVE = 1.
• Check whether the processor extended state component associated with a given
instruction set extension is enabled by the OS. The bits of EDX:EAX returned by
XGETBV as 1 indicate which processor extended state components have been
enabled by OS. Note, the CR4.OSFXSR is not used by OS to enable instruction
extensions requiring processor extended state support.
• Check the target instruction set extension is supported in the processor. Each
new instruction set extension is expected to provide a feature flag in CPUID when
it is introduced.