User's Manual

Vol. 3 16-5
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
exceptions, debug handlers should clear the register before returning to the inter-
rupted task.
16.2.4 Debug Control Register (DR7)
The debug control register (DR7) enables or disables breakpoints and sets break-
point conditions (see Figure 16-1). The flags and fields in this register control the
following things:
• L0 through L3 (local breakpoint enable) flags (bits 0, 2, 4, and 6) —
Enables (when set) the breakpoint condition for the associated breakpoint for the
current task. When a breakpoint condition is detected and its associated Ln flag
is set, a debug exception is generated. The processor automatically clears these
flags on every task switch to avoid unwanted breakpoint conditions in the new
task.
• G0 through G3 (global breakpoint enable) flags (bits 1, 3, 5, and 7) —
Enables (when set) the breakpoint condition for the associated breakpoint for all
tasks. When a breakpoint condition is detected and its associated Gn flag is set,
a debug exception is generated. The processor does not clear these flags on a
task switch, allowing a breakpoint to be enabled for all tasks.
• LE and GE (local and global exact breakpoint enable) flags (bits 8, 9) —
This feature is not supported in the P6 family processors, later IA-32 processors,
and Intel 64 processors. When set, these flags cause the processor to detect the
exact instruction that caused a data breakpoint condition. For backward and
forward compatibility with other Intel processors, we recommend that the LE and
GE flags be set to 1 if exact breakpoints are required.
• GD (general detect enable) flag (bit 13) — Enables (when set) debug-
register protection, which causes a debug exception to be generated prior to any
MOV instruction that accesses a debug register. When such a condition is
detected, the BD flag in debug status register DR6 is set prior to generating the
exception. This condition is provided to support in-circuit emulators.
When the emulator needs to access the debug registers, emulator software can
set the GD flag to prevent interference from the program currently executing on
the processor.
The processor clears the GD flag upon entering to the debug exception handler,
to allow the handler access to the debug registers.
• R/W0 through R/W3 (read/write) fields (bits 16, 17, 20, 21, 24, 25, 28,
and 29) — Specifies the breakpoint condition for the corresponding breakpoint.
The DE (debug extensions) flag in control register CR4 determines how the bits in
the R/Wn fields are interpreted. When the DE flag is set, the processor interprets
bits as follows:
00 — Break on instruction execution only.
01 — Break on data writes only.