User's Manual

19-4 Vol. 3
ARCHITECTURE COMPATIBILITY
control and status register. These instructions and registers are designed to allow
SIMD computations to be made on single-precision floating-point numbers. Several
of these new instructions also operate in the MMX registers. SSE instructions and
registers are described in
Section 10, “Programming with Streaming SIMD Exten-
sions (SSE),” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, and in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volumes 2A & 2B.
19.7 STREAMING SIMD EXTENSIONS 2 (SSE2)
The Streaming SIMD Extensions 2 (SSE2) were introduced in the Pentium 4 and Intel
Xeon processors. They consist of a new set of instructions that operate on the XMM
and MXCSR registers and perform SIMD operations on double-precision floating-
point values and on integer values. Several of these new instructions also operate in
the MMX registers. SSE2 instructions and registers are described in
Chapter 11,
“Programming with Streaming SIMD Extensions 2 (SSE2),” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, and in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B.
19.8 STREAMING SIMD EXTENSIONS 3 (SSE3)
The Streaming SIMD Extensions 3 (SSE3) were introduced in Pentium 4 processors
supporting Intel Hyper-Threading Technology and Intel Xeon processors. SSE3
extensions include 13 instructions. Ten of these 13 instructions support the single
instruction multiple data (SIMD) execution model used with SSE/SSE2 extensions.
One SSE3 instruction accelerates x87 style programming for conversion to integer.
The remaining two instructions (MONITOR and MWAIT) accelerate synchronization
of threads. SSE3 instructions are described in
Chapter 12, “Programming with SSE3,
SSSE3 and SSE4,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1, and in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volumes 2A & 2B.
19.9 ADDITIONAL STREAMING SIMD EXTENSIONS
The Supplemental Streaming SIMD Extensions 3 (SSSE3) were introduced in the
Intel Core 2 processor and Intel Xeon processor 5100 series. Streaming SIMD Exten
-
sions 4 provided 54 new instructions introduced in 45nm Intel Xeon processors and
Intel Core 2 processors. SSSE3, SSE4.1 and SSE4.2 instructions are described in
Chapter 12, “Programming with SSE3, SSSE3 and SSE4,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, and in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B.