User's Manual

Vol. 3 2-25

SYSTEM ARCHITECTURE OVERVIEW

processor will generate an invalid opcode exception (#UD) if it attempts to

execute any SSE/SSE2/SSE3and instruction, with the exception of PAUSE,

PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and

POPCNT. The operating system or executive must explicitly set this flag.

NOTE

CPUID feature flags FXSR indicates availability of the

FXSAVE/FXRSTOR instructions. The OSFXSR bit provides operating

system software with a means of enabling FXSAVE/FXRSTOR to

save/restore the contents of the X87 FPU, XMM and MXCSR registers.

Consequently OSFXSR bit indicates that the operating system

provides context switch support for SSE/SSE2/SSE3/SSSE3/SSE4.

OSXMMEXCPT

Operating System Support for Unmasked SIMD Floating-Point Excep-

tions (bit 10 of CR4) — When set, indicates that the operating system

supports the handling of unmasked SIMD floating-point exceptions through

an exception handler that is invoked when a SIMD floating-point exception

(#XF) is generated. SIMD floating-point exceptions are only generated by

SSE/SSE2/SSE3/SSE4.1 SIMD floating-point instructions.

The operating system or executive must explicitly set this flag. If this flag is

not set, the processor will generate an invalid opcode exception (#UD)

whenever it detects an unmasked SIMD floating-point exception.

VMXE

VMX-Enable Bit (bit 13 of CR4) — Enables VMX operation when set. See

Chapter 20, “Introduction to Virtual-Machine Extensions.”

SMXE

SMX-Enable Bit (bit 14 of CR4) — Enables SMX operation when set. See

Chapter 6, “Safer Mode Extensions Reference” of Intel® 64 and IA-32 Archi-

tectures Software Developer’s Manual, Volume 2B.

OSXSAVE

XSAVE and Processor Extended States-Enable Bit (bit 18 of CR4) —

When set, this flag: (1) indicates (via CPUID.01H:ECX.OSXSAVE[bit 27])

that the operating system supports the use of the XGETBV, XSAVE and

XRSTOR instructions by general software; (2) enables the XSAVE and

XRSTOR instructions to save and restore the x87 FPU state (including MMX

registers), the SSE state (XMM registers and MXCSR), along with other

processor extended states enabled in the XFEATURE_ENABLED_MASK

instructions in order to read and write XCR0. See

Section 2.6 and Chapter

13, “System Programming for Instruction Set Extensions and Processor

Extended States”.

TPL Task Priority Level (bit 3:0 of CR8) — This sets the threshold value corre-

sponding to the highest-priority interrupt to be blocked. A value of 0 means