Datasheet

Register Description
38 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
defined and is implementation dependent. This does not result in all of the power
savings of a reduced number of core product, but does save more power than even the
deepest sleep state.
.
2.6.2 MIRROR_PORT_CTL
Mirror Port control register.
.
Device: 0
Function: 0
Offset: 80h
Access as a Dword
Bit Type
Reset
Value
Description
16 RW1S 0 LOCK. Once written to 1, changes to this register cannot be made.
8RWL0MT_DISABLE. Disables multi-threading (2 logical threads per core) in all
cores if set to 1.
2:0 RWL 0 CORE_COUNT.
000 - max number (default value)
001 - 1 core
010 - 2 cores
011 - 3 cores
100 - 4 cores
101 - 5 cores
Device: 0
Function: 0
Offset: D0h
Access as a Dword
Bit Type
Reset
Value
Description
10:7 - - RESERVED
6RW0DSBL_ENH_MPRX_SYNC. When set, it disables the enhancing
synchronization scheme for the MiP_Rx.
5RW0MIP_GO_10. When set, the Mip_Tx and Mip_Rx go to L0 directly from
Config_FlitLock.
4RW0MIP_RX_CRC_SQUASH. When set, replaces CRC errors with CRC special
packet on MiP Rx.
3RW0MIP_RX_PORT_SEL. Port select for MiP Rx. _PORT_SEL0=QPI Port 0.
_PORT_SEL1=QPI Port 1.
2RW0MIP_TX_PORT_SEL. Port select for MiP Tx. _PORT_SEL0=QPI Port 0.
_PORT_SEL1=QPI Port 1.
1RW1MIP_RX_ENABLE. Enables the Rx portion of the mirror port.
0RW1MIP_TX_ENABLE. Enables the Tx portion of the mirror port.