Datasheet

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2 39
Register Description
2.7 SAD - System Address Decoder Registers
2.7.1 SAD_MCSEG_BASE
Global register for MCSEG address space. These are designed to look just like the cores
SMRR type registers.
2.7.2 SAD_MCSEG_MASK
Global register for MCSEG address space. These are designed to look just like the cores
SMRR type registers.
2.7.3 SAD_MESEG_BASE
Register for ME stolen range address space. They are designed to look like the core
SMRR type registers.
Device: 0
Function: 1
Offset: 60h
Access as a Qword
Bit Type
Reset
Value
Description
63:40 RSVD.
39:19 RW 0 BASE_ADDRESS. Specifies the base address of the MCSEG. Must be aligned
on 512KB or greater boundary.
18:0 RSVD.
Device: 0
Function: 1
Offset: 68h
Access as a Qword
Bit Type
Reset
Value
Description
63:40 RSVD.
39:19 RW 0 MASK. Specifies the mask value for the MCSEG. For initial implementations this
must be a 2MB mask value = 0000_00FF_FFE0_0000 = (1FFFFCh << 19).
18:12 RSVD.
11 RW 0 ENABLE. When set to 1 all chipset accesses to this range are aborted and
generate a Machine Check.
10 RW 0 LOCK. When set to 1 prevents modifications to the next SAD_MCSEG_BASE
and SAD_MCSEG_MASK registers until the next reset.
9:0 RSVD.