Datasheet

4 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.11.6 MC_CHANNEL_0_SCHEDULER_PARAMS
MC_CHANNEL_1_SCHEDULER_PARAMS
MC_CHANNEL_2_SCHEDULER_PARAMS....................................................52
2.11.7 MC_CHANNEL_0_PAGETABLE_PARAMS2
MC_CHANNEL_1_PAGETABLE_PARAMS2
MC_CHANNEL_2_PAGETABLE_PARAMS2...................................................52
2.12 Memory Thermal Control ....................................................................................53
2.12.1 MC_THERMAL_STATUS0
MC_THERMAL_STATUS1
MC_THERMAL_STATUS2.........................................................................53
2.12.2 MC_DDR_THERM0_COMMAND0
MC_DDR_THERM0_COMMAND1
MC_DDR_THERM0_COMMAND2...............................................................53
2.12.3 MC_DDR_THERM1_COMMAND0
MC_DDR_THERM1_COMMAND1
MC_DDR_THERM1_COMMAND2...............................................................54
2.12.4 MC_DDR_THERM0_STATUS0
MC_DDR_THERM0_STATUS1
MC_DDR_THERM0_STATUS2 ..................................................................54
2.12.5 MC_DDR_THERM1_STATUS0
MC_DDR_THERM1_STATUS1
MC_DDR_THERM1_STATUS2 ..................................................................55
3 Functional Description .............................................................................................57
3.1 Integrated Memory Controller..............................................................................57
3.2 Supported RDIMM Memory Configurations.............................................................58
3.2.1 RDIMM 1.5 V Configurations ...................................................................58
3.2.2 RDIMM 1.35 V Configurations .................................................................59
3.3 Supported UDIMM Memory Configurations.............................................................59
3.3.1 UDIMM 1.5V Configurations....................................................................59
3.3.2 UDIMM 1.35V Configurations ..................................................................61
3.4 Channel Population Requirements for Memory RAS Modes.......................................61
3.5 Memory Error Signaling ......................................................................................62
3.5.1 Enabling SMI/NMI for Memory Corrected Errors.........................................62
3.5.2 Identifying the Cause of an Interrupt.......................................................62
3.6 DDR_THERM# and DDR_THERM2# Pin Response...................................................62
3.7 2X Refresh........................................................................................................63
3.8 Pre-charge Power-Down Slow Exit........................................................................63