Datasheet

Register Description
40 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.7.4 SAD_MESEG_MASK
Register for ME stolen range address space. They are designed to look just like the core
SMRR type registers.
2.8 Intel QPI Link Registers
2.8.1 QPI_DEF_RMT_VN_CREDITS_L0
QPI_DEF_RMT_VN_CREDITS_L1
This is the control register that houses the default values of available remote credits to
be transmitted to the remote agent for the remote Tx use.
Device: 0
Function: 1
Offset: 70h
Access as a Qword
Bit Type
Reset
Value
Description
63:40 RSVD.
39:19 RW 0 BASE_ADDRESS. Specifies the base address of the MESEG. Must be aligned
on 512KB or greater boundary.
18:0 RSVD.
Device: 0
Function: 1
Offset: 78h
Access as a Qword
Bit Type
Reset
Value
Description
63:40 RSVD.
39:19 RW 0 MASK. Mask of MESEG. Space must be poewr of 2 aligned. Which bits must
match the BASE in order. to be inside the ME range.
11 RW 0 ENABLE. Indicates if ME stolen range is enabled (when enabled all core
accesses to this range are aborted).
10 RW 0 LOCK. Indicates if ME stolen range base/mask is locked.
11 RW 0 ENABLE. When set to 1 all chipset accesses to this range are aborted and
generate a Machine Check.
10 RW 0 LOCK. When set to 1 prevents modifications to the next SAD_MCSEG_BASE
and SAD_MCSEG_MASK registers until the next reset.
9:0 RSVD.
Device: 2
Function: 0, 4
Offset: 58h
Access as a Dword
Bit Type
Reset
Value
Description
18:12 RW 100 VNA. VNA Credits.
11:10 RW 1 NCS. NCS Channel VN0 Credits.