Datasheet

Register Description
42 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.8.4 MIP_PH_PRT_L0
MIP_PH_PRT_L1
Mirror Port periodic retraining timing register.
2.9 Integrated Memory Controller Control Registers
The registers in this section apply only to processors supporting registered DIMMs
Device: 2
Function: 2,3
Offset: 6Ch
Access as a Dword
Bit Type
Reset
Value
Description
31 RW 0 RETRAIN_NOW. This bit generates a retraining event with the provided
retraining parameters when enabled only during at-speed operation
.
27 RW 0 LA_LOAD_DISABLE. Disables the loading of the effective values of the
Intel® QuickPath CSRs when set.
23 RW 0 ENABLE_PRBS. Enables LFSR pattern during bitlock/training.
22 RW 0 ENABLE_SCRAMBLE. Enables data scrambling through LFSR.
14 RW 1 DETERMINISM_MODE. Sets determinism mode of operation.
13 RW 1 DISABLE_AUTO_COMP. Disables automatic entry into compliance.
12 RW 0 INIT_FREEZE. When set, freezes the FSM when initialization aborts.
10:8 RW 0 INIT_MODE. Initialization mode that determines altered initialization
modes.
7RW0LINK_SPEED. Identifies slow speed or at-speed operation for the Intel QPI
port.
5RW1PHYINITBEGIN. Instructs the port to start initialization.
4RW0SINGLE_STEP. Enables single step mode.
3RW0LAT_FIX_CTL. If set, instructs the remote agent to fix the latency.
2RW0BYPASS_CALIBRATION. Indicates the physical layer to bypass calibration.
1RW0RESET_MODIFIER. Modifies soft reset to default reset when set.
0RW1S0PHY_RESET. Physical Layer Reset. Note while this register is locked after
going to FAST speed L0, this bit is not locked.
Device: 2
Function: 2,3
Offset: A4h
Access as a Dword
Bit Type
Reset
Value
Description
21:16 RW 29 RETRAIN_PKT_CNT. Retraining packet count.
13:10 RW 11 EXP_RETRAIN_INTERVAL. Exponential count for retraining interval.
7:0 RW 3 RETRAIN_INTERVAL. Periodic retraining interval. A value of 0 indicates
retraining is disabled.