Datasheet

Intel

Xeon

Processor 5600 Series Datasheet Volume 2 43

2.9.1 MC_SMI_DIMM_ERROR_STATUS

SMI DIMM error threshold overflow status register. This bit is set when the per-DIMM

error counter exceeds the specified threshold. The bit is reset by BIOS.

2.9.2 MC_SMI__CNTRL

System Management Interrupt control register.

Device: 3

Function: 0

Offset: 50h

Access as a Dword

Bit Type

Reset

Value

Description

13:12 RW0C 0 REDUNDANCY_LOSS_FAILING_DIMM. The ID for the failing DIMM when

redundancy is lost.

11:0 RW0C 0 DIMM_ERROR_OVERFLOW_STATUS. This 12-bit field is the per dimm error

overflow status bits. The organization is as follows:

If there are three or more DIMMS on the channel:

Bit 0 : Dimm 0 Channel 0

Bit 1 : Dimm 1 Channel 0

Bit 2 : Dimm 2 Channel 0

Bit 3 : Dimm 3 Channel 0

Bit 4 : Dimm 0 Channel 1

Bit 5 : Dimm 1 Channel 1

Bit 6 : Dimm 2 Channel 1

Bit 7 : Dimm 3 Channel 1

Bit 8 : Dimm 0 Channel 2

Bit 9 : Dimm 1 Channel 2

Bit 10 : Dimm 2 Channel 2

Bit 11 : Dimm 3 Channel 2

If there are one or two DIMMS on the channel:

Bit 0 : Dimm 0, Ranks 0 and 1, Channel 0

Bit 1 : Dimm 0, Ranks 2 and 3, Channel 0

Bit 2 : Dimm 1, Ranks 0 and 1, Channel 0

Bit 3 : Dimm 1, Ranks 2 and 3, Channel 0

Bit 4 : Dimm 0, Ranks 0 and 1, Channel 1

Bit 5 : Dimm 0, Ranks 2 and 3, Channel 1

Bit 6 : Dimm 1, Ranks 0 and 1, Channel 1

Bit 7 : Dimm 1, Ranks 2 and 3, Channel 1

Bit 8 : Dimm 0, Ranks 0 and 1, Channel 2

Bit 9 : Dimm 0, Ranks 2 and 3, Channel 2

Bit 10 : Dimm 1, Ranks 0 and 1, Channel 2

Bit 11 : Dimm 1, Ranks 2 and 3, Channel 2