Datasheet

Register Description
50 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
2.11.3 MC_CHANNEL_0_REFRESH_TIMING
MC_CHANNEL_1_REFRESH_TIMING
MC_CHANNEL_2_REFRESH_TIMING
This register contains parameters that specify the refresh timings. Units are in DCLK.
10:7 RW 0 tsrRdTWr. Minimum delay between Read followed by a write to the same rank.
0000: RSVD
0001: RSVD
0010: RSVD
0011: 5
0100: 6
0101: 7
0110: 8
0111: 9
1000: 10
1001: 11
1010: 12
1011: 13
1100: 14
1101: RSVD
1110: RSVD
1111: RSVD
6:4 RW 0 tddRdTRd. Minimum delay between reads to different DIMMs.
000: 2
001: 3
010: 4
011: 5
100: 6
101: 7
110: 8
111: 9
3:1 RW 0 tdrRdTRd. Minimum delay between reads to different ranks on the same
DIMM.
000: 2
001: 3
010: 4
011: 5
100: 6
101: 7
110: 8
111: 9
0RW0tsrRdTRd. Minimum delay between reads to the same rank.
0: 4
1: 6
Device: 4, 5, 6
Function: 0
Offset: 80h
Access as a Dword