Datasheet

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2 51
Register Description
2.11.4 MC_CHANNEL_0_CKE_TIMING
MC_CHANNEL_1_CKE_TIMING
MC_CHANNEL_2_CKE_TIMING
This register contains parameters that specify the CKE timings. All units are in DCLK.
2.11.5 MC_CHANNEL_0_CKE_TIMING_B
MC_CHANNEL_1_CKE_TIMING_B
MC_CHANNEL_2_CKE_TIMING_B
This register contains parameters that specify CKE timings.
Device: 4, 5, 6
Function: 0
Offset: 8Ch
Access as a Dword
Bit Type
Reset
Value
Description
29:19 RW 0 tTHROT_OPPREF. The minimum time between two opportunistic refreshes.
Should be set to tRFC in DCLKs. Zero is an invalid encoding. A value of 1 should
be programmed to disable the throttling of opportunistic refreshes. By setting this
field to tRFC, current to a single DIMM can be limited to that required to support
this scenario without significant performance impact:
- 8 panic refreshes in tREFI to one rank
- 1 opportunistic refresh every tRFC to another rank
- full bandwidth delivered by the third and fourth ranks
Platforms that can supply peak currents to the DIMMs should disable opportunistic
refresh throttling for maximum performance.
18:9 RW 0 tREFI_8. Average periodic refresh interval divided by 8.
8:0 RW 0 tRFC. Delay between the refresh command and an activate or refresh command.
Device: 4, 5, 6
Function: 0
Offset: 90h
Access as a Dword
Bit Type
Reset
Value
Description
21 RW 1 CsForCkeTransition. Specifies if CS is to be asserted when CKE transition with
PowerDown entry/exit and SelfRefresh exit.
20:11 RW 0 tXSDLL. Minimum delay between the exit of self refresh and commands that
require a locked DLL.
10:3 RW 0 tXS. Minimum delay between the exit of self refresh and commands not
requiring a DLL.
2:0 RW 0 tCKE. CKE minimum pulse width.