Datasheet

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2 53
Register Description
2.12 Memory Thermal Control
2.12.1 MC_THERMAL_STATUS0
MC_THERMAL_STATUS1
MC_THERMAL_STATUS2
Status registers for the thermal throttling logic for each channel.
2.12.2 MC_DDR_THERM0_COMMAND0
MC_DDR_THERM0_COMMAND1
MC_DDR_THERM0_COMMAND2
This register contains the command portion of the DDR_THERM# pin functionality (i.e.
what an assertion of the pin does).
Device: 4, 5, 6
Function: 0
Offset: DCh
Access as a Dword
Bit Type
Reset
Value
Description
27 RW 0 ENABLEADAPTIVEPAGECLOSE. When set, enables Adaptive Page Closing.
26:18 RW 0 MINPAGECLOSELIMIT. Upper 9 MSBs of a 13-bit threshold limit. When the
mistake counter falls below this threshold, a less aggressive page close interval
(larger) is selected.
17:9 RW 0 MAXPAGECLOSELIMIT. Upper 9 bits of a 13-bit threshold limit. When the
mistake counter exceeds this threshold, a more aggressive page close interval
(smaller) is selected.
8:0 RW 0 MISTAKECOUNTER. Upper 8 MSBs of a 12-bit counter. This counter adapts
the interval between assertions of the page close flag. For a less aggressive
page close, the length of the count interval is increased and vice versa for a
more aggressive page close policy.
Device: 4, 5, 6
Function: 3
Offset: 4Ch
Access as a Dword
Bit Type
Reset
Value
Description
29:4 RO 0 CYCLES_THROTTLED. The number of throttle cycles, in increments of 256
Dclks, triggered in any rank in the last SAFE_INTERVAL number of ZQs.
3:0 RO 0 RANK_TEMP. The bit[3:0] specifies whether the throttler[3:0] is above
throttling threshold
.
Device: 4, 5, 6
Function: 3
Offset: 9Ch
Access as a Dword
Bit Type
Reset
Value
Description
3RW0THROTTLE. Force throttling when DDR_THERM# pin is asserted.