Datasheet

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2 55
Register Description
2.12.5 MC_DDR_THERM1_STATUS0
MC_DDR_THERM1_STATUS1
MC_DDR_THERM1_STATUS2
This register contains the status portion of the DDR_THERM2# pin functionality (that is,
what is happening or has happened with respect to the pin).
§
Device: 4, 5, 6
Function: 3
Offset: A8h
Access as a Dword
Bit Type
Reset
Value
Description
2RO0ASSERTION. An assertion edge was seen on DDR_THERM#. Write-1-to-clear.
1RO0DEASSERTION. A de-assertion edge was seen on DDR_THERM#. Write-1-to-
clear.
0RO0STATE. Present logical state of DDR_THERM# bit. This is a static indication of
the pin, and may be several clocks out of date due to the delay between the pin
and the signal.
STATE = 0 means DDR_THERM# is deasserted
STATE = 1 means DDR_THERM# is asserted