Datasheet
Functional Description
62 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2
3.5 Memory Error Signaling
3.5.1 Enabling SMI/NMI for Memory Corrected Errors
The MC_SMI_CNTRL register has enables for SMI and NMI interrupts. Only one should
be set. Whichever type of interrupt is enabled will be triggered if:
• a DIMM error counter exceeds the threshold
• redundancy is lost on a mirrored configuration or
3.5.2 Identifying the Cause of an Interrupt
Table 3-6 defines how to determine the cause of an interrupt.
3.6 DDR_THERM# and DDR_THERM2# Pin Response
Two pins are available on the Intel Xeon processor 5600 series, DDR_THERM# and
DDR_THERM2#. One of the responses shown below can be configured to each pin.
Existing Intel Xeon 5500 platform implementations use DDR_THERM# for the Throttling
function, so DDR_THERM2# may be used for the 2X refresh function with Intel Xeon
processor 5600 series. Architecturally, there is no restriction on which pin is used to
control which function.
Table 3-6. Causes of SMI or NMI
Condition Cause
Recommended Platform Software
Response
MC_SMI_DIMM_ERROR_STATUS.
DIMM_ERROR_OVERFLOW_STATUS != 0
This register has one bit for each
DIMM error counter that exceeds
threshold.
This can happen at the same time
as any of the other SMI events
(redundancy lost in Mirror Mode).
It is recommended that software
address one, so that the other
cause remains when the second
event is taken.
Examine the associated
MC_COR_ECC_CNT_X register. Determine
the time since the counter has been cleared.
The counter should be cleared to reset the
overflow bit.
MC_RAS_STATUS.REDUNDANCY_LOSS = 1 One channel of a mirrored pair had
an uncorrectable error and
redundancy has been lost.
Raise an indication that a reboot should be
scheduled, possibly replace the failed DIMM
specified in the
MC_SMI_DIMM_ERROR_STATUS register.
Table 3-7. DDR_THERM# Responses
Register Parameter Bits One Per Description
MC_DDR_THERM_COMMANDX THROTTLE 1 Socket.
(appears in each
of the 3
channels)
While DDR_THERM# is asserted, Duty Cycle throttling
will be imposed on all channels. The platform should
ensure DDR_THERM# is asserted when any DIMM is
over T64.
MC_DDR_THERM_COMMANDX 2X refresh 1 Socket.
(appears in each
of the 3
channels)
Refresh rate is doubled on all channels while
DDR_THERM# is asserted. The platform should ensure
DDR_THERM# is asserted when any DIMM is over T32.