Datasheet

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Intel

Xeon

Processor 5600 Series Datasheet Volume 2 9

2 Register Description

The processor supports PCI configuration space accesses using the mechanism denoted

as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus

Specification, as well as the PCI Express enhanced configuration mechanism as

specified in the PCI Express Base Specification. All the registers are organized by bus,

device, function, etc. as defined in the PCI Express Base Specification. All processor

registers appear on the PCI bus assigned for the processor socket. Bus number is

derived by the max bus range setting and processor socket number. All multi-byte

numeric fields use “little-endian” ordering (that is, lower addresses contain the least

significant parts of the field).

2.1 Register Terminology

Registers and register bits are assigned one or more of the following attributes. These

attributes define the behavior of register and the bit(s) that are contained with in. All

bits are set to default values by hard reset. Sticky bits retain their states between hard

resets.

Term Description

RO Read Only. If a register bit is read only, the hardware sets its state. The bit may be read

by software. Writes to this bit have no effect.

WO Write Only. The register bit is not implemented as a bit. The write causes some hardware

event to take place.

RW Read/Write. A register bit with this attribute can be read and written by software.

RC Read Clear: The bit or bits can be read by software, but the act of reading causes the

value to be cleared.

RCW Read Clear/Write: A register bit with this attribute will get cleared after the read. The

RW1C Read/Write 1 Clear. A register bit with this attribute can be read or cleared by software.

In order to clear this bit, a one must be written to it. Writing a zero will have no effect.

RW0C Read/Write 0 Clear. A register bit with this attribute can be read or cleared by software.

In order to clear this bit, a zero must be written to it. Writing a one will have no effect.

RW1S Read/Write 1 Set: A register bit can be either read or set by software. In order to set

this bit, a one must be written to it. Writing a zero to this bit has no effect. Hardware will

clear this bit.

RW0S Read/Write 0 Set: A register bit can be either read or set by software. In order to set

this bit, a zero must be written to it. Writing a one to this bit has no effect. Hardware will

clear this bit.

RWL Read/Write/Lock. A register bit with this attribute can be read or written by software.

Hardware or a configuration bit can lock the bit and prevent it from being updated.

RWO Read/Write Once. A register bit with this attribute can be written to only once after

power up. After the first write, the bit becomes read only. This attribute is applied on a bit

by bit basis. For example, if the RWO attribute is applied to a 2 bit field, and only one bit

is written, then the written bit cannot be rewritten (unless reset). The unwritten bit, of the

field, may still be written once. This is special case of RWL.

RRW Read/Restricted Write. This bit can be read and written by software. However, only

supported values will be written. Writes of non supported values will have no effect.

L Lock. A register bit with this attribute becomes Read Only after a lock bit is set.

RSVD Reserved Bit. This bit is reserved for future expansion and must not be written. The PCI

Local Bus Specification, Revision 2.2 requires that reserved bits must be preserved. Any

software that modifies a register that contains a reserved bit is responsible for reading the