Intel® Celeron® Processor 200Δ Sequence Datasheet October 2007 Document Number: 318546-001
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Packaging Terminology ............................................................. 10 1.2 References ....................................................................................................... 11 2 Low Power Features ....
5.3 5.4 5.5 Processor Thermal Features ................................................................................63 Intel® Thermal Monitor.......................................................................................64 Digital Thermal Sensor .......................................................................................65 Figures 1 2 3 4 5 6 7 8 Processor Low Power State Machine ............................................................................
Revision History Revision Number -001 Datasheet Description • Initial Release Date October 2007 5
Datasheet
Intel® Celeron® Processor 200 Sequence Features • • • • Available at 1.
Datasheet
Introduction 1 Introduction The Intel® Celeron® processor 200 sequence is a desktop processor that combines the performance of the previous generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. The Intel Celeron processor 200 sequence is a 64-bit processor that maintains compatibility with IA-32 software.
Introduction 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Intel Celeron Processor 200 Sequence — Single core processor in the FC-BGA6 package with a 512 KB L2 cache. • Processor — For this document, the term processor is the generic form of the Intel Celeron processor 200 sequence. The processor is a single package that contains one exectution unit. • Keep-out zone — The area on or near the processor that system design can not use.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Intel® Celeron® Location Processor 200 Sequence Specification Update Intel® Celeron® Processor 200 Sequence Thermal and Mechanical Design Guidelines http:// developer.intel.com/ design/processor/ specupdt/318547.htm http:// developer.intel.com/ design/processor/ designex/318548.
Introduction 12 Datasheet
Low Power Features 2 Low Power Features 2.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Low Power Features Figure 1.
Low Power Features 2.2.2 Stop Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state.
Low Power Features 16 Datasheet
Electrical Specifications 3 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 3.1 Power and Ground Pins The processor has VCC (power), VCCP and VSS (ground) inputs for on-chip power distribution. All power pins must be connected to VCC, while all VSS pins must be connected to a system ground plane.
Electrical Specifications 3.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 3.
Electrical Specifications Table 2. Datasheet Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 0 0 0 1 1 0 1 1.3375 0 0 0 1 1 1 0 1.3250 0 0 0 1 1 1 1 1.3125 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 0 0 1 0 1 0 1 1.2375 0 0 1 0 1 1 0 1.
Electrical Specifications Table 2. 20 Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.
Electrical Specifications Table 2. Datasheet Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000 1 1 0 0 0 0 1 0.2875 1 1 0 0 0 1 0 0.2750 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 1 1 0 0 1 0 1 0.2375 1 1 0 0 1 1 0 0.
Electrical Specifications 3.4 Catastrophic Thermal Protection The Celeron processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor.
Electrical Specifications 3.7 Voltage and Current Specification 3.7.1 Absolute Maximum and Minimum Ratings Table 4 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 3.7.2 DC Voltage and Current Specification Table 5. Voltage and Current Specifications Symbol VID Range VCC Parameter VID Processor Number Core VCC 220 1.20 GHz VCC_BOOT Default VCC voltage for initial power up VCCA PLL VCC ICC Processor Number 220 VCCP ITT 1.20 GHz FSB termination voltage (DC + AC specifications) ICC for VCCP supply before VCC stable ICC for VCCP supply after VCC stable Notes2, 15 Min Typ Max Unit 1.0000 — 1.
Electrical Specifications Table 6. VCC Static and Transient Tolerance ICC (A) Voltage Deviation from VID Setting (V)1, 2, 3, 4 5.80 mΩ Maximum Voltage Typical Voltage Minimum Voltage 0 0.050 0.000 -0.050 2 0.038 -0.012 -0.062 4 0.027 -0.023 -0.073 6 0.015 -0.035 -0.085 8 0.004 -0.046 -0.096 10 -0.008 -0.058 -0.108 12 -0.020 -0.070 -0.120 14 -0.031 -0.081 -0.131 16 -0.043 -0.093 -0.143 18 -0.054 0.104 -0.154 20 -0.066 -0.116 -0.166 22 -0.078 -0.128 -0.
Electrical Specifications The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Intel(R) IMVP-6 Mobile Processor Voltage Regulation Specification for socket loadline guidelines and VR implementation details. 3.7.
Electrical Specifications 3.7.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_SENSE pins. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. 3.
Electrical Specifications Table 8.
Electrical Specifications Table 9.
Electrical Specifications 3.8.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads), unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 11. GTL+ Signal Group DC Specifications Symbol Min Max Unit Notes1 VIL Input Low Voltage -0.10 GTLREF – 0.10 V 2, 5 VIH Input High Voltage GTLREF + 0.10 VCCP + 0.10 V 3, 4, 5 VOH Output High Voltage VCCP – 0.
Electrical Specifications Table 13. CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 VCCP * 0.30 V 2, 3 VIH Input High Voltage VCCP * 0.70 VCCP + 0.10 V 4, 5, 3 VOL Output Low Voltage -0.10 VCCP * 0.10 V 3 VOH Output High Voltage 0.90 * VCCP VCCP + 0.10 V 6, 5, 3 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications 3.9 Clock Specifications 3.9.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The Celeron processor 200 sequence is available in a 479-pin Micro-FCBGA package shown in Figure 4. 4.1.1 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones.
Package Mechanical Specifications and Pin Information 4.1.3 Processor Mass Specifications The typical mass is given in Figure 4 and Table 16. This mass includes all the components that are included in the package. Table 16. Micro-FCBGA Package Mechanical Specifications Symbol B1 Min Max Unit Figure Package substrate width 34.95 35.05 mm Figure 4 34.95 B2 Package substrate length mm Figure 4 C1 Die width 11.1 mm Figure 4 C2 Die length 8.
Package Mechanical Specifications and Pin Information = Figure 4.
Package Mechanical Specifications and Pin Information Figure 5.
Package Mechanical Specifications and Pin Information 4.1.4 Processor Markings Figure 6 shows the topside markings on the processor. This diagram is to aid in the identification of the processor. Figure 6. Processor Top-Side Marking Example GRIP1LINE1 GRIP1LINE2 GRIP1LINE1: GRIP1LINE2: GRIP2LINE1: GRIP2LINE2: LE80557 220 {FPO} SLAF2 1.20/512/533 Intel {M}{C}06{e1} GRIP2LINE1 GRIP2LINE2 4.2 Processor Pinout and Pin List Figure 7 and Figure 8 show the top view pinout of the Celeron processor.
Package Mechanical Specifications and Pin Information Figure 7.
Package Mechanical Specifications and Pin Information Figure 8.
Package Mechanical Specifications and Pin Information Table 17. Pin Name 40 Pin Listing by Pin Name (Sheet 1 of 12) Pin # Table 17.
Package Mechanical Specifications and Pin Information Table 17. Datasheet Pin Listing by Pin Name (Sheet 3 of 12) Table 17.
Package Mechanical Specifications and Pin Information Table 17. Pin # Signal Buffer Type RSVD F6 RSVD M4 RSVD N5 Pin Name 42 Pin Listing by Pin Name (Sheet 5 of 12) Table 17.
Package Mechanical Specifications and Pin Information Table 17. Datasheet Pin Listing by Pin Name (Sheet 7 of 12) Pin Name Pin # Signal Buffer Type VCC B15 VCC VCC Table 17.
Package Mechanical Specifications and Pin Information Table 17. 44 Pin Listing by Pin Name (Sheet 9 of 12) Pin Name Pin # Signal Buffer Type VSS AB16 VSS AB19 VSS Table 17.
Package Mechanical Specifications and Pin Information Table 17. Datasheet Pin Listing by Pin Name (Sheet 11 of 12) Pin Name Pin # Signal Buffer Type VSS F5 Table 17.
Package Mechanical Specifications and Pin Information Table 18. Pin Name Signal Buffer Type A2 VSS Power/Other A3 SMI# CMOS A4 VSS Power/Other A5 FERR# Open Drain Output A6 A20M# CMOS Input A7 VCC A8 Table 18.
Package Mechanical Specifications and Pin Information Table 18. Datasheet Pin Listing by Pin Number (Sheet 3 of 12) Pin # Pin Name Signal Buffer Type D8 VSS Table 18.
Package Mechanical Specifications and Pin Information Table 18. 48 Pin Listing by Pin Number (Sheet 5 of 12) Table 18.
Package Mechanical Specifications and Pin Information Table 18. Datasheet Pin Listing by Pin Number (Sheet 7 of 12) Pin # Pin Name Signal Buffer Type R2 VSS Power/Other R3 A[19]# Source Synch R4 A[24]# Source Synch R5 VSS R6 VCCP R21 R22 Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin # 50 Pin Listing by Pin Number (Sheet 9 of 12) Pin Name Signal Buffer Type Direction Table 18.
Package Mechanical Specifications and Pin Information Table 18. Datasheet Pin Listing by Pin Number (Sheet 11 of Table 18.
Package Mechanical Specifications and Pin Information 4.3 Alphabetical Signals Reference Table 19. Signal Description (Sheet 1 of 8) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Celeron FSB.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 2 of 8) Name BPM[2:1]# BPM[3,0]# BPRI# BR0# Type Output Input/ Output Input Input/ Output Description BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Celeron FSB agents.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 3 of 8) Name Type Description DBR# Output DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 4 of 8) Name Type Description Data strobe used to latch in D[63:0]#. DSTBP[3:0]# FERR#/PBE# Input/ Output Output Signals Associated Strobe D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]# FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 5 of 8) Name INIT# Type Input Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 6 of 8) Name PWRGOOD Type Input Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 7 of 8) Name Type Description STPCLK# Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state.
Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 8 of 8) Name VCC_SENSE VID[6:0] VSS_SENSE Type Description Output VCC_SENSE together with VSS_SENSE are voltage feedback signals to IMVP 6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense or measure power near the silicon with little noise. Output VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC).
Package Mechanical Specifications and Pin Information 60 Datasheet
Thermal Specifications 5 Thermal Specifications A complete thermal solution includes both component and system level thermal management features. The Celeron processor requires a thermal solution to maintain temperatures within operating limits. Caution: Any attempt to operate the processor outside operating limits may result in permanent damage to the processor and potentially other components in the system.
Thermal Specifications 5.2 Processor Thermal Features 5.2.1 Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications.
Thermal Specifications used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 5.2.3 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature.
Thermal Specifications 5.4 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.
Thermal Specifications Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#.
Thermal Specifications § 66 Datasheet
