Datasheet

Low Power Features
14 Datasheet
2.2.1 Normal State
This is the normal operating state for the processor.
2.2.1.1 HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted, however, the other processor continues normal operation.
The processor will transition to the Normal state upon the occurrence of SMI#, INIT#,
or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize
itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system de-asserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT Power Down state, the processor will process bus snoops.
Figure 1. Processor Low Power State Machine
Normal State
- Normal Execution
Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Stop Grant Snoop State
-BCLK running
- Service Snoops to caches
HALT Snoop State
-BCLK running
- Service Snoops to caches
HALT State
-BCLK running
- Snoops and interrupts
allowed
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
INIT#, BINT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
STPCLK#
Asserted
STPCLK#
De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Snoop
Event
Occurs
Snoop
Event
Serviced
Snoop Event Occurs
Snoop Event Serviced